ci_hdrc_msm.c 7.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /* Copyright (c) 2010, Code Aurora Forum. All rights reserved. */
  3. #include <linux/module.h>
  4. #include <linux/platform_device.h>
  5. #include <linux/pm_runtime.h>
  6. #include <linux/usb/chipidea.h>
  7. #include <linux/clk.h>
  8. #include <linux/reset.h>
  9. #include <linux/mfd/syscon.h>
  10. #include <linux/regmap.h>
  11. #include <linux/io.h>
  12. #include <linux/reset-controller.h>
  13. #include <linux/extcon.h>
  14. #include <linux/of.h>
  15. #include "ci.h"
  16. #define HS_PHY_AHB_MODE 0x0098
  17. #define HS_PHY_GENCONFIG 0x009c
  18. #define HS_PHY_TXFIFO_IDLE_FORCE_DIS BIT(4)
  19. #define HS_PHY_GENCONFIG_2 0x00a0
  20. #define HS_PHY_SESS_VLD_CTRL_EN BIT(7)
  21. #define HS_PHY_ULPI_TX_PKT_EN_CLR_FIX BIT(19)
  22. #define HSPHY_SESS_VLD_CTRL BIT(25)
  23. /* Vendor base starts at 0x200 beyond CI base */
  24. #define HS_PHY_CTRL 0x0040
  25. #define HS_PHY_SEC_CTRL 0x0078
  26. #define HS_PHY_DIG_CLAMP_N BIT(16)
  27. #define HS_PHY_POR_ASSERT BIT(0)
  28. struct ci_hdrc_msm {
  29. struct platform_device *ci;
  30. struct clk *core_clk;
  31. struct clk *iface_clk;
  32. struct clk *fs_clk;
  33. struct ci_hdrc_platform_data pdata;
  34. struct reset_controller_dev rcdev;
  35. bool secondary_phy;
  36. bool hsic;
  37. void __iomem *base;
  38. };
  39. static int
  40. ci_hdrc_msm_por_reset(struct reset_controller_dev *r, unsigned long id)
  41. {
  42. struct ci_hdrc_msm *ci_msm = container_of(r, struct ci_hdrc_msm, rcdev);
  43. void __iomem *addr = ci_msm->base;
  44. u32 val;
  45. if (id)
  46. addr += HS_PHY_SEC_CTRL;
  47. else
  48. addr += HS_PHY_CTRL;
  49. val = readl_relaxed(addr);
  50. val |= HS_PHY_POR_ASSERT;
  51. writel(val, addr);
  52. /*
  53. * wait for minimum 10 microseconds as suggested by manual.
  54. * Use a slightly larger value since the exact value didn't
  55. * work 100% of the time.
  56. */
  57. udelay(12);
  58. val &= ~HS_PHY_POR_ASSERT;
  59. writel(val, addr);
  60. return 0;
  61. }
  62. static const struct reset_control_ops ci_hdrc_msm_reset_ops = {
  63. .reset = ci_hdrc_msm_por_reset,
  64. };
  65. static int ci_hdrc_msm_notify_event(struct ci_hdrc *ci, unsigned event)
  66. {
  67. struct device *dev = ci->dev->parent;
  68. struct ci_hdrc_msm *msm_ci = dev_get_drvdata(dev);
  69. int ret;
  70. switch (event) {
  71. case CI_HDRC_CONTROLLER_RESET_EVENT:
  72. dev_dbg(dev, "CI_HDRC_CONTROLLER_RESET_EVENT received\n");
  73. hw_phymode_configure(ci);
  74. if (msm_ci->secondary_phy) {
  75. u32 val = readl_relaxed(msm_ci->base + HS_PHY_SEC_CTRL);
  76. val |= HS_PHY_DIG_CLAMP_N;
  77. writel_relaxed(val, msm_ci->base + HS_PHY_SEC_CTRL);
  78. }
  79. ret = phy_init(ci->phy);
  80. if (ret)
  81. return ret;
  82. ret = phy_power_on(ci->phy);
  83. if (ret) {
  84. phy_exit(ci->phy);
  85. return ret;
  86. }
  87. /* use AHB transactor, allow posted data writes */
  88. hw_write_id_reg(ci, HS_PHY_AHB_MODE, 0xffffffff, 0x8);
  89. /* workaround for rx buffer collision issue */
  90. hw_write_id_reg(ci, HS_PHY_GENCONFIG,
  91. HS_PHY_TXFIFO_IDLE_FORCE_DIS, 0);
  92. if (!msm_ci->hsic)
  93. hw_write_id_reg(ci, HS_PHY_GENCONFIG_2,
  94. HS_PHY_ULPI_TX_PKT_EN_CLR_FIX, 0);
  95. if (!IS_ERR(ci->platdata->vbus_extcon.edev) || ci->role_switch) {
  96. hw_write_id_reg(ci, HS_PHY_GENCONFIG_2,
  97. HS_PHY_SESS_VLD_CTRL_EN,
  98. HS_PHY_SESS_VLD_CTRL_EN);
  99. hw_write(ci, OP_USBCMD, HSPHY_SESS_VLD_CTRL,
  100. HSPHY_SESS_VLD_CTRL);
  101. }
  102. break;
  103. case CI_HDRC_CONTROLLER_STOPPED_EVENT:
  104. dev_dbg(dev, "CI_HDRC_CONTROLLER_STOPPED_EVENT received\n");
  105. phy_power_off(ci->phy);
  106. phy_exit(ci->phy);
  107. break;
  108. default:
  109. dev_dbg(dev, "unknown ci_hdrc event\n");
  110. break;
  111. }
  112. return 0;
  113. }
  114. static int ci_hdrc_msm_mux_phy(struct ci_hdrc_msm *ci,
  115. struct platform_device *pdev)
  116. {
  117. struct regmap *regmap;
  118. struct device *dev = &pdev->dev;
  119. struct of_phandle_args args;
  120. u32 val;
  121. int ret;
  122. ret = of_parse_phandle_with_fixed_args(dev->of_node, "phy-select", 2, 0,
  123. &args);
  124. if (ret)
  125. return 0;
  126. regmap = syscon_node_to_regmap(args.np);
  127. of_node_put(args.np);
  128. if (IS_ERR(regmap))
  129. return PTR_ERR(regmap);
  130. ret = regmap_write(regmap, args.args[0], args.args[1]);
  131. if (ret)
  132. return ret;
  133. ci->secondary_phy = !!args.args[1];
  134. if (ci->secondary_phy) {
  135. val = readl_relaxed(ci->base + HS_PHY_SEC_CTRL);
  136. val |= HS_PHY_DIG_CLAMP_N;
  137. writel_relaxed(val, ci->base + HS_PHY_SEC_CTRL);
  138. }
  139. return 0;
  140. }
  141. static int ci_hdrc_msm_probe(struct platform_device *pdev)
  142. {
  143. struct ci_hdrc_msm *ci;
  144. struct platform_device *plat_ci;
  145. struct clk *clk;
  146. struct reset_control *reset;
  147. int ret;
  148. struct device_node *ulpi_node, *phy_node;
  149. dev_dbg(&pdev->dev, "ci_hdrc_msm_probe\n");
  150. ci = devm_kzalloc(&pdev->dev, sizeof(*ci), GFP_KERNEL);
  151. if (!ci)
  152. return -ENOMEM;
  153. platform_set_drvdata(pdev, ci);
  154. ci->pdata.name = "ci_hdrc_msm";
  155. ci->pdata.capoffset = DEF_CAPOFFSET;
  156. ci->pdata.flags = CI_HDRC_REGS_SHARED | CI_HDRC_DISABLE_STREAMING |
  157. CI_HDRC_OVERRIDE_AHB_BURST |
  158. CI_HDRC_OVERRIDE_PHY_CONTROL;
  159. ci->pdata.notify_event = ci_hdrc_msm_notify_event;
  160. reset = devm_reset_control_get(&pdev->dev, "core");
  161. if (IS_ERR(reset))
  162. return PTR_ERR(reset);
  163. ci->core_clk = clk = devm_clk_get(&pdev->dev, "core");
  164. if (IS_ERR(clk))
  165. return PTR_ERR(clk);
  166. ci->iface_clk = clk = devm_clk_get(&pdev->dev, "iface");
  167. if (IS_ERR(clk))
  168. return PTR_ERR(clk);
  169. ci->fs_clk = clk = devm_clk_get_optional(&pdev->dev, "fs");
  170. if (IS_ERR(clk))
  171. return PTR_ERR(clk);
  172. ci->base = devm_platform_ioremap_resource(pdev, 1);
  173. if (IS_ERR(ci->base))
  174. return PTR_ERR(ci->base);
  175. ci->rcdev.owner = THIS_MODULE;
  176. ci->rcdev.ops = &ci_hdrc_msm_reset_ops;
  177. ci->rcdev.of_node = pdev->dev.of_node;
  178. ci->rcdev.nr_resets = 2;
  179. ret = devm_reset_controller_register(&pdev->dev, &ci->rcdev);
  180. if (ret)
  181. return ret;
  182. ret = clk_prepare_enable(ci->fs_clk);
  183. if (ret)
  184. return ret;
  185. reset_control_assert(reset);
  186. usleep_range(10000, 12000);
  187. reset_control_deassert(reset);
  188. clk_disable_unprepare(ci->fs_clk);
  189. ret = clk_prepare_enable(ci->core_clk);
  190. if (ret)
  191. return ret;
  192. ret = clk_prepare_enable(ci->iface_clk);
  193. if (ret)
  194. goto err_iface;
  195. ret = ci_hdrc_msm_mux_phy(ci, pdev);
  196. if (ret)
  197. goto err_mux;
  198. ulpi_node = of_get_child_by_name(pdev->dev.of_node, "ulpi");
  199. if (ulpi_node) {
  200. phy_node = of_get_next_available_child(ulpi_node, NULL);
  201. ci->hsic = of_device_is_compatible(phy_node, "qcom,usb-hsic-phy");
  202. of_node_put(phy_node);
  203. }
  204. of_node_put(ulpi_node);
  205. plat_ci = ci_hdrc_add_device(&pdev->dev, pdev->resource,
  206. pdev->num_resources, &ci->pdata);
  207. if (IS_ERR(plat_ci)) {
  208. ret = PTR_ERR(plat_ci);
  209. if (ret != -EPROBE_DEFER)
  210. dev_err(&pdev->dev, "ci_hdrc_add_device failed!\n");
  211. goto err_mux;
  212. }
  213. ci->ci = plat_ci;
  214. pm_runtime_set_active(&pdev->dev);
  215. pm_runtime_no_callbacks(&pdev->dev);
  216. pm_runtime_enable(&pdev->dev);
  217. return 0;
  218. err_mux:
  219. clk_disable_unprepare(ci->iface_clk);
  220. err_iface:
  221. clk_disable_unprepare(ci->core_clk);
  222. return ret;
  223. }
  224. static int ci_hdrc_msm_remove(struct platform_device *pdev)
  225. {
  226. struct ci_hdrc_msm *ci = platform_get_drvdata(pdev);
  227. pm_runtime_disable(&pdev->dev);
  228. ci_hdrc_remove_device(ci->ci);
  229. clk_disable_unprepare(ci->iface_clk);
  230. clk_disable_unprepare(ci->core_clk);
  231. return 0;
  232. }
  233. static const struct of_device_id msm_ci_dt_match[] = {
  234. { .compatible = "qcom,ci-hdrc", },
  235. { }
  236. };
  237. MODULE_DEVICE_TABLE(of, msm_ci_dt_match);
  238. static struct platform_driver ci_hdrc_msm_driver = {
  239. .probe = ci_hdrc_msm_probe,
  240. .remove = ci_hdrc_msm_remove,
  241. .driver = {
  242. .name = "msm_hsusb",
  243. .of_match_table = msm_ci_dt_match,
  244. },
  245. };
  246. module_platform_driver(ci_hdrc_msm_driver);
  247. MODULE_ALIAS("platform:msm_hsusb");
  248. MODULE_ALIAS("platform:ci13xxx_msm");
  249. MODULE_LICENSE("GPL v2");