c67x00.h 8.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * c67x00.h: Cypress C67X00 USB register and field definitions
  4. *
  5. * Copyright (C) 2006-2008 Barco N.V.
  6. * Derived from the Cypress cy7c67200/300 ezusb linux driver and
  7. * based on multiple host controller drivers inside the linux kernel.
  8. */
  9. #ifndef _USB_C67X00_H
  10. #define _USB_C67X00_H
  11. #include <linux/spinlock.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/completion.h>
  14. #include <linux/mutex.h>
  15. /* ---------------------------------------------------------------------
  16. * Cypress C67x00 register definitions
  17. */
  18. /* Hardware Revision Register */
  19. #define HW_REV_REG 0xC004
  20. /* General USB registers */
  21. /* ===================== */
  22. /* USB Control Register */
  23. #define USB_CTL_REG(x) ((x) ? 0xC0AA : 0xC08A)
  24. #define LOW_SPEED_PORT(x) ((x) ? 0x0800 : 0x0400)
  25. #define HOST_MODE 0x0200
  26. #define PORT_RES_EN(x) ((x) ? 0x0100 : 0x0080)
  27. #define SOF_EOP_EN(x) ((x) ? 0x0002 : 0x0001)
  28. /* USB status register - Notice it has different content in hcd/udc mode */
  29. #define USB_STAT_REG(x) ((x) ? 0xC0B0 : 0xC090)
  30. #define EP0_IRQ_FLG 0x0001
  31. #define EP1_IRQ_FLG 0x0002
  32. #define EP2_IRQ_FLG 0x0004
  33. #define EP3_IRQ_FLG 0x0008
  34. #define EP4_IRQ_FLG 0x0010
  35. #define EP5_IRQ_FLG 0x0020
  36. #define EP6_IRQ_FLG 0x0040
  37. #define EP7_IRQ_FLG 0x0080
  38. #define RESET_IRQ_FLG 0x0100
  39. #define SOF_EOP_IRQ_FLG 0x0200
  40. #define ID_IRQ_FLG 0x4000
  41. #define VBUS_IRQ_FLG 0x8000
  42. /* USB Host only registers */
  43. /* ======================= */
  44. /* Host n Control Register */
  45. #define HOST_CTL_REG(x) ((x) ? 0xC0A0 : 0xC080)
  46. #define PREAMBLE_EN 0x0080 /* Preamble enable */
  47. #define SEQ_SEL 0x0040 /* Data Toggle Sequence Bit Select */
  48. #define ISO_EN 0x0010 /* Isochronous enable */
  49. #define ARM_EN 0x0001 /* Arm operation */
  50. /* Host n Interrupt Enable Register */
  51. #define HOST_IRQ_EN_REG(x) ((x) ? 0xC0AC : 0xC08C)
  52. #define SOF_EOP_IRQ_EN 0x0200 /* SOF/EOP Interrupt Enable */
  53. #define SOF_EOP_TMOUT_IRQ_EN 0x0800 /* SOF/EOP Timeout Interrupt Enable */
  54. #define ID_IRQ_EN 0x4000 /* ID interrupt enable */
  55. #define VBUS_IRQ_EN 0x8000 /* VBUS interrupt enable */
  56. #define DONE_IRQ_EN 0x0001 /* Done Interrupt Enable */
  57. /* USB status register */
  58. #define HOST_STAT_MASK 0x02FD
  59. #define PORT_CONNECT_CHANGE(x) ((x) ? 0x0020 : 0x0010)
  60. #define PORT_SE0_STATUS(x) ((x) ? 0x0008 : 0x0004)
  61. /* Host Frame Register */
  62. #define HOST_FRAME_REG(x) ((x) ? 0xC0B6 : 0xC096)
  63. #define HOST_FRAME_MASK 0x07FF
  64. /* USB Peripheral only registers */
  65. /* ============================= */
  66. /* Device n Port Sel reg */
  67. #define DEVICE_N_PORT_SEL(x) ((x) ? 0xC0A4 : 0xC084)
  68. /* Device n Interrupt Enable Register */
  69. #define DEVICE_N_IRQ_EN_REG(x) ((x) ? 0xC0AC : 0xC08C)
  70. #define DEVICE_N_ENDPOINT_N_CTL_REG(dev, ep) ((dev) \
  71. ? (0x0280 + (ep << 4)) \
  72. : (0x0200 + (ep << 4)))
  73. #define DEVICE_N_ENDPOINT_N_STAT_REG(dev, ep) ((dev) \
  74. ? (0x0286 + (ep << 4)) \
  75. : (0x0206 + (ep << 4)))
  76. #define DEVICE_N_ADDRESS(dev) ((dev) ? (0xC0AE) : (0xC08E))
  77. /* HPI registers */
  78. /* ============= */
  79. /* HPI Status register */
  80. #define SOFEOP_FLG(x) (1 << ((x) ? 12 : 10))
  81. #define SIEMSG_FLG(x) (1 << (4 + (x)))
  82. #define RESET_FLG(x) ((x) ? 0x0200 : 0x0002)
  83. #define DONE_FLG(x) (1 << (2 + (x)))
  84. #define RESUME_FLG(x) (1 << (6 + (x)))
  85. #define MBX_OUT_FLG 0x0001 /* Message out available */
  86. #define MBX_IN_FLG 0x0100
  87. #define ID_FLG 0x4000
  88. #define VBUS_FLG 0x8000
  89. /* Interrupt routing register */
  90. #define HPI_IRQ_ROUTING_REG 0x0142
  91. #define HPI_SWAP_ENABLE(x) ((x) ? 0x0100 : 0x0001)
  92. #define RESET_TO_HPI_ENABLE(x) ((x) ? 0x0200 : 0x0002)
  93. #define DONE_TO_HPI_ENABLE(x) ((x) ? 0x0008 : 0x0004)
  94. #define RESUME_TO_HPI_ENABLE(x) ((x) ? 0x0080 : 0x0040)
  95. #define SOFEOP_TO_HPI_EN(x) ((x) ? 0x2000 : 0x0800)
  96. #define SOFEOP_TO_CPU_EN(x) ((x) ? 0x1000 : 0x0400)
  97. #define ID_TO_HPI_ENABLE 0x4000
  98. #define VBUS_TO_HPI_ENABLE 0x8000
  99. /* SIE msg registers */
  100. #define SIEMSG_REG(x) ((x) ? 0x0148 : 0x0144)
  101. #define HUSB_TDListDone 0x1000
  102. #define SUSB_EP0_MSG 0x0001
  103. #define SUSB_EP1_MSG 0x0002
  104. #define SUSB_EP2_MSG 0x0004
  105. #define SUSB_EP3_MSG 0x0008
  106. #define SUSB_EP4_MSG 0x0010
  107. #define SUSB_EP5_MSG 0x0020
  108. #define SUSB_EP6_MSG 0x0040
  109. #define SUSB_EP7_MSG 0x0080
  110. #define SUSB_RST_MSG 0x0100
  111. #define SUSB_SOF_MSG 0x0200
  112. #define SUSB_CFG_MSG 0x0400
  113. #define SUSB_SUS_MSG 0x0800
  114. #define SUSB_ID_MSG 0x4000
  115. #define SUSB_VBUS_MSG 0x8000
  116. /* BIOS interrupt routines */
  117. #define SUSBx_RECEIVE_INT(x) ((x) ? 97 : 81)
  118. #define SUSBx_SEND_INT(x) ((x) ? 96 : 80)
  119. #define SUSBx_DEV_DESC_VEC(x) ((x) ? 0x00D4 : 0x00B4)
  120. #define SUSBx_CONF_DESC_VEC(x) ((x) ? 0x00D6 : 0x00B6)
  121. #define SUSBx_STRING_DESC_VEC(x) ((x) ? 0x00D8 : 0x00B8)
  122. #define CY_HCD_BUF_ADDR 0x500 /* Base address for host */
  123. #define SIE_TD_SIZE 0x200 /* size of the td list */
  124. #define SIE_TD_BUF_SIZE 0x400 /* size of the data buffer */
  125. #define SIE_TD_OFFSET(host) ((host) ? (SIE_TD_SIZE+SIE_TD_BUF_SIZE) : 0)
  126. #define SIE_BUF_OFFSET(host) (SIE_TD_OFFSET(host) + SIE_TD_SIZE)
  127. /* Base address of HCD + 2 x TD_SIZE + 2 x TD_BUF_SIZE */
  128. #define CY_UDC_REQ_HEADER_BASE 0x1100
  129. /* 8- byte request headers for IN/OUT transfers */
  130. #define CY_UDC_REQ_HEADER_SIZE 8
  131. #define CY_UDC_REQ_HEADER_ADDR(ep_num) (CY_UDC_REQ_HEADER_BASE + \
  132. ((ep_num) * CY_UDC_REQ_HEADER_SIZE))
  133. #define CY_UDC_DESC_BASE_ADDRESS (CY_UDC_REQ_HEADER_ADDR(8))
  134. #define CY_UDC_BIOS_REPLACE_BASE 0x1800
  135. #define CY_UDC_REQ_BUFFER_BASE 0x2000
  136. #define CY_UDC_REQ_BUFFER_SIZE 0x0400
  137. #define CY_UDC_REQ_BUFFER_ADDR(ep_num) (CY_UDC_REQ_BUFFER_BASE + \
  138. ((ep_num) * CY_UDC_REQ_BUFFER_SIZE))
  139. /* ---------------------------------------------------------------------
  140. * Driver data structures
  141. */
  142. struct c67x00_device;
  143. /**
  144. * struct c67x00_sie - Common data associated with a SIE
  145. * @lock: lock to protect this struct and the associated chip registers
  146. * @private_data: subdriver dependent data
  147. * @irq: subdriver dependent irq handler, set NULL when not used
  148. * @dev: link to common driver structure
  149. * @sie_num: SIE number on chip, starting from 0
  150. * @mode: SIE mode (host/peripheral/otg/not used)
  151. */
  152. struct c67x00_sie {
  153. /* Entries to be used by the subdrivers */
  154. spinlock_t lock; /* protect this structure */
  155. void *private_data;
  156. void (*irq) (struct c67x00_sie *sie, u16 int_status, u16 msg);
  157. /* Read only: */
  158. struct c67x00_device *dev;
  159. int sie_num;
  160. int mode;
  161. };
  162. #define sie_dev(s) (&(s)->dev->pdev->dev)
  163. /**
  164. * struct c67x00_lcp
  165. */
  166. struct c67x00_lcp {
  167. /* Internal use only */
  168. struct mutex mutex;
  169. struct completion msg_received;
  170. u16 last_msg;
  171. };
  172. /*
  173. * struct c67x00_hpi
  174. */
  175. struct c67x00_hpi {
  176. void __iomem *base;
  177. int regstep;
  178. spinlock_t lock;
  179. struct c67x00_lcp lcp;
  180. };
  181. #define C67X00_SIES 2
  182. #define C67X00_PORTS 2
  183. /**
  184. * struct c67x00_device - Common data associated with a c67x00 instance
  185. * @hpi: hpi addresses
  186. * @sie: array of sie's on this chip
  187. * @pdev: platform device of instance
  188. * @pdata: configuration provided by the platform
  189. */
  190. struct c67x00_device {
  191. struct c67x00_hpi hpi;
  192. struct c67x00_sie sie[C67X00_SIES];
  193. struct platform_device *pdev;
  194. struct c67x00_platform_data *pdata;
  195. };
  196. /* ---------------------------------------------------------------------
  197. * Low level interface functions
  198. */
  199. /* Host Port Interface (HPI) functions */
  200. u16 c67x00_ll_hpi_status(struct c67x00_device *dev);
  201. void c67x00_ll_hpi_reg_init(struct c67x00_device *dev);
  202. void c67x00_ll_hpi_enable_sofeop(struct c67x00_sie *sie);
  203. void c67x00_ll_hpi_disable_sofeop(struct c67x00_sie *sie);
  204. /* General functions */
  205. u16 c67x00_ll_fetch_siemsg(struct c67x00_device *dev, int sie_num);
  206. u16 c67x00_ll_get_usb_ctl(struct c67x00_sie *sie);
  207. void c67x00_ll_usb_clear_status(struct c67x00_sie *sie, u16 bits);
  208. u16 c67x00_ll_usb_get_status(struct c67x00_sie *sie);
  209. void c67x00_ll_write_mem_le16(struct c67x00_device *dev, u16 addr,
  210. void *data, int len);
  211. void c67x00_ll_read_mem_le16(struct c67x00_device *dev, u16 addr,
  212. void *data, int len);
  213. /* Host specific functions */
  214. void c67x00_ll_set_husb_eot(struct c67x00_device *dev, u16 value);
  215. void c67x00_ll_husb_reset(struct c67x00_sie *sie, int port);
  216. void c67x00_ll_husb_set_current_td(struct c67x00_sie *sie, u16 addr);
  217. u16 c67x00_ll_husb_get_current_td(struct c67x00_sie *sie);
  218. u16 c67x00_ll_husb_get_frame(struct c67x00_sie *sie);
  219. void c67x00_ll_husb_init_host_port(struct c67x00_sie *sie);
  220. void c67x00_ll_husb_reset_port(struct c67x00_sie *sie, int port);
  221. /* Called by c67x00_irq to handle lcp interrupts */
  222. void c67x00_ll_irq(struct c67x00_device *dev, u16 int_status);
  223. /* Setup and teardown */
  224. void c67x00_ll_init(struct c67x00_device *dev);
  225. void c67x00_ll_release(struct c67x00_device *dev);
  226. int c67x00_ll_reset(struct c67x00_device *dev);
  227. #endif /* _USB_C67X00_H */