c67x00-ll-hpi.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * c67x00-ll-hpi.c: Cypress C67X00 USB Low level interface using HPI
  4. *
  5. * Copyright (C) 2006-2008 Barco N.V.
  6. * Derived from the Cypress cy7c67200/300 ezusb linux driver and
  7. * based on multiple host controller drivers inside the linux kernel.
  8. */
  9. #include <asm/byteorder.h>
  10. #include <linux/delay.h>
  11. #include <linux/io.h>
  12. #include <linux/jiffies.h>
  13. #include <linux/usb/c67x00.h>
  14. #include "c67x00.h"
  15. #define COMM_REGS 14
  16. struct c67x00_lcp_int_data {
  17. u16 regs[COMM_REGS];
  18. };
  19. /* -------------------------------------------------------------------------- */
  20. /* Interface definitions */
  21. #define COMM_ACK 0x0FED
  22. #define COMM_NAK 0xDEAD
  23. #define COMM_RESET 0xFA50
  24. #define COMM_EXEC_INT 0xCE01
  25. #define COMM_INT_NUM 0x01C2
  26. /* Registers 0 to COMM_REGS-1 */
  27. #define COMM_R(x) (0x01C4 + 2 * (x))
  28. #define HUSB_SIE_pCurrentTDPtr(x) ((x) ? 0x01B2 : 0x01B0)
  29. #define HUSB_SIE_pTDListDone_Sem(x) ((x) ? 0x01B8 : 0x01B6)
  30. #define HUSB_pEOT 0x01B4
  31. /* Software interrupts */
  32. /* 114, 115: */
  33. #define HUSB_SIE_INIT_INT(x) ((x) ? 0x0073 : 0x0072)
  34. #define HUSB_RESET_INT 0x0074
  35. #define SUSB_INIT_INT 0x0071
  36. #define SUSB_INIT_INT_LOC (SUSB_INIT_INT * 2)
  37. /* -----------------------------------------------------------------------
  38. * HPI implementation
  39. *
  40. * The c67x00 chip also support control via SPI or HSS serial
  41. * interfaces. However, this driver assumes that register access can
  42. * be performed from IRQ context. While this is a safe assumption with
  43. * the HPI interface, it is not true for the serial interfaces.
  44. */
  45. /* HPI registers */
  46. #define HPI_DATA 0
  47. #define HPI_MAILBOX 1
  48. #define HPI_ADDR 2
  49. #define HPI_STATUS 3
  50. /*
  51. * According to CY7C67300 specification (tables 140 and 141) HPI read and
  52. * write cycle duration Tcyc must be at least 6T long, where T is 1/48MHz,
  53. * which is 125ns.
  54. */
  55. #define HPI_T_CYC_NS 125
  56. static inline u16 hpi_read_reg(struct c67x00_device *dev, int reg)
  57. {
  58. ndelay(HPI_T_CYC_NS);
  59. return __raw_readw(dev->hpi.base + reg * dev->hpi.regstep);
  60. }
  61. static inline void hpi_write_reg(struct c67x00_device *dev, int reg, u16 value)
  62. {
  63. ndelay(HPI_T_CYC_NS);
  64. __raw_writew(value, dev->hpi.base + reg * dev->hpi.regstep);
  65. }
  66. static inline u16 hpi_read_word_nolock(struct c67x00_device *dev, u16 reg)
  67. {
  68. hpi_write_reg(dev, HPI_ADDR, reg);
  69. return hpi_read_reg(dev, HPI_DATA);
  70. }
  71. static u16 hpi_read_word(struct c67x00_device *dev, u16 reg)
  72. {
  73. u16 value;
  74. unsigned long flags;
  75. spin_lock_irqsave(&dev->hpi.lock, flags);
  76. value = hpi_read_word_nolock(dev, reg);
  77. spin_unlock_irqrestore(&dev->hpi.lock, flags);
  78. return value;
  79. }
  80. static void hpi_write_word_nolock(struct c67x00_device *dev, u16 reg, u16 value)
  81. {
  82. hpi_write_reg(dev, HPI_ADDR, reg);
  83. hpi_write_reg(dev, HPI_DATA, value);
  84. }
  85. static void hpi_write_word(struct c67x00_device *dev, u16 reg, u16 value)
  86. {
  87. unsigned long flags;
  88. spin_lock_irqsave(&dev->hpi.lock, flags);
  89. hpi_write_word_nolock(dev, reg, value);
  90. spin_unlock_irqrestore(&dev->hpi.lock, flags);
  91. }
  92. /*
  93. * Only data is little endian, addr has cpu endianess
  94. */
  95. static void hpi_write_words_le16(struct c67x00_device *dev, u16 addr,
  96. __le16 *data, u16 count)
  97. {
  98. unsigned long flags;
  99. int i;
  100. spin_lock_irqsave(&dev->hpi.lock, flags);
  101. hpi_write_reg(dev, HPI_ADDR, addr);
  102. for (i = 0; i < count; i++)
  103. hpi_write_reg(dev, HPI_DATA, le16_to_cpu(*data++));
  104. spin_unlock_irqrestore(&dev->hpi.lock, flags);
  105. }
  106. /*
  107. * Only data is little endian, addr has cpu endianess
  108. */
  109. static void hpi_read_words_le16(struct c67x00_device *dev, u16 addr,
  110. __le16 *data, u16 count)
  111. {
  112. unsigned long flags;
  113. int i;
  114. spin_lock_irqsave(&dev->hpi.lock, flags);
  115. hpi_write_reg(dev, HPI_ADDR, addr);
  116. for (i = 0; i < count; i++)
  117. *data++ = cpu_to_le16(hpi_read_reg(dev, HPI_DATA));
  118. spin_unlock_irqrestore(&dev->hpi.lock, flags);
  119. }
  120. static void hpi_set_bits(struct c67x00_device *dev, u16 reg, u16 mask)
  121. {
  122. u16 value;
  123. unsigned long flags;
  124. spin_lock_irqsave(&dev->hpi.lock, flags);
  125. value = hpi_read_word_nolock(dev, reg);
  126. hpi_write_word_nolock(dev, reg, value | mask);
  127. spin_unlock_irqrestore(&dev->hpi.lock, flags);
  128. }
  129. static void hpi_clear_bits(struct c67x00_device *dev, u16 reg, u16 mask)
  130. {
  131. u16 value;
  132. unsigned long flags;
  133. spin_lock_irqsave(&dev->hpi.lock, flags);
  134. value = hpi_read_word_nolock(dev, reg);
  135. hpi_write_word_nolock(dev, reg, value & ~mask);
  136. spin_unlock_irqrestore(&dev->hpi.lock, flags);
  137. }
  138. static u16 hpi_recv_mbox(struct c67x00_device *dev)
  139. {
  140. u16 value;
  141. unsigned long flags;
  142. spin_lock_irqsave(&dev->hpi.lock, flags);
  143. value = hpi_read_reg(dev, HPI_MAILBOX);
  144. spin_unlock_irqrestore(&dev->hpi.lock, flags);
  145. return value;
  146. }
  147. static u16 hpi_send_mbox(struct c67x00_device *dev, u16 value)
  148. {
  149. unsigned long flags;
  150. spin_lock_irqsave(&dev->hpi.lock, flags);
  151. hpi_write_reg(dev, HPI_MAILBOX, value);
  152. spin_unlock_irqrestore(&dev->hpi.lock, flags);
  153. return value;
  154. }
  155. u16 c67x00_ll_hpi_status(struct c67x00_device *dev)
  156. {
  157. u16 value;
  158. unsigned long flags;
  159. spin_lock_irqsave(&dev->hpi.lock, flags);
  160. value = hpi_read_reg(dev, HPI_STATUS);
  161. spin_unlock_irqrestore(&dev->hpi.lock, flags);
  162. return value;
  163. }
  164. void c67x00_ll_hpi_reg_init(struct c67x00_device *dev)
  165. {
  166. int i;
  167. hpi_recv_mbox(dev);
  168. c67x00_ll_hpi_status(dev);
  169. hpi_write_word(dev, HPI_IRQ_ROUTING_REG, 0);
  170. for (i = 0; i < C67X00_SIES; i++) {
  171. hpi_write_word(dev, SIEMSG_REG(i), 0);
  172. hpi_read_word(dev, SIEMSG_REG(i));
  173. }
  174. }
  175. void c67x00_ll_hpi_enable_sofeop(struct c67x00_sie *sie)
  176. {
  177. hpi_set_bits(sie->dev, HPI_IRQ_ROUTING_REG,
  178. SOFEOP_TO_HPI_EN(sie->sie_num));
  179. }
  180. void c67x00_ll_hpi_disable_sofeop(struct c67x00_sie *sie)
  181. {
  182. hpi_clear_bits(sie->dev, HPI_IRQ_ROUTING_REG,
  183. SOFEOP_TO_HPI_EN(sie->sie_num));
  184. }
  185. /* -------------------------------------------------------------------------- */
  186. /* Transactions */
  187. static inline int ll_recv_msg(struct c67x00_device *dev)
  188. {
  189. u16 res;
  190. res = wait_for_completion_timeout(&dev->hpi.lcp.msg_received, 5 * HZ);
  191. WARN_ON(!res);
  192. return (res == 0) ? -EIO : 0;
  193. }
  194. /* -------------------------------------------------------------------------- */
  195. /* General functions */
  196. u16 c67x00_ll_fetch_siemsg(struct c67x00_device *dev, int sie_num)
  197. {
  198. u16 val;
  199. val = hpi_read_word(dev, SIEMSG_REG(sie_num));
  200. /* clear register to allow next message */
  201. hpi_write_word(dev, SIEMSG_REG(sie_num), 0);
  202. return val;
  203. }
  204. u16 c67x00_ll_get_usb_ctl(struct c67x00_sie *sie)
  205. {
  206. return hpi_read_word(sie->dev, USB_CTL_REG(sie->sie_num));
  207. }
  208. /*
  209. * c67x00_ll_usb_clear_status - clear the USB status bits
  210. */
  211. void c67x00_ll_usb_clear_status(struct c67x00_sie *sie, u16 bits)
  212. {
  213. hpi_write_word(sie->dev, USB_STAT_REG(sie->sie_num), bits);
  214. }
  215. u16 c67x00_ll_usb_get_status(struct c67x00_sie *sie)
  216. {
  217. return hpi_read_word(sie->dev, USB_STAT_REG(sie->sie_num));
  218. }
  219. /* -------------------------------------------------------------------------- */
  220. static int c67x00_comm_exec_int(struct c67x00_device *dev, u16 nr,
  221. struct c67x00_lcp_int_data *data)
  222. {
  223. int i, rc;
  224. mutex_lock(&dev->hpi.lcp.mutex);
  225. hpi_write_word(dev, COMM_INT_NUM, nr);
  226. for (i = 0; i < COMM_REGS; i++)
  227. hpi_write_word(dev, COMM_R(i), data->regs[i]);
  228. hpi_send_mbox(dev, COMM_EXEC_INT);
  229. rc = ll_recv_msg(dev);
  230. mutex_unlock(&dev->hpi.lcp.mutex);
  231. return rc;
  232. }
  233. /* -------------------------------------------------------------------------- */
  234. /* Host specific functions */
  235. void c67x00_ll_set_husb_eot(struct c67x00_device *dev, u16 value)
  236. {
  237. mutex_lock(&dev->hpi.lcp.mutex);
  238. hpi_write_word(dev, HUSB_pEOT, value);
  239. mutex_unlock(&dev->hpi.lcp.mutex);
  240. }
  241. static inline void c67x00_ll_husb_sie_init(struct c67x00_sie *sie)
  242. {
  243. struct c67x00_device *dev = sie->dev;
  244. struct c67x00_lcp_int_data data;
  245. int rc;
  246. rc = c67x00_comm_exec_int(dev, HUSB_SIE_INIT_INT(sie->sie_num), &data);
  247. BUG_ON(rc); /* No return path for error code; crash spectacularly */
  248. }
  249. void c67x00_ll_husb_reset(struct c67x00_sie *sie, int port)
  250. {
  251. struct c67x00_device *dev = sie->dev;
  252. struct c67x00_lcp_int_data data;
  253. int rc;
  254. data.regs[0] = 50; /* Reset USB port for 50ms */
  255. data.regs[1] = port | (sie->sie_num << 1);
  256. rc = c67x00_comm_exec_int(dev, HUSB_RESET_INT, &data);
  257. BUG_ON(rc); /* No return path for error code; crash spectacularly */
  258. }
  259. void c67x00_ll_husb_set_current_td(struct c67x00_sie *sie, u16 addr)
  260. {
  261. hpi_write_word(sie->dev, HUSB_SIE_pCurrentTDPtr(sie->sie_num), addr);
  262. }
  263. u16 c67x00_ll_husb_get_current_td(struct c67x00_sie *sie)
  264. {
  265. return hpi_read_word(sie->dev, HUSB_SIE_pCurrentTDPtr(sie->sie_num));
  266. }
  267. u16 c67x00_ll_husb_get_frame(struct c67x00_sie *sie)
  268. {
  269. return hpi_read_word(sie->dev, HOST_FRAME_REG(sie->sie_num));
  270. }
  271. void c67x00_ll_husb_init_host_port(struct c67x00_sie *sie)
  272. {
  273. /* Set port into host mode */
  274. hpi_set_bits(sie->dev, USB_CTL_REG(sie->sie_num), HOST_MODE);
  275. c67x00_ll_husb_sie_init(sie);
  276. /* Clear interrupts */
  277. c67x00_ll_usb_clear_status(sie, HOST_STAT_MASK);
  278. /* Check */
  279. if (!(hpi_read_word(sie->dev, USB_CTL_REG(sie->sie_num)) & HOST_MODE))
  280. dev_warn(sie_dev(sie),
  281. "SIE %d not set to host mode\n", sie->sie_num);
  282. }
  283. void c67x00_ll_husb_reset_port(struct c67x00_sie *sie, int port)
  284. {
  285. /* Clear connect change */
  286. c67x00_ll_usb_clear_status(sie, PORT_CONNECT_CHANGE(port));
  287. /* Enable interrupts */
  288. hpi_set_bits(sie->dev, HPI_IRQ_ROUTING_REG,
  289. SOFEOP_TO_CPU_EN(sie->sie_num));
  290. hpi_set_bits(sie->dev, HOST_IRQ_EN_REG(sie->sie_num),
  291. SOF_EOP_IRQ_EN | DONE_IRQ_EN);
  292. /* Enable pull down transistors */
  293. hpi_set_bits(sie->dev, USB_CTL_REG(sie->sie_num), PORT_RES_EN(port));
  294. }
  295. /* -------------------------------------------------------------------------- */
  296. void c67x00_ll_irq(struct c67x00_device *dev, u16 int_status)
  297. {
  298. if ((int_status & MBX_OUT_FLG) == 0)
  299. return;
  300. dev->hpi.lcp.last_msg = hpi_recv_mbox(dev);
  301. complete(&dev->hpi.lcp.msg_received);
  302. }
  303. /* -------------------------------------------------------------------------- */
  304. int c67x00_ll_reset(struct c67x00_device *dev)
  305. {
  306. int rc;
  307. mutex_lock(&dev->hpi.lcp.mutex);
  308. hpi_send_mbox(dev, COMM_RESET);
  309. rc = ll_recv_msg(dev);
  310. mutex_unlock(&dev->hpi.lcp.mutex);
  311. return rc;
  312. }
  313. /* -------------------------------------------------------------------------- */
  314. /*
  315. * c67x00_ll_write_mem_le16 - write into c67x00 memory
  316. * Only data is little endian, addr has cpu endianess.
  317. */
  318. void c67x00_ll_write_mem_le16(struct c67x00_device *dev, u16 addr,
  319. void *data, int len)
  320. {
  321. u8 *buf = data;
  322. /* Sanity check */
  323. if (addr + len > 0xffff) {
  324. dev_err(&dev->pdev->dev,
  325. "Trying to write beyond writable region!\n");
  326. return;
  327. }
  328. if (addr & 0x01) {
  329. /* unaligned access */
  330. u16 tmp;
  331. tmp = hpi_read_word(dev, addr - 1);
  332. tmp = (tmp & 0x00ff) | (*buf++ << 8);
  333. hpi_write_word(dev, addr - 1, tmp);
  334. addr++;
  335. len--;
  336. }
  337. hpi_write_words_le16(dev, addr, (__le16 *)buf, len / 2);
  338. buf += len & ~0x01;
  339. addr += len & ~0x01;
  340. len &= 0x01;
  341. if (len) {
  342. u16 tmp;
  343. tmp = hpi_read_word(dev, addr);
  344. tmp = (tmp & 0xff00) | *buf;
  345. hpi_write_word(dev, addr, tmp);
  346. }
  347. }
  348. /*
  349. * c67x00_ll_read_mem_le16 - read from c67x00 memory
  350. * Only data is little endian, addr has cpu endianess.
  351. */
  352. void c67x00_ll_read_mem_le16(struct c67x00_device *dev, u16 addr,
  353. void *data, int len)
  354. {
  355. u8 *buf = data;
  356. if (addr & 0x01) {
  357. /* unaligned access */
  358. u16 tmp;
  359. tmp = hpi_read_word(dev, addr - 1);
  360. *buf++ = (tmp >> 8) & 0x00ff;
  361. addr++;
  362. len--;
  363. }
  364. hpi_read_words_le16(dev, addr, (__le16 *)buf, len / 2);
  365. buf += len & ~0x01;
  366. addr += len & ~0x01;
  367. len &= 0x01;
  368. if (len) {
  369. u16 tmp;
  370. tmp = hpi_read_word(dev, addr);
  371. *buf = tmp & 0x00ff;
  372. }
  373. }
  374. /* -------------------------------------------------------------------------- */
  375. void c67x00_ll_init(struct c67x00_device *dev)
  376. {
  377. mutex_init(&dev->hpi.lcp.mutex);
  378. init_completion(&dev->hpi.lcp.msg_received);
  379. }
  380. void c67x00_ll_release(struct c67x00_device *dev)
  381. {
  382. }