synclinkmp.c 146 KB

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  1. // SPDX-License-Identifier: GPL-1.0+
  2. /*
  3. * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
  4. *
  5. * Device driver for Microgate SyncLink Multiport
  6. * high speed multiprotocol serial adapter.
  7. *
  8. * written by Paul Fulghum for Microgate Corporation
  9. * paulkf@microgate.com
  10. *
  11. * Microgate and SyncLink are trademarks of Microgate Corporation
  12. *
  13. * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
  14. *
  15. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  16. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  17. * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  18. * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  19. * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  20. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  21. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  23. * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  24. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  25. * OF THE POSSIBILITY OF SUCH DAMAGE.
  26. */
  27. #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
  28. #if defined(__i386__)
  29. # define BREAKPOINT() asm(" int $3");
  30. #else
  31. # define BREAKPOINT() { }
  32. #endif
  33. #define MAX_DEVICES 12
  34. #include <linux/module.h>
  35. #include <linux/errno.h>
  36. #include <linux/signal.h>
  37. #include <linux/sched.h>
  38. #include <linux/timer.h>
  39. #include <linux/interrupt.h>
  40. #include <linux/pci.h>
  41. #include <linux/tty.h>
  42. #include <linux/tty_flip.h>
  43. #include <linux/serial.h>
  44. #include <linux/major.h>
  45. #include <linux/string.h>
  46. #include <linux/fcntl.h>
  47. #include <linux/ptrace.h>
  48. #include <linux/ioport.h>
  49. #include <linux/mm.h>
  50. #include <linux/seq_file.h>
  51. #include <linux/slab.h>
  52. #include <linux/netdevice.h>
  53. #include <linux/vmalloc.h>
  54. #include <linux/init.h>
  55. #include <linux/delay.h>
  56. #include <linux/ioctl.h>
  57. #include <asm/io.h>
  58. #include <asm/irq.h>
  59. #include <asm/dma.h>
  60. #include <linux/bitops.h>
  61. #include <asm/types.h>
  62. #include <linux/termios.h>
  63. #include <linux/workqueue.h>
  64. #include <linux/hdlc.h>
  65. #include <linux/synclink.h>
  66. #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE))
  67. #define SYNCLINK_GENERIC_HDLC 1
  68. #else
  69. #define SYNCLINK_GENERIC_HDLC 0
  70. #endif
  71. #define GET_USER(error,value,addr) error = get_user(value,addr)
  72. #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
  73. #define PUT_USER(error,value,addr) error = put_user(value,addr)
  74. #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
  75. #include <linux/uaccess.h>
  76. static MGSL_PARAMS default_params = {
  77. MGSL_MODE_HDLC, /* unsigned long mode */
  78. 0, /* unsigned char loopback; */
  79. HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
  80. HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
  81. 0, /* unsigned long clock_speed; */
  82. 0xff, /* unsigned char addr_filter; */
  83. HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
  84. HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
  85. HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
  86. 9600, /* unsigned long data_rate; */
  87. 8, /* unsigned char data_bits; */
  88. 1, /* unsigned char stop_bits; */
  89. ASYNC_PARITY_NONE /* unsigned char parity; */
  90. };
  91. /* size in bytes of DMA data buffers */
  92. #define SCABUFSIZE 1024
  93. #define SCA_MEM_SIZE 0x40000
  94. #define SCA_BASE_SIZE 512
  95. #define SCA_REG_SIZE 16
  96. #define SCA_MAX_PORTS 4
  97. #define SCAMAXDESC 128
  98. #define BUFFERLISTSIZE 4096
  99. /* SCA-I style DMA buffer descriptor */
  100. typedef struct _SCADESC
  101. {
  102. u16 next; /* lower l6 bits of next descriptor addr */
  103. u16 buf_ptr; /* lower 16 bits of buffer addr */
  104. u8 buf_base; /* upper 8 bits of buffer addr */
  105. u8 pad1;
  106. u16 length; /* length of buffer */
  107. u8 status; /* status of buffer */
  108. u8 pad2;
  109. } SCADESC, *PSCADESC;
  110. typedef struct _SCADESC_EX
  111. {
  112. /* device driver bookkeeping section */
  113. char *virt_addr; /* virtual address of data buffer */
  114. u16 phys_entry; /* lower 16-bits of physical address of this descriptor */
  115. } SCADESC_EX, *PSCADESC_EX;
  116. /* The queue of BH actions to be performed */
  117. #define BH_RECEIVE 1
  118. #define BH_TRANSMIT 2
  119. #define BH_STATUS 4
  120. #define IO_PIN_SHUTDOWN_LIMIT 100
  121. struct _input_signal_events {
  122. int ri_up;
  123. int ri_down;
  124. int dsr_up;
  125. int dsr_down;
  126. int dcd_up;
  127. int dcd_down;
  128. int cts_up;
  129. int cts_down;
  130. };
  131. /*
  132. * Device instance data structure
  133. */
  134. typedef struct _synclinkmp_info {
  135. void *if_ptr; /* General purpose pointer (used by SPPP) */
  136. int magic;
  137. struct tty_port port;
  138. int line;
  139. unsigned short close_delay;
  140. unsigned short closing_wait; /* time to wait before closing */
  141. struct mgsl_icount icount;
  142. int timeout;
  143. int x_char; /* xon/xoff character */
  144. u16 read_status_mask1; /* break detection (SR1 indications) */
  145. u16 read_status_mask2; /* parity/framing/overun (SR2 indications) */
  146. unsigned char ignore_status_mask1; /* break detection (SR1 indications) */
  147. unsigned char ignore_status_mask2; /* parity/framing/overun (SR2 indications) */
  148. unsigned char *tx_buf;
  149. int tx_put;
  150. int tx_get;
  151. int tx_count;
  152. wait_queue_head_t status_event_wait_q;
  153. wait_queue_head_t event_wait_q;
  154. struct timer_list tx_timer; /* HDLC transmit timeout timer */
  155. struct _synclinkmp_info *next_device; /* device list link */
  156. struct timer_list status_timer; /* input signal status check timer */
  157. spinlock_t lock; /* spinlock for synchronizing with ISR */
  158. struct work_struct task; /* task structure for scheduling bh */
  159. u32 max_frame_size; /* as set by device config */
  160. u32 pending_bh;
  161. bool bh_running; /* Protection from multiple */
  162. int isr_overflow;
  163. bool bh_requested;
  164. int dcd_chkcount; /* check counts to prevent */
  165. int cts_chkcount; /* too many IRQs if a signal */
  166. int dsr_chkcount; /* is floating */
  167. int ri_chkcount;
  168. char *buffer_list; /* virtual address of Rx & Tx buffer lists */
  169. unsigned long buffer_list_phys;
  170. unsigned int rx_buf_count; /* count of total allocated Rx buffers */
  171. SCADESC *rx_buf_list; /* list of receive buffer entries */
  172. SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
  173. unsigned int current_rx_buf;
  174. unsigned int tx_buf_count; /* count of total allocated Tx buffers */
  175. SCADESC *tx_buf_list; /* list of transmit buffer entries */
  176. SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
  177. unsigned int last_tx_buf;
  178. unsigned char *tmp_rx_buf;
  179. unsigned int tmp_rx_buf_count;
  180. bool rx_enabled;
  181. bool rx_overflow;
  182. bool tx_enabled;
  183. bool tx_active;
  184. u32 idle_mode;
  185. unsigned char ie0_value;
  186. unsigned char ie1_value;
  187. unsigned char ie2_value;
  188. unsigned char ctrlreg_value;
  189. unsigned char old_signals;
  190. char device_name[25]; /* device instance name */
  191. int port_count;
  192. int adapter_num;
  193. int port_num;
  194. struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
  195. unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
  196. unsigned int irq_level; /* interrupt level */
  197. unsigned long irq_flags;
  198. bool irq_requested; /* true if IRQ requested */
  199. MGSL_PARAMS params; /* communications parameters */
  200. unsigned char serial_signals; /* current serial signal states */
  201. bool irq_occurred; /* for diagnostics use */
  202. unsigned int init_error; /* Initialization startup error */
  203. u32 last_mem_alloc;
  204. unsigned char* memory_base; /* shared memory address (PCI only) */
  205. u32 phys_memory_base;
  206. int shared_mem_requested;
  207. unsigned char* sca_base; /* HD64570 SCA Memory address */
  208. u32 phys_sca_base;
  209. u32 sca_offset;
  210. bool sca_base_requested;
  211. unsigned char* lcr_base; /* local config registers (PCI only) */
  212. u32 phys_lcr_base;
  213. u32 lcr_offset;
  214. int lcr_mem_requested;
  215. unsigned char* statctrl_base; /* status/control register memory */
  216. u32 phys_statctrl_base;
  217. u32 statctrl_offset;
  218. bool sca_statctrl_requested;
  219. u32 misc_ctrl_value;
  220. char *flag_buf;
  221. bool drop_rts_on_tx_done;
  222. struct _input_signal_events input_signal_events;
  223. /* SPPP/Cisco HDLC device parts */
  224. int netcount;
  225. spinlock_t netlock;
  226. #if SYNCLINK_GENERIC_HDLC
  227. struct net_device *netdev;
  228. #endif
  229. } SLMP_INFO;
  230. #define MGSL_MAGIC 0x5401
  231. /*
  232. * define serial signal status change macros
  233. */
  234. #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) /* indicates change in DCD */
  235. #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) /* indicates change in RI */
  236. #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) /* indicates change in CTS */
  237. #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) /* change in DSR */
  238. /* Common Register macros */
  239. #define LPR 0x00
  240. #define PABR0 0x02
  241. #define PABR1 0x03
  242. #define WCRL 0x04
  243. #define WCRM 0x05
  244. #define WCRH 0x06
  245. #define DPCR 0x08
  246. #define DMER 0x09
  247. #define ISR0 0x10
  248. #define ISR1 0x11
  249. #define ISR2 0x12
  250. #define IER0 0x14
  251. #define IER1 0x15
  252. #define IER2 0x16
  253. #define ITCR 0x18
  254. #define INTVR 0x1a
  255. #define IMVR 0x1c
  256. /* MSCI Register macros */
  257. #define TRB 0x20
  258. #define TRBL 0x20
  259. #define TRBH 0x21
  260. #define SR0 0x22
  261. #define SR1 0x23
  262. #define SR2 0x24
  263. #define SR3 0x25
  264. #define FST 0x26
  265. #define IE0 0x28
  266. #define IE1 0x29
  267. #define IE2 0x2a
  268. #define FIE 0x2b
  269. #define CMD 0x2c
  270. #define MD0 0x2e
  271. #define MD1 0x2f
  272. #define MD2 0x30
  273. #define CTL 0x31
  274. #define SA0 0x32
  275. #define SA1 0x33
  276. #define IDL 0x34
  277. #define TMC 0x35
  278. #define RXS 0x36
  279. #define TXS 0x37
  280. #define TRC0 0x38
  281. #define TRC1 0x39
  282. #define RRC 0x3a
  283. #define CST0 0x3c
  284. #define CST1 0x3d
  285. /* Timer Register Macros */
  286. #define TCNT 0x60
  287. #define TCNTL 0x60
  288. #define TCNTH 0x61
  289. #define TCONR 0x62
  290. #define TCONRL 0x62
  291. #define TCONRH 0x63
  292. #define TMCS 0x64
  293. #define TEPR 0x65
  294. /* DMA Controller Register macros */
  295. #define DARL 0x80
  296. #define DARH 0x81
  297. #define DARB 0x82
  298. #define BAR 0x80
  299. #define BARL 0x80
  300. #define BARH 0x81
  301. #define BARB 0x82
  302. #define SAR 0x84
  303. #define SARL 0x84
  304. #define SARH 0x85
  305. #define SARB 0x86
  306. #define CPB 0x86
  307. #define CDA 0x88
  308. #define CDAL 0x88
  309. #define CDAH 0x89
  310. #define EDA 0x8a
  311. #define EDAL 0x8a
  312. #define EDAH 0x8b
  313. #define BFL 0x8c
  314. #define BFLL 0x8c
  315. #define BFLH 0x8d
  316. #define BCR 0x8e
  317. #define BCRL 0x8e
  318. #define BCRH 0x8f
  319. #define DSR 0x90
  320. #define DMR 0x91
  321. #define FCT 0x93
  322. #define DIR 0x94
  323. #define DCMD 0x95
  324. /* combine with timer or DMA register address */
  325. #define TIMER0 0x00
  326. #define TIMER1 0x08
  327. #define TIMER2 0x10
  328. #define TIMER3 0x18
  329. #define RXDMA 0x00
  330. #define TXDMA 0x20
  331. /* SCA Command Codes */
  332. #define NOOP 0x00
  333. #define TXRESET 0x01
  334. #define TXENABLE 0x02
  335. #define TXDISABLE 0x03
  336. #define TXCRCINIT 0x04
  337. #define TXCRCEXCL 0x05
  338. #define TXEOM 0x06
  339. #define TXABORT 0x07
  340. #define MPON 0x08
  341. #define TXBUFCLR 0x09
  342. #define RXRESET 0x11
  343. #define RXENABLE 0x12
  344. #define RXDISABLE 0x13
  345. #define RXCRCINIT 0x14
  346. #define RXREJECT 0x15
  347. #define SEARCHMP 0x16
  348. #define RXCRCEXCL 0x17
  349. #define RXCRCCALC 0x18
  350. #define CHRESET 0x21
  351. #define HUNT 0x31
  352. /* DMA command codes */
  353. #define SWABORT 0x01
  354. #define FEICLEAR 0x02
  355. /* IE0 */
  356. #define TXINTE BIT7
  357. #define RXINTE BIT6
  358. #define TXRDYE BIT1
  359. #define RXRDYE BIT0
  360. /* IE1 & SR1 */
  361. #define UDRN BIT7
  362. #define IDLE BIT6
  363. #define SYNCD BIT4
  364. #define FLGD BIT4
  365. #define CCTS BIT3
  366. #define CDCD BIT2
  367. #define BRKD BIT1
  368. #define ABTD BIT1
  369. #define GAPD BIT1
  370. #define BRKE BIT0
  371. #define IDLD BIT0
  372. /* IE2 & SR2 */
  373. #define EOM BIT7
  374. #define PMP BIT6
  375. #define SHRT BIT6
  376. #define PE BIT5
  377. #define ABT BIT5
  378. #define FRME BIT4
  379. #define RBIT BIT4
  380. #define OVRN BIT3
  381. #define CRCE BIT2
  382. /*
  383. * Global linked list of SyncLink devices
  384. */
  385. static SLMP_INFO *synclinkmp_device_list = NULL;
  386. static int synclinkmp_adapter_count = -1;
  387. static int synclinkmp_device_count = 0;
  388. /*
  389. * Set this param to non-zero to load eax with the
  390. * .text section address and breakpoint on module load.
  391. * This is useful for use with gdb and add-symbol-file command.
  392. */
  393. static bool break_on_load = 0;
  394. /*
  395. * Driver major number, defaults to zero to get auto
  396. * assigned major number. May be forced as module parameter.
  397. */
  398. static int ttymajor = 0;
  399. /*
  400. * Array of user specified options for ISA adapters.
  401. */
  402. static int debug_level = 0;
  403. static int maxframe[MAX_DEVICES] = {0,};
  404. module_param(break_on_load, bool, 0);
  405. module_param(ttymajor, int, 0);
  406. module_param(debug_level, int, 0);
  407. module_param_array(maxframe, int, NULL, 0);
  408. static char *driver_name = "SyncLink MultiPort driver";
  409. static char *driver_version = "$Revision: 4.38 $";
  410. static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
  411. static void synclinkmp_remove_one(struct pci_dev *dev);
  412. static const struct pci_device_id synclinkmp_pci_tbl[] = {
  413. { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
  414. { 0, }, /* terminate list */
  415. };
  416. MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
  417. MODULE_LICENSE("GPL");
  418. static struct pci_driver synclinkmp_pci_driver = {
  419. .name = "synclinkmp",
  420. .id_table = synclinkmp_pci_tbl,
  421. .probe = synclinkmp_init_one,
  422. .remove = synclinkmp_remove_one,
  423. };
  424. static struct tty_driver *serial_driver;
  425. /* number of characters left in xmit buffer before we ask for more */
  426. #define WAKEUP_CHARS 256
  427. /* tty callbacks */
  428. static int open(struct tty_struct *tty, struct file * filp);
  429. static void close(struct tty_struct *tty, struct file * filp);
  430. static void hangup(struct tty_struct *tty);
  431. static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
  432. static int write(struct tty_struct *tty, const unsigned char *buf, int count);
  433. static int put_char(struct tty_struct *tty, unsigned char ch);
  434. static void send_xchar(struct tty_struct *tty, char ch);
  435. static void wait_until_sent(struct tty_struct *tty, int timeout);
  436. static int write_room(struct tty_struct *tty);
  437. static void flush_chars(struct tty_struct *tty);
  438. static void flush_buffer(struct tty_struct *tty);
  439. static void tx_hold(struct tty_struct *tty);
  440. static void tx_release(struct tty_struct *tty);
  441. static int ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg);
  442. static int chars_in_buffer(struct tty_struct *tty);
  443. static void throttle(struct tty_struct * tty);
  444. static void unthrottle(struct tty_struct * tty);
  445. static int set_break(struct tty_struct *tty, int break_state);
  446. #if SYNCLINK_GENERIC_HDLC
  447. #define dev_to_port(D) (dev_to_hdlc(D)->priv)
  448. static void hdlcdev_tx_done(SLMP_INFO *info);
  449. static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
  450. static int hdlcdev_init(SLMP_INFO *info);
  451. static void hdlcdev_exit(SLMP_INFO *info);
  452. #endif
  453. /* ioctl handlers */
  454. static int get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
  455. static int get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
  456. static int set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
  457. static int get_txidle(SLMP_INFO *info, int __user *idle_mode);
  458. static int set_txidle(SLMP_INFO *info, int idle_mode);
  459. static int tx_enable(SLMP_INFO *info, int enable);
  460. static int tx_abort(SLMP_INFO *info);
  461. static int rx_enable(SLMP_INFO *info, int enable);
  462. static int modem_input_wait(SLMP_INFO *info,int arg);
  463. static int wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
  464. static int tiocmget(struct tty_struct *tty);
  465. static int tiocmset(struct tty_struct *tty,
  466. unsigned int set, unsigned int clear);
  467. static int set_break(struct tty_struct *tty, int break_state);
  468. static int add_device(SLMP_INFO *info);
  469. static int device_init(int adapter_num, struct pci_dev *pdev);
  470. static int claim_resources(SLMP_INFO *info);
  471. static void release_resources(SLMP_INFO *info);
  472. static int startup(SLMP_INFO *info);
  473. static int block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
  474. static int carrier_raised(struct tty_port *port);
  475. static void shutdown(SLMP_INFO *info);
  476. static void program_hw(SLMP_INFO *info);
  477. static void change_params(SLMP_INFO *info);
  478. static bool init_adapter(SLMP_INFO *info);
  479. static bool register_test(SLMP_INFO *info);
  480. static bool irq_test(SLMP_INFO *info);
  481. static bool loopback_test(SLMP_INFO *info);
  482. static int adapter_test(SLMP_INFO *info);
  483. static bool memory_test(SLMP_INFO *info);
  484. static void reset_adapter(SLMP_INFO *info);
  485. static void reset_port(SLMP_INFO *info);
  486. static void async_mode(SLMP_INFO *info);
  487. static void hdlc_mode(SLMP_INFO *info);
  488. static void rx_stop(SLMP_INFO *info);
  489. static void rx_start(SLMP_INFO *info);
  490. static void rx_reset_buffers(SLMP_INFO *info);
  491. static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
  492. static bool rx_get_frame(SLMP_INFO *info);
  493. static void tx_start(SLMP_INFO *info);
  494. static void tx_stop(SLMP_INFO *info);
  495. static void tx_load_fifo(SLMP_INFO *info);
  496. static void tx_set_idle(SLMP_INFO *info);
  497. static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
  498. static void get_signals(SLMP_INFO *info);
  499. static void set_signals(SLMP_INFO *info);
  500. static void enable_loopback(SLMP_INFO *info, int enable);
  501. static void set_rate(SLMP_INFO *info, u32 data_rate);
  502. static int bh_action(SLMP_INFO *info);
  503. static void bh_handler(struct work_struct *work);
  504. static void bh_receive(SLMP_INFO *info);
  505. static void bh_transmit(SLMP_INFO *info);
  506. static void bh_status(SLMP_INFO *info);
  507. static void isr_timer(SLMP_INFO *info);
  508. static void isr_rxint(SLMP_INFO *info);
  509. static void isr_rxrdy(SLMP_INFO *info);
  510. static void isr_txint(SLMP_INFO *info);
  511. static void isr_txrdy(SLMP_INFO *info);
  512. static void isr_rxdmaok(SLMP_INFO *info);
  513. static void isr_rxdmaerror(SLMP_INFO *info);
  514. static void isr_txdmaok(SLMP_INFO *info);
  515. static void isr_txdmaerror(SLMP_INFO *info);
  516. static void isr_io_pin(SLMP_INFO *info, u16 status);
  517. static int alloc_dma_bufs(SLMP_INFO *info);
  518. static void free_dma_bufs(SLMP_INFO *info);
  519. static int alloc_buf_list(SLMP_INFO *info);
  520. static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
  521. static int alloc_tmp_rx_buf(SLMP_INFO *info);
  522. static void free_tmp_rx_buf(SLMP_INFO *info);
  523. static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
  524. static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
  525. static void tx_timeout(struct timer_list *t);
  526. static void status_timeout(struct timer_list *t);
  527. static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
  528. static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
  529. static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
  530. static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
  531. static unsigned char read_status_reg(SLMP_INFO * info);
  532. static void write_control_reg(SLMP_INFO * info);
  533. static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
  534. static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
  535. static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
  536. static u32 misc_ctrl_value = 0x007e4040;
  537. static u32 lcr1_brdr_value = 0x00800028;
  538. static u32 read_ahead_count = 8;
  539. /* DPCR, DMA Priority Control
  540. *
  541. * 07..05 Not used, must be 0
  542. * 04 BRC, bus release condition: 0=all transfers complete
  543. * 1=release after 1 xfer on all channels
  544. * 03 CCC, channel change condition: 0=every cycle
  545. * 1=after each channel completes all xfers
  546. * 02..00 PR<2..0>, priority 100=round robin
  547. *
  548. * 00000100 = 0x00
  549. */
  550. static unsigned char dma_priority = 0x04;
  551. // Number of bytes that can be written to shared RAM
  552. // in a single write operation
  553. static u32 sca_pci_load_interval = 64;
  554. /*
  555. * 1st function defined in .text section. Calling this function in
  556. * init_module() followed by a breakpoint allows a remote debugger
  557. * (gdb) to get the .text address for the add-symbol-file command.
  558. * This allows remote debugging of dynamically loadable modules.
  559. */
  560. static void* synclinkmp_get_text_ptr(void);
  561. static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
  562. static inline int sanity_check(SLMP_INFO *info,
  563. char *name, const char *routine)
  564. {
  565. #ifdef SANITY_CHECK
  566. static const char *badmagic =
  567. "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
  568. static const char *badinfo =
  569. "Warning: null synclinkmp_struct for (%s) in %s\n";
  570. if (!info) {
  571. printk(badinfo, name, routine);
  572. return 1;
  573. }
  574. if (info->magic != MGSL_MAGIC) {
  575. printk(badmagic, name, routine);
  576. return 1;
  577. }
  578. #else
  579. if (!info)
  580. return 1;
  581. #endif
  582. return 0;
  583. }
  584. /*
  585. * line discipline callback wrappers
  586. *
  587. * The wrappers maintain line discipline references
  588. * while calling into the line discipline.
  589. *
  590. * ldisc_receive_buf - pass receive data to line discipline
  591. */
  592. static void ldisc_receive_buf(struct tty_struct *tty,
  593. const __u8 *data, char *flags, int count)
  594. {
  595. struct tty_ldisc *ld;
  596. if (!tty)
  597. return;
  598. ld = tty_ldisc_ref(tty);
  599. if (ld) {
  600. if (ld->ops->receive_buf)
  601. ld->ops->receive_buf(tty, data, flags, count);
  602. tty_ldisc_deref(ld);
  603. }
  604. }
  605. /* tty callbacks */
  606. static int install(struct tty_driver *driver, struct tty_struct *tty)
  607. {
  608. SLMP_INFO *info;
  609. int line = tty->index;
  610. if (line >= synclinkmp_device_count) {
  611. printk("%s(%d): open with invalid line #%d.\n",
  612. __FILE__,__LINE__,line);
  613. return -ENODEV;
  614. }
  615. info = synclinkmp_device_list;
  616. while (info && info->line != line)
  617. info = info->next_device;
  618. if (sanity_check(info, tty->name, "open"))
  619. return -ENODEV;
  620. if (info->init_error) {
  621. printk("%s(%d):%s device is not allocated, init error=%d\n",
  622. __FILE__, __LINE__, info->device_name,
  623. info->init_error);
  624. return -ENODEV;
  625. }
  626. tty->driver_data = info;
  627. return tty_port_install(&info->port, driver, tty);
  628. }
  629. /* Called when a port is opened. Init and enable port.
  630. */
  631. static int open(struct tty_struct *tty, struct file *filp)
  632. {
  633. SLMP_INFO *info = tty->driver_data;
  634. unsigned long flags;
  635. int retval;
  636. info->port.tty = tty;
  637. if (debug_level >= DEBUG_LEVEL_INFO)
  638. printk("%s(%d):%s open(), old ref count = %d\n",
  639. __FILE__,__LINE__,tty->driver->name, info->port.count);
  640. info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
  641. spin_lock_irqsave(&info->netlock, flags);
  642. if (info->netcount) {
  643. retval = -EBUSY;
  644. spin_unlock_irqrestore(&info->netlock, flags);
  645. goto cleanup;
  646. }
  647. info->port.count++;
  648. spin_unlock_irqrestore(&info->netlock, flags);
  649. if (info->port.count == 1) {
  650. /* 1st open on this device, init hardware */
  651. retval = startup(info);
  652. if (retval < 0)
  653. goto cleanup;
  654. }
  655. retval = block_til_ready(tty, filp, info);
  656. if (retval) {
  657. if (debug_level >= DEBUG_LEVEL_INFO)
  658. printk("%s(%d):%s block_til_ready() returned %d\n",
  659. __FILE__,__LINE__, info->device_name, retval);
  660. goto cleanup;
  661. }
  662. if (debug_level >= DEBUG_LEVEL_INFO)
  663. printk("%s(%d):%s open() success\n",
  664. __FILE__,__LINE__, info->device_name);
  665. retval = 0;
  666. cleanup:
  667. if (retval) {
  668. if (tty->count == 1)
  669. info->port.tty = NULL; /* tty layer will release tty struct */
  670. if(info->port.count)
  671. info->port.count--;
  672. }
  673. return retval;
  674. }
  675. /* Called when port is closed. Wait for remaining data to be
  676. * sent. Disable port and free resources.
  677. */
  678. static void close(struct tty_struct *tty, struct file *filp)
  679. {
  680. SLMP_INFO * info = tty->driver_data;
  681. if (sanity_check(info, tty->name, "close"))
  682. return;
  683. if (debug_level >= DEBUG_LEVEL_INFO)
  684. printk("%s(%d):%s close() entry, count=%d\n",
  685. __FILE__,__LINE__, info->device_name, info->port.count);
  686. if (tty_port_close_start(&info->port, tty, filp) == 0)
  687. goto cleanup;
  688. mutex_lock(&info->port.mutex);
  689. if (tty_port_initialized(&info->port))
  690. wait_until_sent(tty, info->timeout);
  691. flush_buffer(tty);
  692. tty_ldisc_flush(tty);
  693. shutdown(info);
  694. mutex_unlock(&info->port.mutex);
  695. tty_port_close_end(&info->port, tty);
  696. info->port.tty = NULL;
  697. cleanup:
  698. if (debug_level >= DEBUG_LEVEL_INFO)
  699. printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
  700. tty->driver->name, info->port.count);
  701. }
  702. /* Called by tty_hangup() when a hangup is signaled.
  703. * This is the same as closing all open descriptors for the port.
  704. */
  705. static void hangup(struct tty_struct *tty)
  706. {
  707. SLMP_INFO *info = tty->driver_data;
  708. unsigned long flags;
  709. if (debug_level >= DEBUG_LEVEL_INFO)
  710. printk("%s(%d):%s hangup()\n",
  711. __FILE__,__LINE__, info->device_name );
  712. if (sanity_check(info, tty->name, "hangup"))
  713. return;
  714. mutex_lock(&info->port.mutex);
  715. flush_buffer(tty);
  716. shutdown(info);
  717. spin_lock_irqsave(&info->port.lock, flags);
  718. info->port.count = 0;
  719. info->port.tty = NULL;
  720. spin_unlock_irqrestore(&info->port.lock, flags);
  721. tty_port_set_active(&info->port, 1);
  722. mutex_unlock(&info->port.mutex);
  723. wake_up_interruptible(&info->port.open_wait);
  724. }
  725. /* Set new termios settings
  726. */
  727. static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
  728. {
  729. SLMP_INFO *info = tty->driver_data;
  730. unsigned long flags;
  731. if (debug_level >= DEBUG_LEVEL_INFO)
  732. printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
  733. tty->driver->name );
  734. change_params(info);
  735. /* Handle transition to B0 status */
  736. if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
  737. info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
  738. spin_lock_irqsave(&info->lock,flags);
  739. set_signals(info);
  740. spin_unlock_irqrestore(&info->lock,flags);
  741. }
  742. /* Handle transition away from B0 status */
  743. if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
  744. info->serial_signals |= SerialSignal_DTR;
  745. if (!C_CRTSCTS(tty) || !tty_throttled(tty))
  746. info->serial_signals |= SerialSignal_RTS;
  747. spin_lock_irqsave(&info->lock,flags);
  748. set_signals(info);
  749. spin_unlock_irqrestore(&info->lock,flags);
  750. }
  751. /* Handle turning off CRTSCTS */
  752. if (old_termios->c_cflag & CRTSCTS && !C_CRTSCTS(tty)) {
  753. tty->hw_stopped = 0;
  754. tx_release(tty);
  755. }
  756. }
  757. /* Send a block of data
  758. *
  759. * Arguments:
  760. *
  761. * tty pointer to tty information structure
  762. * buf pointer to buffer containing send data
  763. * count size of send data in bytes
  764. *
  765. * Return Value: number of characters written
  766. */
  767. static int write(struct tty_struct *tty,
  768. const unsigned char *buf, int count)
  769. {
  770. int c, ret = 0;
  771. SLMP_INFO *info = tty->driver_data;
  772. unsigned long flags;
  773. if (debug_level >= DEBUG_LEVEL_INFO)
  774. printk("%s(%d):%s write() count=%d\n",
  775. __FILE__,__LINE__,info->device_name,count);
  776. if (sanity_check(info, tty->name, "write"))
  777. goto cleanup;
  778. if (!info->tx_buf)
  779. goto cleanup;
  780. if (info->params.mode == MGSL_MODE_HDLC) {
  781. if (count > info->max_frame_size) {
  782. ret = -EIO;
  783. goto cleanup;
  784. }
  785. if (info->tx_active)
  786. goto cleanup;
  787. if (info->tx_count) {
  788. /* send accumulated data from send_char() calls */
  789. /* as frame and wait before accepting more data. */
  790. tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
  791. goto start;
  792. }
  793. ret = info->tx_count = count;
  794. tx_load_dma_buffer(info, buf, count);
  795. goto start;
  796. }
  797. for (;;) {
  798. c = min_t(int, count,
  799. min(info->max_frame_size - info->tx_count - 1,
  800. info->max_frame_size - info->tx_put));
  801. if (c <= 0)
  802. break;
  803. memcpy(info->tx_buf + info->tx_put, buf, c);
  804. spin_lock_irqsave(&info->lock,flags);
  805. info->tx_put += c;
  806. if (info->tx_put >= info->max_frame_size)
  807. info->tx_put -= info->max_frame_size;
  808. info->tx_count += c;
  809. spin_unlock_irqrestore(&info->lock,flags);
  810. buf += c;
  811. count -= c;
  812. ret += c;
  813. }
  814. if (info->params.mode == MGSL_MODE_HDLC) {
  815. if (count) {
  816. ret = info->tx_count = 0;
  817. goto cleanup;
  818. }
  819. tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
  820. }
  821. start:
  822. if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
  823. spin_lock_irqsave(&info->lock,flags);
  824. if (!info->tx_active)
  825. tx_start(info);
  826. spin_unlock_irqrestore(&info->lock,flags);
  827. }
  828. cleanup:
  829. if (debug_level >= DEBUG_LEVEL_INFO)
  830. printk( "%s(%d):%s write() returning=%d\n",
  831. __FILE__,__LINE__,info->device_name,ret);
  832. return ret;
  833. }
  834. /* Add a character to the transmit buffer.
  835. */
  836. static int put_char(struct tty_struct *tty, unsigned char ch)
  837. {
  838. SLMP_INFO *info = tty->driver_data;
  839. unsigned long flags;
  840. int ret = 0;
  841. if ( debug_level >= DEBUG_LEVEL_INFO ) {
  842. printk( "%s(%d):%s put_char(%d)\n",
  843. __FILE__,__LINE__,info->device_name,ch);
  844. }
  845. if (sanity_check(info, tty->name, "put_char"))
  846. return 0;
  847. if (!info->tx_buf)
  848. return 0;
  849. spin_lock_irqsave(&info->lock,flags);
  850. if ( (info->params.mode != MGSL_MODE_HDLC) ||
  851. !info->tx_active ) {
  852. if (info->tx_count < info->max_frame_size - 1) {
  853. info->tx_buf[info->tx_put++] = ch;
  854. if (info->tx_put >= info->max_frame_size)
  855. info->tx_put -= info->max_frame_size;
  856. info->tx_count++;
  857. ret = 1;
  858. }
  859. }
  860. spin_unlock_irqrestore(&info->lock,flags);
  861. return ret;
  862. }
  863. /* Send a high-priority XON/XOFF character
  864. */
  865. static void send_xchar(struct tty_struct *tty, char ch)
  866. {
  867. SLMP_INFO *info = tty->driver_data;
  868. unsigned long flags;
  869. if (debug_level >= DEBUG_LEVEL_INFO)
  870. printk("%s(%d):%s send_xchar(%d)\n",
  871. __FILE__,__LINE__, info->device_name, ch );
  872. if (sanity_check(info, tty->name, "send_xchar"))
  873. return;
  874. info->x_char = ch;
  875. if (ch) {
  876. /* Make sure transmit interrupts are on */
  877. spin_lock_irqsave(&info->lock,flags);
  878. if (!info->tx_enabled)
  879. tx_start(info);
  880. spin_unlock_irqrestore(&info->lock,flags);
  881. }
  882. }
  883. /* Wait until the transmitter is empty.
  884. */
  885. static void wait_until_sent(struct tty_struct *tty, int timeout)
  886. {
  887. SLMP_INFO * info = tty->driver_data;
  888. unsigned long orig_jiffies, char_time;
  889. if (!info )
  890. return;
  891. if (debug_level >= DEBUG_LEVEL_INFO)
  892. printk("%s(%d):%s wait_until_sent() entry\n",
  893. __FILE__,__LINE__, info->device_name );
  894. if (sanity_check(info, tty->name, "wait_until_sent"))
  895. return;
  896. if (!tty_port_initialized(&info->port))
  897. goto exit;
  898. orig_jiffies = jiffies;
  899. /* Set check interval to 1/5 of estimated time to
  900. * send a character, and make it at least 1. The check
  901. * interval should also be less than the timeout.
  902. * Note: use tight timings here to satisfy the NIST-PCTS.
  903. */
  904. if ( info->params.data_rate ) {
  905. char_time = info->timeout/(32 * 5);
  906. if (!char_time)
  907. char_time++;
  908. } else
  909. char_time = 1;
  910. if (timeout)
  911. char_time = min_t(unsigned long, char_time, timeout);
  912. if ( info->params.mode == MGSL_MODE_HDLC ) {
  913. while (info->tx_active) {
  914. msleep_interruptible(jiffies_to_msecs(char_time));
  915. if (signal_pending(current))
  916. break;
  917. if (timeout && time_after(jiffies, orig_jiffies + timeout))
  918. break;
  919. }
  920. } else {
  921. /*
  922. * TODO: determine if there is something similar to USC16C32
  923. * TXSTATUS_ALL_SENT status
  924. */
  925. while ( info->tx_active && info->tx_enabled) {
  926. msleep_interruptible(jiffies_to_msecs(char_time));
  927. if (signal_pending(current))
  928. break;
  929. if (timeout && time_after(jiffies, orig_jiffies + timeout))
  930. break;
  931. }
  932. }
  933. exit:
  934. if (debug_level >= DEBUG_LEVEL_INFO)
  935. printk("%s(%d):%s wait_until_sent() exit\n",
  936. __FILE__,__LINE__, info->device_name );
  937. }
  938. /* Return the count of free bytes in transmit buffer
  939. */
  940. static int write_room(struct tty_struct *tty)
  941. {
  942. SLMP_INFO *info = tty->driver_data;
  943. int ret;
  944. if (sanity_check(info, tty->name, "write_room"))
  945. return 0;
  946. if (info->params.mode == MGSL_MODE_HDLC) {
  947. ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
  948. } else {
  949. ret = info->max_frame_size - info->tx_count - 1;
  950. if (ret < 0)
  951. ret = 0;
  952. }
  953. if (debug_level >= DEBUG_LEVEL_INFO)
  954. printk("%s(%d):%s write_room()=%d\n",
  955. __FILE__, __LINE__, info->device_name, ret);
  956. return ret;
  957. }
  958. /* enable transmitter and send remaining buffered characters
  959. */
  960. static void flush_chars(struct tty_struct *tty)
  961. {
  962. SLMP_INFO *info = tty->driver_data;
  963. unsigned long flags;
  964. if ( debug_level >= DEBUG_LEVEL_INFO )
  965. printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
  966. __FILE__,__LINE__,info->device_name,info->tx_count);
  967. if (sanity_check(info, tty->name, "flush_chars"))
  968. return;
  969. if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
  970. !info->tx_buf)
  971. return;
  972. if ( debug_level >= DEBUG_LEVEL_INFO )
  973. printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
  974. __FILE__,__LINE__,info->device_name );
  975. spin_lock_irqsave(&info->lock,flags);
  976. if (!info->tx_active) {
  977. if ( (info->params.mode == MGSL_MODE_HDLC) &&
  978. info->tx_count ) {
  979. /* operating in synchronous (frame oriented) mode */
  980. /* copy data from circular tx_buf to */
  981. /* transmit DMA buffer. */
  982. tx_load_dma_buffer(info,
  983. info->tx_buf,info->tx_count);
  984. }
  985. tx_start(info);
  986. }
  987. spin_unlock_irqrestore(&info->lock,flags);
  988. }
  989. /* Discard all data in the send buffer
  990. */
  991. static void flush_buffer(struct tty_struct *tty)
  992. {
  993. SLMP_INFO *info = tty->driver_data;
  994. unsigned long flags;
  995. if (debug_level >= DEBUG_LEVEL_INFO)
  996. printk("%s(%d):%s flush_buffer() entry\n",
  997. __FILE__,__LINE__, info->device_name );
  998. if (sanity_check(info, tty->name, "flush_buffer"))
  999. return;
  1000. spin_lock_irqsave(&info->lock,flags);
  1001. info->tx_count = info->tx_put = info->tx_get = 0;
  1002. del_timer(&info->tx_timer);
  1003. spin_unlock_irqrestore(&info->lock,flags);
  1004. tty_wakeup(tty);
  1005. }
  1006. /* throttle (stop) transmitter
  1007. */
  1008. static void tx_hold(struct tty_struct *tty)
  1009. {
  1010. SLMP_INFO *info = tty->driver_data;
  1011. unsigned long flags;
  1012. if (sanity_check(info, tty->name, "tx_hold"))
  1013. return;
  1014. if ( debug_level >= DEBUG_LEVEL_INFO )
  1015. printk("%s(%d):%s tx_hold()\n",
  1016. __FILE__,__LINE__,info->device_name);
  1017. spin_lock_irqsave(&info->lock,flags);
  1018. if (info->tx_enabled)
  1019. tx_stop(info);
  1020. spin_unlock_irqrestore(&info->lock,flags);
  1021. }
  1022. /* release (start) transmitter
  1023. */
  1024. static void tx_release(struct tty_struct *tty)
  1025. {
  1026. SLMP_INFO *info = tty->driver_data;
  1027. unsigned long flags;
  1028. if (sanity_check(info, tty->name, "tx_release"))
  1029. return;
  1030. if ( debug_level >= DEBUG_LEVEL_INFO )
  1031. printk("%s(%d):%s tx_release()\n",
  1032. __FILE__,__LINE__,info->device_name);
  1033. spin_lock_irqsave(&info->lock,flags);
  1034. if (!info->tx_enabled)
  1035. tx_start(info);
  1036. spin_unlock_irqrestore(&info->lock,flags);
  1037. }
  1038. /* Service an IOCTL request
  1039. *
  1040. * Arguments:
  1041. *
  1042. * tty pointer to tty instance data
  1043. * cmd IOCTL command code
  1044. * arg command argument/context
  1045. *
  1046. * Return Value: 0 if success, otherwise error code
  1047. */
  1048. static int ioctl(struct tty_struct *tty,
  1049. unsigned int cmd, unsigned long arg)
  1050. {
  1051. SLMP_INFO *info = tty->driver_data;
  1052. void __user *argp = (void __user *)arg;
  1053. if (debug_level >= DEBUG_LEVEL_INFO)
  1054. printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
  1055. info->device_name, cmd );
  1056. if (sanity_check(info, tty->name, "ioctl"))
  1057. return -ENODEV;
  1058. if (cmd != TIOCMIWAIT) {
  1059. if (tty_io_error(tty))
  1060. return -EIO;
  1061. }
  1062. switch (cmd) {
  1063. case MGSL_IOCGPARAMS:
  1064. return get_params(info, argp);
  1065. case MGSL_IOCSPARAMS:
  1066. return set_params(info, argp);
  1067. case MGSL_IOCGTXIDLE:
  1068. return get_txidle(info, argp);
  1069. case MGSL_IOCSTXIDLE:
  1070. return set_txidle(info, (int)arg);
  1071. case MGSL_IOCTXENABLE:
  1072. return tx_enable(info, (int)arg);
  1073. case MGSL_IOCRXENABLE:
  1074. return rx_enable(info, (int)arg);
  1075. case MGSL_IOCTXABORT:
  1076. return tx_abort(info);
  1077. case MGSL_IOCGSTATS:
  1078. return get_stats(info, argp);
  1079. case MGSL_IOCWAITEVENT:
  1080. return wait_mgsl_event(info, argp);
  1081. case MGSL_IOCLOOPTXDONE:
  1082. return 0; // TODO: Not supported, need to document
  1083. /* Wait for modem input (DCD,RI,DSR,CTS) change
  1084. * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
  1085. */
  1086. case TIOCMIWAIT:
  1087. return modem_input_wait(info,(int)arg);
  1088. /*
  1089. * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
  1090. * Return: write counters to the user passed counter struct
  1091. * NB: both 1->0 and 0->1 transitions are counted except for
  1092. * RI where only 0->1 is counted.
  1093. */
  1094. default:
  1095. return -ENOIOCTLCMD;
  1096. }
  1097. return 0;
  1098. }
  1099. static int get_icount(struct tty_struct *tty,
  1100. struct serial_icounter_struct *icount)
  1101. {
  1102. SLMP_INFO *info = tty->driver_data;
  1103. struct mgsl_icount cnow; /* kernel counter temps */
  1104. unsigned long flags;
  1105. spin_lock_irqsave(&info->lock,flags);
  1106. cnow = info->icount;
  1107. spin_unlock_irqrestore(&info->lock,flags);
  1108. icount->cts = cnow.cts;
  1109. icount->dsr = cnow.dsr;
  1110. icount->rng = cnow.rng;
  1111. icount->dcd = cnow.dcd;
  1112. icount->rx = cnow.rx;
  1113. icount->tx = cnow.tx;
  1114. icount->frame = cnow.frame;
  1115. icount->overrun = cnow.overrun;
  1116. icount->parity = cnow.parity;
  1117. icount->brk = cnow.brk;
  1118. icount->buf_overrun = cnow.buf_overrun;
  1119. return 0;
  1120. }
  1121. /*
  1122. * /proc fs routines....
  1123. */
  1124. static inline void line_info(struct seq_file *m, SLMP_INFO *info)
  1125. {
  1126. char stat_buf[30];
  1127. unsigned long flags;
  1128. seq_printf(m, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
  1129. "\tIRQ=%d MaxFrameSize=%u\n",
  1130. info->device_name,
  1131. info->phys_sca_base,
  1132. info->phys_memory_base,
  1133. info->phys_statctrl_base,
  1134. info->phys_lcr_base,
  1135. info->irq_level,
  1136. info->max_frame_size );
  1137. /* output current serial signal states */
  1138. spin_lock_irqsave(&info->lock,flags);
  1139. get_signals(info);
  1140. spin_unlock_irqrestore(&info->lock,flags);
  1141. stat_buf[0] = 0;
  1142. stat_buf[1] = 0;
  1143. if (info->serial_signals & SerialSignal_RTS)
  1144. strcat(stat_buf, "|RTS");
  1145. if (info->serial_signals & SerialSignal_CTS)
  1146. strcat(stat_buf, "|CTS");
  1147. if (info->serial_signals & SerialSignal_DTR)
  1148. strcat(stat_buf, "|DTR");
  1149. if (info->serial_signals & SerialSignal_DSR)
  1150. strcat(stat_buf, "|DSR");
  1151. if (info->serial_signals & SerialSignal_DCD)
  1152. strcat(stat_buf, "|CD");
  1153. if (info->serial_signals & SerialSignal_RI)
  1154. strcat(stat_buf, "|RI");
  1155. if (info->params.mode == MGSL_MODE_HDLC) {
  1156. seq_printf(m, "\tHDLC txok:%d rxok:%d",
  1157. info->icount.txok, info->icount.rxok);
  1158. if (info->icount.txunder)
  1159. seq_printf(m, " txunder:%d", info->icount.txunder);
  1160. if (info->icount.txabort)
  1161. seq_printf(m, " txabort:%d", info->icount.txabort);
  1162. if (info->icount.rxshort)
  1163. seq_printf(m, " rxshort:%d", info->icount.rxshort);
  1164. if (info->icount.rxlong)
  1165. seq_printf(m, " rxlong:%d", info->icount.rxlong);
  1166. if (info->icount.rxover)
  1167. seq_printf(m, " rxover:%d", info->icount.rxover);
  1168. if (info->icount.rxcrc)
  1169. seq_printf(m, " rxlong:%d", info->icount.rxcrc);
  1170. } else {
  1171. seq_printf(m, "\tASYNC tx:%d rx:%d",
  1172. info->icount.tx, info->icount.rx);
  1173. if (info->icount.frame)
  1174. seq_printf(m, " fe:%d", info->icount.frame);
  1175. if (info->icount.parity)
  1176. seq_printf(m, " pe:%d", info->icount.parity);
  1177. if (info->icount.brk)
  1178. seq_printf(m, " brk:%d", info->icount.brk);
  1179. if (info->icount.overrun)
  1180. seq_printf(m, " oe:%d", info->icount.overrun);
  1181. }
  1182. /* Append serial signal status to end */
  1183. seq_printf(m, " %s\n", stat_buf+1);
  1184. seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
  1185. info->tx_active,info->bh_requested,info->bh_running,
  1186. info->pending_bh);
  1187. }
  1188. /* Called to print information about devices
  1189. */
  1190. static int synclinkmp_proc_show(struct seq_file *m, void *v)
  1191. {
  1192. SLMP_INFO *info;
  1193. seq_printf(m, "synclinkmp driver:%s\n", driver_version);
  1194. info = synclinkmp_device_list;
  1195. while( info ) {
  1196. line_info(m, info);
  1197. info = info->next_device;
  1198. }
  1199. return 0;
  1200. }
  1201. /* Return the count of bytes in transmit buffer
  1202. */
  1203. static int chars_in_buffer(struct tty_struct *tty)
  1204. {
  1205. SLMP_INFO *info = tty->driver_data;
  1206. if (sanity_check(info, tty->name, "chars_in_buffer"))
  1207. return 0;
  1208. if (debug_level >= DEBUG_LEVEL_INFO)
  1209. printk("%s(%d):%s chars_in_buffer()=%d\n",
  1210. __FILE__, __LINE__, info->device_name, info->tx_count);
  1211. return info->tx_count;
  1212. }
  1213. /* Signal remote device to throttle send data (our receive data)
  1214. */
  1215. static void throttle(struct tty_struct * tty)
  1216. {
  1217. SLMP_INFO *info = tty->driver_data;
  1218. unsigned long flags;
  1219. if (debug_level >= DEBUG_LEVEL_INFO)
  1220. printk("%s(%d):%s throttle() entry\n",
  1221. __FILE__,__LINE__, info->device_name );
  1222. if (sanity_check(info, tty->name, "throttle"))
  1223. return;
  1224. if (I_IXOFF(tty))
  1225. send_xchar(tty, STOP_CHAR(tty));
  1226. if (C_CRTSCTS(tty)) {
  1227. spin_lock_irqsave(&info->lock,flags);
  1228. info->serial_signals &= ~SerialSignal_RTS;
  1229. set_signals(info);
  1230. spin_unlock_irqrestore(&info->lock,flags);
  1231. }
  1232. }
  1233. /* Signal remote device to stop throttling send data (our receive data)
  1234. */
  1235. static void unthrottle(struct tty_struct * tty)
  1236. {
  1237. SLMP_INFO *info = tty->driver_data;
  1238. unsigned long flags;
  1239. if (debug_level >= DEBUG_LEVEL_INFO)
  1240. printk("%s(%d):%s unthrottle() entry\n",
  1241. __FILE__,__LINE__, info->device_name );
  1242. if (sanity_check(info, tty->name, "unthrottle"))
  1243. return;
  1244. if (I_IXOFF(tty)) {
  1245. if (info->x_char)
  1246. info->x_char = 0;
  1247. else
  1248. send_xchar(tty, START_CHAR(tty));
  1249. }
  1250. if (C_CRTSCTS(tty)) {
  1251. spin_lock_irqsave(&info->lock,flags);
  1252. info->serial_signals |= SerialSignal_RTS;
  1253. set_signals(info);
  1254. spin_unlock_irqrestore(&info->lock,flags);
  1255. }
  1256. }
  1257. /* set or clear transmit break condition
  1258. * break_state -1=set break condition, 0=clear
  1259. */
  1260. static int set_break(struct tty_struct *tty, int break_state)
  1261. {
  1262. unsigned char RegValue;
  1263. SLMP_INFO * info = tty->driver_data;
  1264. unsigned long flags;
  1265. if (debug_level >= DEBUG_LEVEL_INFO)
  1266. printk("%s(%d):%s set_break(%d)\n",
  1267. __FILE__,__LINE__, info->device_name, break_state);
  1268. if (sanity_check(info, tty->name, "set_break"))
  1269. return -EINVAL;
  1270. spin_lock_irqsave(&info->lock,flags);
  1271. RegValue = read_reg(info, CTL);
  1272. if (break_state == -1)
  1273. RegValue |= BIT3;
  1274. else
  1275. RegValue &= ~BIT3;
  1276. write_reg(info, CTL, RegValue);
  1277. spin_unlock_irqrestore(&info->lock,flags);
  1278. return 0;
  1279. }
  1280. #if SYNCLINK_GENERIC_HDLC
  1281. /**
  1282. * hdlcdev_attach - called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
  1283. * @dev: pointer to network device structure
  1284. * @encoding: serial encoding setting
  1285. * @parity: FCS setting
  1286. *
  1287. * Set encoding and frame check sequence (FCS) options.
  1288. *
  1289. * Return: 0 if success, otherwise error code
  1290. */
  1291. static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
  1292. unsigned short parity)
  1293. {
  1294. SLMP_INFO *info = dev_to_port(dev);
  1295. unsigned char new_encoding;
  1296. unsigned short new_crctype;
  1297. /* return error if TTY interface open */
  1298. if (info->port.count)
  1299. return -EBUSY;
  1300. switch (encoding)
  1301. {
  1302. case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
  1303. case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
  1304. case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
  1305. case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
  1306. case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
  1307. default: return -EINVAL;
  1308. }
  1309. switch (parity)
  1310. {
  1311. case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
  1312. case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
  1313. case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
  1314. default: return -EINVAL;
  1315. }
  1316. info->params.encoding = new_encoding;
  1317. info->params.crc_type = new_crctype;
  1318. /* if network interface up, reprogram hardware */
  1319. if (info->netcount)
  1320. program_hw(info);
  1321. return 0;
  1322. }
  1323. /**
  1324. * hdlcdev_xmit - called by generic HDLC layer to send frame
  1325. * @skb: socket buffer containing HDLC frame
  1326. * @dev: pointer to network device structure
  1327. */
  1328. static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
  1329. struct net_device *dev)
  1330. {
  1331. SLMP_INFO *info = dev_to_port(dev);
  1332. unsigned long flags;
  1333. if (debug_level >= DEBUG_LEVEL_INFO)
  1334. printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
  1335. /* stop sending until this frame completes */
  1336. netif_stop_queue(dev);
  1337. /* copy data to device buffers */
  1338. info->tx_count = skb->len;
  1339. tx_load_dma_buffer(info, skb->data, skb->len);
  1340. /* update network statistics */
  1341. dev->stats.tx_packets++;
  1342. dev->stats.tx_bytes += skb->len;
  1343. /* done with socket buffer, so free it */
  1344. dev_kfree_skb(skb);
  1345. /* save start time for transmit timeout detection */
  1346. netif_trans_update(dev);
  1347. /* start hardware transmitter if necessary */
  1348. spin_lock_irqsave(&info->lock,flags);
  1349. if (!info->tx_active)
  1350. tx_start(info);
  1351. spin_unlock_irqrestore(&info->lock,flags);
  1352. return NETDEV_TX_OK;
  1353. }
  1354. /**
  1355. * hdlcdev_open - called by network layer when interface enabled
  1356. * @dev: pointer to network device structure
  1357. *
  1358. * Claim resources and initialize hardware.
  1359. *
  1360. * Return: 0 if success, otherwise error code
  1361. */
  1362. static int hdlcdev_open(struct net_device *dev)
  1363. {
  1364. SLMP_INFO *info = dev_to_port(dev);
  1365. int rc;
  1366. unsigned long flags;
  1367. if (debug_level >= DEBUG_LEVEL_INFO)
  1368. printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
  1369. /* generic HDLC layer open processing */
  1370. rc = hdlc_open(dev);
  1371. if (rc)
  1372. return rc;
  1373. /* arbitrate between network and tty opens */
  1374. spin_lock_irqsave(&info->netlock, flags);
  1375. if (info->port.count != 0 || info->netcount != 0) {
  1376. printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
  1377. spin_unlock_irqrestore(&info->netlock, flags);
  1378. return -EBUSY;
  1379. }
  1380. info->netcount=1;
  1381. spin_unlock_irqrestore(&info->netlock, flags);
  1382. /* claim resources and init adapter */
  1383. if ((rc = startup(info)) != 0) {
  1384. spin_lock_irqsave(&info->netlock, flags);
  1385. info->netcount=0;
  1386. spin_unlock_irqrestore(&info->netlock, flags);
  1387. return rc;
  1388. }
  1389. /* assert RTS and DTR, apply hardware settings */
  1390. info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
  1391. program_hw(info);
  1392. /* enable network layer transmit */
  1393. netif_trans_update(dev);
  1394. netif_start_queue(dev);
  1395. /* inform generic HDLC layer of current DCD status */
  1396. spin_lock_irqsave(&info->lock, flags);
  1397. get_signals(info);
  1398. spin_unlock_irqrestore(&info->lock, flags);
  1399. if (info->serial_signals & SerialSignal_DCD)
  1400. netif_carrier_on(dev);
  1401. else
  1402. netif_carrier_off(dev);
  1403. return 0;
  1404. }
  1405. /**
  1406. * hdlcdev_close - called by network layer when interface is disabled
  1407. * @dev: pointer to network device structure
  1408. *
  1409. * Shutdown hardware and release resources.
  1410. *
  1411. * Return: 0 if success, otherwise error code
  1412. */
  1413. static int hdlcdev_close(struct net_device *dev)
  1414. {
  1415. SLMP_INFO *info = dev_to_port(dev);
  1416. unsigned long flags;
  1417. if (debug_level >= DEBUG_LEVEL_INFO)
  1418. printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
  1419. netif_stop_queue(dev);
  1420. /* shutdown adapter and release resources */
  1421. shutdown(info);
  1422. hdlc_close(dev);
  1423. spin_lock_irqsave(&info->netlock, flags);
  1424. info->netcount=0;
  1425. spin_unlock_irqrestore(&info->netlock, flags);
  1426. return 0;
  1427. }
  1428. /**
  1429. * hdlcdev_ioctl - called by network layer to process IOCTL call to network device
  1430. * @dev: pointer to network device structure
  1431. * @ifr: pointer to network interface request structure
  1432. * @cmd: IOCTL command code
  1433. *
  1434. * Return: 0 if success, otherwise error code
  1435. */
  1436. static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  1437. {
  1438. const size_t size = sizeof(sync_serial_settings);
  1439. sync_serial_settings new_line;
  1440. sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
  1441. SLMP_INFO *info = dev_to_port(dev);
  1442. unsigned int flags;
  1443. if (debug_level >= DEBUG_LEVEL_INFO)
  1444. printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
  1445. /* return error if TTY interface open */
  1446. if (info->port.count)
  1447. return -EBUSY;
  1448. if (cmd != SIOCWANDEV)
  1449. return hdlc_ioctl(dev, ifr, cmd);
  1450. switch(ifr->ifr_settings.type) {
  1451. case IF_GET_IFACE: /* return current sync_serial_settings */
  1452. ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
  1453. if (ifr->ifr_settings.size < size) {
  1454. ifr->ifr_settings.size = size; /* data size wanted */
  1455. return -ENOBUFS;
  1456. }
  1457. flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  1458. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  1459. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  1460. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
  1461. memset(&new_line, 0, sizeof(new_line));
  1462. switch (flags){
  1463. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
  1464. case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
  1465. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
  1466. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
  1467. default: new_line.clock_type = CLOCK_DEFAULT;
  1468. }
  1469. new_line.clock_rate = info->params.clock_speed;
  1470. new_line.loopback = info->params.loopback ? 1:0;
  1471. if (copy_to_user(line, &new_line, size))
  1472. return -EFAULT;
  1473. return 0;
  1474. case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
  1475. if(!capable(CAP_NET_ADMIN))
  1476. return -EPERM;
  1477. if (copy_from_user(&new_line, line, size))
  1478. return -EFAULT;
  1479. switch (new_line.clock_type)
  1480. {
  1481. case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
  1482. case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
  1483. case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
  1484. case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
  1485. case CLOCK_DEFAULT: flags = info->params.flags &
  1486. (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  1487. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  1488. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  1489. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
  1490. default: return -EINVAL;
  1491. }
  1492. if (new_line.loopback != 0 && new_line.loopback != 1)
  1493. return -EINVAL;
  1494. info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  1495. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  1496. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  1497. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
  1498. info->params.flags |= flags;
  1499. info->params.loopback = new_line.loopback;
  1500. if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
  1501. info->params.clock_speed = new_line.clock_rate;
  1502. else
  1503. info->params.clock_speed = 0;
  1504. /* if network interface up, reprogram hardware */
  1505. if (info->netcount)
  1506. program_hw(info);
  1507. return 0;
  1508. default:
  1509. return hdlc_ioctl(dev, ifr, cmd);
  1510. }
  1511. }
  1512. /**
  1513. * hdlcdev_tx_timeout - called by network layer when transmit timeout is detected
  1514. * @dev: pointer to network device structure
  1515. */
  1516. static void hdlcdev_tx_timeout(struct net_device *dev, unsigned int txqueue)
  1517. {
  1518. SLMP_INFO *info = dev_to_port(dev);
  1519. unsigned long flags;
  1520. if (debug_level >= DEBUG_LEVEL_INFO)
  1521. printk("hdlcdev_tx_timeout(%s)\n",dev->name);
  1522. dev->stats.tx_errors++;
  1523. dev->stats.tx_aborted_errors++;
  1524. spin_lock_irqsave(&info->lock,flags);
  1525. tx_stop(info);
  1526. spin_unlock_irqrestore(&info->lock,flags);
  1527. netif_wake_queue(dev);
  1528. }
  1529. /**
  1530. * hdlcdev_tx_done - called by device driver when transmit completes
  1531. * @info: pointer to device instance information
  1532. *
  1533. * Reenable network layer transmit if stopped.
  1534. */
  1535. static void hdlcdev_tx_done(SLMP_INFO *info)
  1536. {
  1537. if (netif_queue_stopped(info->netdev))
  1538. netif_wake_queue(info->netdev);
  1539. }
  1540. /**
  1541. * hdlcdev_rx - called by device driver when frame received
  1542. * @info: pointer to device instance information
  1543. * @buf: pointer to buffer contianing frame data
  1544. * @size: count of data bytes in buf
  1545. *
  1546. * Pass frame to network layer.
  1547. */
  1548. static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
  1549. {
  1550. struct sk_buff *skb = dev_alloc_skb(size);
  1551. struct net_device *dev = info->netdev;
  1552. if (debug_level >= DEBUG_LEVEL_INFO)
  1553. printk("hdlcdev_rx(%s)\n",dev->name);
  1554. if (skb == NULL) {
  1555. printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
  1556. dev->name);
  1557. dev->stats.rx_dropped++;
  1558. return;
  1559. }
  1560. skb_put_data(skb, buf, size);
  1561. skb->protocol = hdlc_type_trans(skb, dev);
  1562. dev->stats.rx_packets++;
  1563. dev->stats.rx_bytes += size;
  1564. netif_rx(skb);
  1565. }
  1566. static const struct net_device_ops hdlcdev_ops = {
  1567. .ndo_open = hdlcdev_open,
  1568. .ndo_stop = hdlcdev_close,
  1569. .ndo_start_xmit = hdlc_start_xmit,
  1570. .ndo_do_ioctl = hdlcdev_ioctl,
  1571. .ndo_tx_timeout = hdlcdev_tx_timeout,
  1572. };
  1573. /**
  1574. * hdlcdev_init - called by device driver when adding device instance
  1575. * @info: pointer to device instance information
  1576. *
  1577. * Do generic HDLC initialization.
  1578. *
  1579. * Return: 0 if success, otherwise error code
  1580. */
  1581. static int hdlcdev_init(SLMP_INFO *info)
  1582. {
  1583. int rc;
  1584. struct net_device *dev;
  1585. hdlc_device *hdlc;
  1586. /* allocate and initialize network and HDLC layer objects */
  1587. dev = alloc_hdlcdev(info);
  1588. if (!dev) {
  1589. printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
  1590. return -ENOMEM;
  1591. }
  1592. /* for network layer reporting purposes only */
  1593. dev->mem_start = info->phys_sca_base;
  1594. dev->mem_end = info->phys_sca_base + SCA_BASE_SIZE - 1;
  1595. dev->irq = info->irq_level;
  1596. /* network layer callbacks and settings */
  1597. dev->netdev_ops = &hdlcdev_ops;
  1598. dev->watchdog_timeo = 10 * HZ;
  1599. dev->tx_queue_len = 50;
  1600. /* generic HDLC layer callbacks and settings */
  1601. hdlc = dev_to_hdlc(dev);
  1602. hdlc->attach = hdlcdev_attach;
  1603. hdlc->xmit = hdlcdev_xmit;
  1604. /* register objects with HDLC layer */
  1605. rc = register_hdlc_device(dev);
  1606. if (rc) {
  1607. printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
  1608. free_netdev(dev);
  1609. return rc;
  1610. }
  1611. info->netdev = dev;
  1612. return 0;
  1613. }
  1614. /**
  1615. * hdlcdev_exit - called by device driver when removing device instance
  1616. * @info: pointer to device instance information
  1617. *
  1618. * Do generic HDLC cleanup.
  1619. */
  1620. static void hdlcdev_exit(SLMP_INFO *info)
  1621. {
  1622. unregister_hdlc_device(info->netdev);
  1623. free_netdev(info->netdev);
  1624. info->netdev = NULL;
  1625. }
  1626. #endif /* CONFIG_HDLC */
  1627. /* Return next bottom half action to perform.
  1628. * Return Value: BH action code or 0 if nothing to do.
  1629. */
  1630. static int bh_action(SLMP_INFO *info)
  1631. {
  1632. unsigned long flags;
  1633. int rc = 0;
  1634. spin_lock_irqsave(&info->lock,flags);
  1635. if (info->pending_bh & BH_RECEIVE) {
  1636. info->pending_bh &= ~BH_RECEIVE;
  1637. rc = BH_RECEIVE;
  1638. } else if (info->pending_bh & BH_TRANSMIT) {
  1639. info->pending_bh &= ~BH_TRANSMIT;
  1640. rc = BH_TRANSMIT;
  1641. } else if (info->pending_bh & BH_STATUS) {
  1642. info->pending_bh &= ~BH_STATUS;
  1643. rc = BH_STATUS;
  1644. }
  1645. if (!rc) {
  1646. /* Mark BH routine as complete */
  1647. info->bh_running = false;
  1648. info->bh_requested = false;
  1649. }
  1650. spin_unlock_irqrestore(&info->lock,flags);
  1651. return rc;
  1652. }
  1653. /* Perform bottom half processing of work items queued by ISR.
  1654. */
  1655. static void bh_handler(struct work_struct *work)
  1656. {
  1657. SLMP_INFO *info = container_of(work, SLMP_INFO, task);
  1658. int action;
  1659. if ( debug_level >= DEBUG_LEVEL_BH )
  1660. printk( "%s(%d):%s bh_handler() entry\n",
  1661. __FILE__,__LINE__,info->device_name);
  1662. info->bh_running = true;
  1663. while((action = bh_action(info)) != 0) {
  1664. /* Process work item */
  1665. if ( debug_level >= DEBUG_LEVEL_BH )
  1666. printk( "%s(%d):%s bh_handler() work item action=%d\n",
  1667. __FILE__,__LINE__,info->device_name, action);
  1668. switch (action) {
  1669. case BH_RECEIVE:
  1670. bh_receive(info);
  1671. break;
  1672. case BH_TRANSMIT:
  1673. bh_transmit(info);
  1674. break;
  1675. case BH_STATUS:
  1676. bh_status(info);
  1677. break;
  1678. default:
  1679. /* unknown work item ID */
  1680. printk("%s(%d):%s Unknown work item ID=%08X!\n",
  1681. __FILE__,__LINE__,info->device_name,action);
  1682. break;
  1683. }
  1684. }
  1685. if ( debug_level >= DEBUG_LEVEL_BH )
  1686. printk( "%s(%d):%s bh_handler() exit\n",
  1687. __FILE__,__LINE__,info->device_name);
  1688. }
  1689. static void bh_receive(SLMP_INFO *info)
  1690. {
  1691. if ( debug_level >= DEBUG_LEVEL_BH )
  1692. printk( "%s(%d):%s bh_receive()\n",
  1693. __FILE__,__LINE__,info->device_name);
  1694. while( rx_get_frame(info) );
  1695. }
  1696. static void bh_transmit(SLMP_INFO *info)
  1697. {
  1698. struct tty_struct *tty = info->port.tty;
  1699. if ( debug_level >= DEBUG_LEVEL_BH )
  1700. printk( "%s(%d):%s bh_transmit() entry\n",
  1701. __FILE__,__LINE__,info->device_name);
  1702. if (tty)
  1703. tty_wakeup(tty);
  1704. }
  1705. static void bh_status(SLMP_INFO *info)
  1706. {
  1707. if ( debug_level >= DEBUG_LEVEL_BH )
  1708. printk( "%s(%d):%s bh_status() entry\n",
  1709. __FILE__,__LINE__,info->device_name);
  1710. info->ri_chkcount = 0;
  1711. info->dsr_chkcount = 0;
  1712. info->dcd_chkcount = 0;
  1713. info->cts_chkcount = 0;
  1714. }
  1715. static void isr_timer(SLMP_INFO * info)
  1716. {
  1717. unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
  1718. /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
  1719. write_reg(info, IER2, 0);
  1720. /* TMCS, Timer Control/Status Register
  1721. *
  1722. * 07 CMF, Compare match flag (read only) 1=match
  1723. * 06 ECMI, CMF Interrupt Enable: 0=disabled
  1724. * 05 Reserved, must be 0
  1725. * 04 TME, Timer Enable
  1726. * 03..00 Reserved, must be 0
  1727. *
  1728. * 0000 0000
  1729. */
  1730. write_reg(info, (unsigned char)(timer + TMCS), 0);
  1731. info->irq_occurred = true;
  1732. if ( debug_level >= DEBUG_LEVEL_ISR )
  1733. printk("%s(%d):%s isr_timer()\n",
  1734. __FILE__,__LINE__,info->device_name);
  1735. }
  1736. static void isr_rxint(SLMP_INFO * info)
  1737. {
  1738. struct tty_struct *tty = info->port.tty;
  1739. struct mgsl_icount *icount = &info->icount;
  1740. unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
  1741. unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
  1742. /* clear status bits */
  1743. if (status)
  1744. write_reg(info, SR1, status);
  1745. if (status2)
  1746. write_reg(info, SR2, status2);
  1747. if ( debug_level >= DEBUG_LEVEL_ISR )
  1748. printk("%s(%d):%s isr_rxint status=%02X %02x\n",
  1749. __FILE__,__LINE__,info->device_name,status,status2);
  1750. if (info->params.mode == MGSL_MODE_ASYNC) {
  1751. if (status & BRKD) {
  1752. icount->brk++;
  1753. /* process break detection if tty control
  1754. * is not set to ignore it
  1755. */
  1756. if (!(status & info->ignore_status_mask1)) {
  1757. if (info->read_status_mask1 & BRKD) {
  1758. tty_insert_flip_char(&info->port, 0, TTY_BREAK);
  1759. if (tty && (info->port.flags & ASYNC_SAK))
  1760. do_SAK(tty);
  1761. }
  1762. }
  1763. }
  1764. }
  1765. else {
  1766. if (status & (FLGD|IDLD)) {
  1767. if (status & FLGD)
  1768. info->icount.exithunt++;
  1769. else if (status & IDLD)
  1770. info->icount.rxidle++;
  1771. wake_up_interruptible(&info->event_wait_q);
  1772. }
  1773. }
  1774. if (status & CDCD) {
  1775. /* simulate a common modem status change interrupt
  1776. * for our handler
  1777. */
  1778. get_signals( info );
  1779. isr_io_pin(info,
  1780. MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
  1781. }
  1782. }
  1783. /*
  1784. * handle async rx data interrupts
  1785. */
  1786. static void isr_rxrdy(SLMP_INFO * info)
  1787. {
  1788. u16 status;
  1789. unsigned char DataByte;
  1790. struct mgsl_icount *icount = &info->icount;
  1791. if ( debug_level >= DEBUG_LEVEL_ISR )
  1792. printk("%s(%d):%s isr_rxrdy\n",
  1793. __FILE__,__LINE__,info->device_name);
  1794. while((status = read_reg(info,CST0)) & BIT0)
  1795. {
  1796. int flag = 0;
  1797. bool over = false;
  1798. DataByte = read_reg(info,TRB);
  1799. icount->rx++;
  1800. if ( status & (PE + FRME + OVRN) ) {
  1801. printk("%s(%d):%s rxerr=%04X\n",
  1802. __FILE__,__LINE__,info->device_name,status);
  1803. /* update error statistics */
  1804. if (status & PE)
  1805. icount->parity++;
  1806. else if (status & FRME)
  1807. icount->frame++;
  1808. else if (status & OVRN)
  1809. icount->overrun++;
  1810. /* discard char if tty control flags say so */
  1811. if (status & info->ignore_status_mask2)
  1812. continue;
  1813. status &= info->read_status_mask2;
  1814. if (status & PE)
  1815. flag = TTY_PARITY;
  1816. else if (status & FRME)
  1817. flag = TTY_FRAME;
  1818. if (status & OVRN) {
  1819. /* Overrun is special, since it's
  1820. * reported immediately, and doesn't
  1821. * affect the current character
  1822. */
  1823. over = true;
  1824. }
  1825. } /* end of if (error) */
  1826. tty_insert_flip_char(&info->port, DataByte, flag);
  1827. if (over)
  1828. tty_insert_flip_char(&info->port, 0, TTY_OVERRUN);
  1829. }
  1830. if ( debug_level >= DEBUG_LEVEL_ISR ) {
  1831. printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
  1832. __FILE__,__LINE__,info->device_name,
  1833. icount->rx,icount->brk,icount->parity,
  1834. icount->frame,icount->overrun);
  1835. }
  1836. tty_flip_buffer_push(&info->port);
  1837. }
  1838. static void isr_txeom(SLMP_INFO * info, unsigned char status)
  1839. {
  1840. if ( debug_level >= DEBUG_LEVEL_ISR )
  1841. printk("%s(%d):%s isr_txeom status=%02x\n",
  1842. __FILE__,__LINE__,info->device_name,status);
  1843. write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
  1844. write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
  1845. write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
  1846. if (status & UDRN) {
  1847. write_reg(info, CMD, TXRESET);
  1848. write_reg(info, CMD, TXENABLE);
  1849. } else
  1850. write_reg(info, CMD, TXBUFCLR);
  1851. /* disable and clear tx interrupts */
  1852. info->ie0_value &= ~TXRDYE;
  1853. info->ie1_value &= ~(IDLE + UDRN);
  1854. write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
  1855. write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
  1856. if ( info->tx_active ) {
  1857. if (info->params.mode != MGSL_MODE_ASYNC) {
  1858. if (status & UDRN)
  1859. info->icount.txunder++;
  1860. else if (status & IDLE)
  1861. info->icount.txok++;
  1862. }
  1863. info->tx_active = false;
  1864. info->tx_count = info->tx_put = info->tx_get = 0;
  1865. del_timer(&info->tx_timer);
  1866. if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
  1867. info->serial_signals &= ~SerialSignal_RTS;
  1868. info->drop_rts_on_tx_done = false;
  1869. set_signals(info);
  1870. }
  1871. #if SYNCLINK_GENERIC_HDLC
  1872. if (info->netcount)
  1873. hdlcdev_tx_done(info);
  1874. else
  1875. #endif
  1876. {
  1877. if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
  1878. tx_stop(info);
  1879. return;
  1880. }
  1881. info->pending_bh |= BH_TRANSMIT;
  1882. }
  1883. }
  1884. }
  1885. /*
  1886. * handle tx status interrupts
  1887. */
  1888. static void isr_txint(SLMP_INFO * info)
  1889. {
  1890. unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
  1891. /* clear status bits */
  1892. write_reg(info, SR1, status);
  1893. if ( debug_level >= DEBUG_LEVEL_ISR )
  1894. printk("%s(%d):%s isr_txint status=%02x\n",
  1895. __FILE__,__LINE__,info->device_name,status);
  1896. if (status & (UDRN + IDLE))
  1897. isr_txeom(info, status);
  1898. if (status & CCTS) {
  1899. /* simulate a common modem status change interrupt
  1900. * for our handler
  1901. */
  1902. get_signals( info );
  1903. isr_io_pin(info,
  1904. MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
  1905. }
  1906. }
  1907. /*
  1908. * handle async tx data interrupts
  1909. */
  1910. static void isr_txrdy(SLMP_INFO * info)
  1911. {
  1912. if ( debug_level >= DEBUG_LEVEL_ISR )
  1913. printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
  1914. __FILE__,__LINE__,info->device_name,info->tx_count);
  1915. if (info->params.mode != MGSL_MODE_ASYNC) {
  1916. /* disable TXRDY IRQ, enable IDLE IRQ */
  1917. info->ie0_value &= ~TXRDYE;
  1918. info->ie1_value |= IDLE;
  1919. write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
  1920. return;
  1921. }
  1922. if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
  1923. tx_stop(info);
  1924. return;
  1925. }
  1926. if ( info->tx_count )
  1927. tx_load_fifo( info );
  1928. else {
  1929. info->tx_active = false;
  1930. info->ie0_value &= ~TXRDYE;
  1931. write_reg(info, IE0, info->ie0_value);
  1932. }
  1933. if (info->tx_count < WAKEUP_CHARS)
  1934. info->pending_bh |= BH_TRANSMIT;
  1935. }
  1936. static void isr_rxdmaok(SLMP_INFO * info)
  1937. {
  1938. /* BIT7 = EOT (end of transfer)
  1939. * BIT6 = EOM (end of message/frame)
  1940. */
  1941. unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
  1942. /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
  1943. write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
  1944. if ( debug_level >= DEBUG_LEVEL_ISR )
  1945. printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
  1946. __FILE__,__LINE__,info->device_name,status);
  1947. info->pending_bh |= BH_RECEIVE;
  1948. }
  1949. static void isr_rxdmaerror(SLMP_INFO * info)
  1950. {
  1951. /* BIT5 = BOF (buffer overflow)
  1952. * BIT4 = COF (counter overflow)
  1953. */
  1954. unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
  1955. /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
  1956. write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
  1957. if ( debug_level >= DEBUG_LEVEL_ISR )
  1958. printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
  1959. __FILE__,__LINE__,info->device_name,status);
  1960. info->rx_overflow = true;
  1961. info->pending_bh |= BH_RECEIVE;
  1962. }
  1963. static void isr_txdmaok(SLMP_INFO * info)
  1964. {
  1965. unsigned char status_reg1 = read_reg(info, SR1);
  1966. write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
  1967. write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
  1968. write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
  1969. if ( debug_level >= DEBUG_LEVEL_ISR )
  1970. printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
  1971. __FILE__,__LINE__,info->device_name,status_reg1);
  1972. /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
  1973. write_reg16(info, TRC0, 0);
  1974. info->ie0_value |= TXRDYE;
  1975. write_reg(info, IE0, info->ie0_value);
  1976. }
  1977. static void isr_txdmaerror(SLMP_INFO * info)
  1978. {
  1979. /* BIT5 = BOF (buffer overflow)
  1980. * BIT4 = COF (counter overflow)
  1981. */
  1982. unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
  1983. /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
  1984. write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
  1985. if ( debug_level >= DEBUG_LEVEL_ISR )
  1986. printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
  1987. __FILE__,__LINE__,info->device_name,status);
  1988. }
  1989. /* handle input serial signal changes
  1990. */
  1991. static void isr_io_pin( SLMP_INFO *info, u16 status )
  1992. {
  1993. struct mgsl_icount *icount;
  1994. if ( debug_level >= DEBUG_LEVEL_ISR )
  1995. printk("%s(%d):isr_io_pin status=%04X\n",
  1996. __FILE__,__LINE__,status);
  1997. if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
  1998. MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
  1999. icount = &info->icount;
  2000. /* update input line counters */
  2001. if (status & MISCSTATUS_RI_LATCHED) {
  2002. icount->rng++;
  2003. if ( status & SerialSignal_RI )
  2004. info->input_signal_events.ri_up++;
  2005. else
  2006. info->input_signal_events.ri_down++;
  2007. }
  2008. if (status & MISCSTATUS_DSR_LATCHED) {
  2009. icount->dsr++;
  2010. if ( status & SerialSignal_DSR )
  2011. info->input_signal_events.dsr_up++;
  2012. else
  2013. info->input_signal_events.dsr_down++;
  2014. }
  2015. if (status & MISCSTATUS_DCD_LATCHED) {
  2016. if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
  2017. info->ie1_value &= ~CDCD;
  2018. write_reg(info, IE1, info->ie1_value);
  2019. }
  2020. icount->dcd++;
  2021. if (status & SerialSignal_DCD) {
  2022. info->input_signal_events.dcd_up++;
  2023. } else
  2024. info->input_signal_events.dcd_down++;
  2025. #if SYNCLINK_GENERIC_HDLC
  2026. if (info->netcount) {
  2027. if (status & SerialSignal_DCD)
  2028. netif_carrier_on(info->netdev);
  2029. else
  2030. netif_carrier_off(info->netdev);
  2031. }
  2032. #endif
  2033. }
  2034. if (status & MISCSTATUS_CTS_LATCHED)
  2035. {
  2036. if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
  2037. info->ie1_value &= ~CCTS;
  2038. write_reg(info, IE1, info->ie1_value);
  2039. }
  2040. icount->cts++;
  2041. if ( status & SerialSignal_CTS )
  2042. info->input_signal_events.cts_up++;
  2043. else
  2044. info->input_signal_events.cts_down++;
  2045. }
  2046. wake_up_interruptible(&info->status_event_wait_q);
  2047. wake_up_interruptible(&info->event_wait_q);
  2048. if (tty_port_check_carrier(&info->port) &&
  2049. (status & MISCSTATUS_DCD_LATCHED) ) {
  2050. if ( debug_level >= DEBUG_LEVEL_ISR )
  2051. printk("%s CD now %s...", info->device_name,
  2052. (status & SerialSignal_DCD) ? "on" : "off");
  2053. if (status & SerialSignal_DCD)
  2054. wake_up_interruptible(&info->port.open_wait);
  2055. else {
  2056. if ( debug_level >= DEBUG_LEVEL_ISR )
  2057. printk("doing serial hangup...");
  2058. if (info->port.tty)
  2059. tty_hangup(info->port.tty);
  2060. }
  2061. }
  2062. if (tty_port_cts_enabled(&info->port) &&
  2063. (status & MISCSTATUS_CTS_LATCHED) ) {
  2064. if ( info->port.tty ) {
  2065. if (info->port.tty->hw_stopped) {
  2066. if (status & SerialSignal_CTS) {
  2067. if ( debug_level >= DEBUG_LEVEL_ISR )
  2068. printk("CTS tx start...");
  2069. info->port.tty->hw_stopped = 0;
  2070. tx_start(info);
  2071. info->pending_bh |= BH_TRANSMIT;
  2072. return;
  2073. }
  2074. } else {
  2075. if (!(status & SerialSignal_CTS)) {
  2076. if ( debug_level >= DEBUG_LEVEL_ISR )
  2077. printk("CTS tx stop...");
  2078. info->port.tty->hw_stopped = 1;
  2079. tx_stop(info);
  2080. }
  2081. }
  2082. }
  2083. }
  2084. }
  2085. info->pending_bh |= BH_STATUS;
  2086. }
  2087. /* Interrupt service routine entry point.
  2088. *
  2089. * Arguments:
  2090. * irq interrupt number that caused interrupt
  2091. * dev_id device ID supplied during interrupt registration
  2092. * regs interrupted processor context
  2093. */
  2094. static irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id)
  2095. {
  2096. SLMP_INFO *info = dev_id;
  2097. unsigned char status, status0, status1=0;
  2098. unsigned char dmastatus, dmastatus0, dmastatus1=0;
  2099. unsigned char timerstatus0, timerstatus1=0;
  2100. unsigned char shift;
  2101. unsigned int i;
  2102. unsigned short tmp;
  2103. if ( debug_level >= DEBUG_LEVEL_ISR )
  2104. printk(KERN_DEBUG "%s(%d): synclinkmp_interrupt(%d)entry.\n",
  2105. __FILE__, __LINE__, info->irq_level);
  2106. spin_lock(&info->lock);
  2107. for(;;) {
  2108. /* get status for SCA0 (ports 0-1) */
  2109. tmp = read_reg16(info, ISR0); /* get ISR0 and ISR1 in one read */
  2110. status0 = (unsigned char)tmp;
  2111. dmastatus0 = (unsigned char)(tmp>>8);
  2112. timerstatus0 = read_reg(info, ISR2);
  2113. if ( debug_level >= DEBUG_LEVEL_ISR )
  2114. printk(KERN_DEBUG "%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
  2115. __FILE__, __LINE__, info->device_name,
  2116. status0, dmastatus0, timerstatus0);
  2117. if (info->port_count == 4) {
  2118. /* get status for SCA1 (ports 2-3) */
  2119. tmp = read_reg16(info->port_array[2], ISR0);
  2120. status1 = (unsigned char)tmp;
  2121. dmastatus1 = (unsigned char)(tmp>>8);
  2122. timerstatus1 = read_reg(info->port_array[2], ISR2);
  2123. if ( debug_level >= DEBUG_LEVEL_ISR )
  2124. printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
  2125. __FILE__,__LINE__,info->device_name,
  2126. status1,dmastatus1,timerstatus1);
  2127. }
  2128. if (!status0 && !dmastatus0 && !timerstatus0 &&
  2129. !status1 && !dmastatus1 && !timerstatus1)
  2130. break;
  2131. for(i=0; i < info->port_count ; i++) {
  2132. if (info->port_array[i] == NULL)
  2133. continue;
  2134. if (i < 2) {
  2135. status = status0;
  2136. dmastatus = dmastatus0;
  2137. } else {
  2138. status = status1;
  2139. dmastatus = dmastatus1;
  2140. }
  2141. shift = i & 1 ? 4 :0;
  2142. if (status & BIT0 << shift)
  2143. isr_rxrdy(info->port_array[i]);
  2144. if (status & BIT1 << shift)
  2145. isr_txrdy(info->port_array[i]);
  2146. if (status & BIT2 << shift)
  2147. isr_rxint(info->port_array[i]);
  2148. if (status & BIT3 << shift)
  2149. isr_txint(info->port_array[i]);
  2150. if (dmastatus & BIT0 << shift)
  2151. isr_rxdmaerror(info->port_array[i]);
  2152. if (dmastatus & BIT1 << shift)
  2153. isr_rxdmaok(info->port_array[i]);
  2154. if (dmastatus & BIT2 << shift)
  2155. isr_txdmaerror(info->port_array[i]);
  2156. if (dmastatus & BIT3 << shift)
  2157. isr_txdmaok(info->port_array[i]);
  2158. }
  2159. if (timerstatus0 & (BIT5 | BIT4))
  2160. isr_timer(info->port_array[0]);
  2161. if (timerstatus0 & (BIT7 | BIT6))
  2162. isr_timer(info->port_array[1]);
  2163. if (timerstatus1 & (BIT5 | BIT4))
  2164. isr_timer(info->port_array[2]);
  2165. if (timerstatus1 & (BIT7 | BIT6))
  2166. isr_timer(info->port_array[3]);
  2167. }
  2168. for(i=0; i < info->port_count ; i++) {
  2169. SLMP_INFO * port = info->port_array[i];
  2170. /* Request bottom half processing if there's something
  2171. * for it to do and the bh is not already running.
  2172. *
  2173. * Note: startup adapter diags require interrupts.
  2174. * do not request bottom half processing if the
  2175. * device is not open in a normal mode.
  2176. */
  2177. if ( port && (port->port.count || port->netcount) &&
  2178. port->pending_bh && !port->bh_running &&
  2179. !port->bh_requested ) {
  2180. if ( debug_level >= DEBUG_LEVEL_ISR )
  2181. printk("%s(%d):%s queueing bh task.\n",
  2182. __FILE__,__LINE__,port->device_name);
  2183. schedule_work(&port->task);
  2184. port->bh_requested = true;
  2185. }
  2186. }
  2187. spin_unlock(&info->lock);
  2188. if ( debug_level >= DEBUG_LEVEL_ISR )
  2189. printk(KERN_DEBUG "%s(%d):synclinkmp_interrupt(%d)exit.\n",
  2190. __FILE__, __LINE__, info->irq_level);
  2191. return IRQ_HANDLED;
  2192. }
  2193. /* Initialize and start device.
  2194. */
  2195. static int startup(SLMP_INFO * info)
  2196. {
  2197. if ( debug_level >= DEBUG_LEVEL_INFO )
  2198. printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
  2199. if (tty_port_initialized(&info->port))
  2200. return 0;
  2201. if (!info->tx_buf) {
  2202. info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
  2203. if (!info->tx_buf) {
  2204. printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
  2205. __FILE__,__LINE__,info->device_name);
  2206. return -ENOMEM;
  2207. }
  2208. }
  2209. info->pending_bh = 0;
  2210. memset(&info->icount, 0, sizeof(info->icount));
  2211. /* program hardware for current parameters */
  2212. reset_port(info);
  2213. change_params(info);
  2214. mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
  2215. if (info->port.tty)
  2216. clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
  2217. tty_port_set_initialized(&info->port, 1);
  2218. return 0;
  2219. }
  2220. /* Called by close() and hangup() to shutdown hardware
  2221. */
  2222. static void shutdown(SLMP_INFO * info)
  2223. {
  2224. unsigned long flags;
  2225. if (!tty_port_initialized(&info->port))
  2226. return;
  2227. if (debug_level >= DEBUG_LEVEL_INFO)
  2228. printk("%s(%d):%s synclinkmp_shutdown()\n",
  2229. __FILE__,__LINE__, info->device_name );
  2230. /* clear status wait queue because status changes */
  2231. /* can't happen after shutting down the hardware */
  2232. wake_up_interruptible(&info->status_event_wait_q);
  2233. wake_up_interruptible(&info->event_wait_q);
  2234. del_timer(&info->tx_timer);
  2235. del_timer(&info->status_timer);
  2236. kfree(info->tx_buf);
  2237. info->tx_buf = NULL;
  2238. spin_lock_irqsave(&info->lock,flags);
  2239. reset_port(info);
  2240. if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
  2241. info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
  2242. set_signals(info);
  2243. }
  2244. spin_unlock_irqrestore(&info->lock,flags);
  2245. if (info->port.tty)
  2246. set_bit(TTY_IO_ERROR, &info->port.tty->flags);
  2247. tty_port_set_initialized(&info->port, 0);
  2248. }
  2249. static void program_hw(SLMP_INFO *info)
  2250. {
  2251. unsigned long flags;
  2252. spin_lock_irqsave(&info->lock,flags);
  2253. rx_stop(info);
  2254. tx_stop(info);
  2255. info->tx_count = info->tx_put = info->tx_get = 0;
  2256. if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
  2257. hdlc_mode(info);
  2258. else
  2259. async_mode(info);
  2260. set_signals(info);
  2261. info->dcd_chkcount = 0;
  2262. info->cts_chkcount = 0;
  2263. info->ri_chkcount = 0;
  2264. info->dsr_chkcount = 0;
  2265. info->ie1_value |= (CDCD|CCTS);
  2266. write_reg(info, IE1, info->ie1_value);
  2267. get_signals(info);
  2268. if (info->netcount || (info->port.tty && info->port.tty->termios.c_cflag & CREAD) )
  2269. rx_start(info);
  2270. spin_unlock_irqrestore(&info->lock,flags);
  2271. }
  2272. /* Reconfigure adapter based on new parameters
  2273. */
  2274. static void change_params(SLMP_INFO *info)
  2275. {
  2276. unsigned cflag;
  2277. int bits_per_char;
  2278. if (!info->port.tty)
  2279. return;
  2280. if (debug_level >= DEBUG_LEVEL_INFO)
  2281. printk("%s(%d):%s change_params()\n",
  2282. __FILE__,__LINE__, info->device_name );
  2283. cflag = info->port.tty->termios.c_cflag;
  2284. /* if B0 rate (hangup) specified then negate RTS and DTR */
  2285. /* otherwise assert RTS and DTR */
  2286. if (cflag & CBAUD)
  2287. info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
  2288. else
  2289. info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
  2290. /* byte size and parity */
  2291. switch (cflag & CSIZE) {
  2292. case CS5: info->params.data_bits = 5; break;
  2293. case CS6: info->params.data_bits = 6; break;
  2294. case CS7: info->params.data_bits = 7; break;
  2295. case CS8: info->params.data_bits = 8; break;
  2296. /* Never happens, but GCC is too dumb to figure it out */
  2297. default: info->params.data_bits = 7; break;
  2298. }
  2299. if (cflag & CSTOPB)
  2300. info->params.stop_bits = 2;
  2301. else
  2302. info->params.stop_bits = 1;
  2303. info->params.parity = ASYNC_PARITY_NONE;
  2304. if (cflag & PARENB) {
  2305. if (cflag & PARODD)
  2306. info->params.parity = ASYNC_PARITY_ODD;
  2307. else
  2308. info->params.parity = ASYNC_PARITY_EVEN;
  2309. #ifdef CMSPAR
  2310. if (cflag & CMSPAR)
  2311. info->params.parity = ASYNC_PARITY_SPACE;
  2312. #endif
  2313. }
  2314. /* calculate number of jiffies to transmit a full
  2315. * FIFO (32 bytes) at specified data rate
  2316. */
  2317. bits_per_char = info->params.data_bits +
  2318. info->params.stop_bits + 1;
  2319. /* if port data rate is set to 460800 or less then
  2320. * allow tty settings to override, otherwise keep the
  2321. * current data rate.
  2322. */
  2323. if (info->params.data_rate <= 460800) {
  2324. info->params.data_rate = tty_get_baud_rate(info->port.tty);
  2325. }
  2326. if ( info->params.data_rate ) {
  2327. info->timeout = (32*HZ*bits_per_char) /
  2328. info->params.data_rate;
  2329. }
  2330. info->timeout += HZ/50; /* Add .02 seconds of slop */
  2331. tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
  2332. tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
  2333. /* process tty input control flags */
  2334. info->read_status_mask2 = OVRN;
  2335. if (I_INPCK(info->port.tty))
  2336. info->read_status_mask2 |= PE | FRME;
  2337. if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
  2338. info->read_status_mask1 |= BRKD;
  2339. if (I_IGNPAR(info->port.tty))
  2340. info->ignore_status_mask2 |= PE | FRME;
  2341. if (I_IGNBRK(info->port.tty)) {
  2342. info->ignore_status_mask1 |= BRKD;
  2343. /* If ignoring parity and break indicators, ignore
  2344. * overruns too. (For real raw support).
  2345. */
  2346. if (I_IGNPAR(info->port.tty))
  2347. info->ignore_status_mask2 |= OVRN;
  2348. }
  2349. program_hw(info);
  2350. }
  2351. static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
  2352. {
  2353. int err;
  2354. if (debug_level >= DEBUG_LEVEL_INFO)
  2355. printk("%s(%d):%s get_params()\n",
  2356. __FILE__,__LINE__, info->device_name);
  2357. if (!user_icount) {
  2358. memset(&info->icount, 0, sizeof(info->icount));
  2359. } else {
  2360. mutex_lock(&info->port.mutex);
  2361. COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
  2362. mutex_unlock(&info->port.mutex);
  2363. if (err)
  2364. return -EFAULT;
  2365. }
  2366. return 0;
  2367. }
  2368. static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
  2369. {
  2370. int err;
  2371. if (debug_level >= DEBUG_LEVEL_INFO)
  2372. printk("%s(%d):%s get_params()\n",
  2373. __FILE__,__LINE__, info->device_name);
  2374. mutex_lock(&info->port.mutex);
  2375. COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
  2376. mutex_unlock(&info->port.mutex);
  2377. if (err) {
  2378. if ( debug_level >= DEBUG_LEVEL_INFO )
  2379. printk( "%s(%d):%s get_params() user buffer copy failed\n",
  2380. __FILE__,__LINE__,info->device_name);
  2381. return -EFAULT;
  2382. }
  2383. return 0;
  2384. }
  2385. static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
  2386. {
  2387. unsigned long flags;
  2388. MGSL_PARAMS tmp_params;
  2389. int err;
  2390. if (debug_level >= DEBUG_LEVEL_INFO)
  2391. printk("%s(%d):%s set_params\n",
  2392. __FILE__,__LINE__,info->device_name );
  2393. COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
  2394. if (err) {
  2395. if ( debug_level >= DEBUG_LEVEL_INFO )
  2396. printk( "%s(%d):%s set_params() user buffer copy failed\n",
  2397. __FILE__,__LINE__,info->device_name);
  2398. return -EFAULT;
  2399. }
  2400. mutex_lock(&info->port.mutex);
  2401. spin_lock_irqsave(&info->lock,flags);
  2402. memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
  2403. spin_unlock_irqrestore(&info->lock,flags);
  2404. change_params(info);
  2405. mutex_unlock(&info->port.mutex);
  2406. return 0;
  2407. }
  2408. static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
  2409. {
  2410. int err;
  2411. if (debug_level >= DEBUG_LEVEL_INFO)
  2412. printk("%s(%d):%s get_txidle()=%d\n",
  2413. __FILE__,__LINE__, info->device_name, info->idle_mode);
  2414. COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
  2415. if (err) {
  2416. if ( debug_level >= DEBUG_LEVEL_INFO )
  2417. printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
  2418. __FILE__,__LINE__,info->device_name);
  2419. return -EFAULT;
  2420. }
  2421. return 0;
  2422. }
  2423. static int set_txidle(SLMP_INFO * info, int idle_mode)
  2424. {
  2425. unsigned long flags;
  2426. if (debug_level >= DEBUG_LEVEL_INFO)
  2427. printk("%s(%d):%s set_txidle(%d)\n",
  2428. __FILE__,__LINE__,info->device_name, idle_mode );
  2429. spin_lock_irqsave(&info->lock,flags);
  2430. info->idle_mode = idle_mode;
  2431. tx_set_idle( info );
  2432. spin_unlock_irqrestore(&info->lock,flags);
  2433. return 0;
  2434. }
  2435. static int tx_enable(SLMP_INFO * info, int enable)
  2436. {
  2437. unsigned long flags;
  2438. if (debug_level >= DEBUG_LEVEL_INFO)
  2439. printk("%s(%d):%s tx_enable(%d)\n",
  2440. __FILE__,__LINE__,info->device_name, enable);
  2441. spin_lock_irqsave(&info->lock,flags);
  2442. if ( enable ) {
  2443. if ( !info->tx_enabled ) {
  2444. tx_start(info);
  2445. }
  2446. } else {
  2447. if ( info->tx_enabled )
  2448. tx_stop(info);
  2449. }
  2450. spin_unlock_irqrestore(&info->lock,flags);
  2451. return 0;
  2452. }
  2453. /* abort send HDLC frame
  2454. */
  2455. static int tx_abort(SLMP_INFO * info)
  2456. {
  2457. unsigned long flags;
  2458. if (debug_level >= DEBUG_LEVEL_INFO)
  2459. printk("%s(%d):%s tx_abort()\n",
  2460. __FILE__,__LINE__,info->device_name);
  2461. spin_lock_irqsave(&info->lock,flags);
  2462. if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
  2463. info->ie1_value &= ~UDRN;
  2464. info->ie1_value |= IDLE;
  2465. write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
  2466. write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
  2467. write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
  2468. write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
  2469. write_reg(info, CMD, TXABORT);
  2470. }
  2471. spin_unlock_irqrestore(&info->lock,flags);
  2472. return 0;
  2473. }
  2474. static int rx_enable(SLMP_INFO * info, int enable)
  2475. {
  2476. unsigned long flags;
  2477. if (debug_level >= DEBUG_LEVEL_INFO)
  2478. printk("%s(%d):%s rx_enable(%d)\n",
  2479. __FILE__,__LINE__,info->device_name,enable);
  2480. spin_lock_irqsave(&info->lock,flags);
  2481. if ( enable ) {
  2482. if ( !info->rx_enabled )
  2483. rx_start(info);
  2484. } else {
  2485. if ( info->rx_enabled )
  2486. rx_stop(info);
  2487. }
  2488. spin_unlock_irqrestore(&info->lock,flags);
  2489. return 0;
  2490. }
  2491. /* wait for specified event to occur
  2492. */
  2493. static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
  2494. {
  2495. unsigned long flags;
  2496. int s;
  2497. int rc=0;
  2498. struct mgsl_icount cprev, cnow;
  2499. int events;
  2500. int mask;
  2501. struct _input_signal_events oldsigs, newsigs;
  2502. DECLARE_WAITQUEUE(wait, current);
  2503. COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
  2504. if (rc) {
  2505. return -EFAULT;
  2506. }
  2507. if (debug_level >= DEBUG_LEVEL_INFO)
  2508. printk("%s(%d):%s wait_mgsl_event(%d)\n",
  2509. __FILE__,__LINE__,info->device_name,mask);
  2510. spin_lock_irqsave(&info->lock,flags);
  2511. /* return immediately if state matches requested events */
  2512. get_signals(info);
  2513. s = info->serial_signals;
  2514. events = mask &
  2515. ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
  2516. ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
  2517. ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
  2518. ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
  2519. if (events) {
  2520. spin_unlock_irqrestore(&info->lock,flags);
  2521. goto exit;
  2522. }
  2523. /* save current irq counts */
  2524. cprev = info->icount;
  2525. oldsigs = info->input_signal_events;
  2526. /* enable hunt and idle irqs if needed */
  2527. if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
  2528. unsigned char oldval = info->ie1_value;
  2529. unsigned char newval = oldval +
  2530. (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
  2531. (mask & MgslEvent_IdleReceived ? IDLD:0);
  2532. if ( oldval != newval ) {
  2533. info->ie1_value = newval;
  2534. write_reg(info, IE1, info->ie1_value);
  2535. }
  2536. }
  2537. set_current_state(TASK_INTERRUPTIBLE);
  2538. add_wait_queue(&info->event_wait_q, &wait);
  2539. spin_unlock_irqrestore(&info->lock,flags);
  2540. for(;;) {
  2541. schedule();
  2542. if (signal_pending(current)) {
  2543. rc = -ERESTARTSYS;
  2544. break;
  2545. }
  2546. /* get current irq counts */
  2547. spin_lock_irqsave(&info->lock,flags);
  2548. cnow = info->icount;
  2549. newsigs = info->input_signal_events;
  2550. set_current_state(TASK_INTERRUPTIBLE);
  2551. spin_unlock_irqrestore(&info->lock,flags);
  2552. /* if no change, wait aborted for some reason */
  2553. if (newsigs.dsr_up == oldsigs.dsr_up &&
  2554. newsigs.dsr_down == oldsigs.dsr_down &&
  2555. newsigs.dcd_up == oldsigs.dcd_up &&
  2556. newsigs.dcd_down == oldsigs.dcd_down &&
  2557. newsigs.cts_up == oldsigs.cts_up &&
  2558. newsigs.cts_down == oldsigs.cts_down &&
  2559. newsigs.ri_up == oldsigs.ri_up &&
  2560. newsigs.ri_down == oldsigs.ri_down &&
  2561. cnow.exithunt == cprev.exithunt &&
  2562. cnow.rxidle == cprev.rxidle) {
  2563. rc = -EIO;
  2564. break;
  2565. }
  2566. events = mask &
  2567. ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
  2568. (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
  2569. (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
  2570. (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
  2571. (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
  2572. (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
  2573. (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
  2574. (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
  2575. (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
  2576. (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
  2577. if (events)
  2578. break;
  2579. cprev = cnow;
  2580. oldsigs = newsigs;
  2581. }
  2582. remove_wait_queue(&info->event_wait_q, &wait);
  2583. set_current_state(TASK_RUNNING);
  2584. if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
  2585. spin_lock_irqsave(&info->lock,flags);
  2586. if (!waitqueue_active(&info->event_wait_q)) {
  2587. /* disable enable exit hunt mode/idle rcvd IRQs */
  2588. info->ie1_value &= ~(FLGD|IDLD);
  2589. write_reg(info, IE1, info->ie1_value);
  2590. }
  2591. spin_unlock_irqrestore(&info->lock,flags);
  2592. }
  2593. exit:
  2594. if ( rc == 0 )
  2595. PUT_USER(rc, events, mask_ptr);
  2596. return rc;
  2597. }
  2598. static int modem_input_wait(SLMP_INFO *info,int arg)
  2599. {
  2600. unsigned long flags;
  2601. int rc;
  2602. struct mgsl_icount cprev, cnow;
  2603. DECLARE_WAITQUEUE(wait, current);
  2604. /* save current irq counts */
  2605. spin_lock_irqsave(&info->lock,flags);
  2606. cprev = info->icount;
  2607. add_wait_queue(&info->status_event_wait_q, &wait);
  2608. set_current_state(TASK_INTERRUPTIBLE);
  2609. spin_unlock_irqrestore(&info->lock,flags);
  2610. for(;;) {
  2611. schedule();
  2612. if (signal_pending(current)) {
  2613. rc = -ERESTARTSYS;
  2614. break;
  2615. }
  2616. /* get new irq counts */
  2617. spin_lock_irqsave(&info->lock,flags);
  2618. cnow = info->icount;
  2619. set_current_state(TASK_INTERRUPTIBLE);
  2620. spin_unlock_irqrestore(&info->lock,flags);
  2621. /* if no change, wait aborted for some reason */
  2622. if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
  2623. cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
  2624. rc = -EIO;
  2625. break;
  2626. }
  2627. /* check for change in caller specified modem input */
  2628. if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
  2629. (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
  2630. (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
  2631. (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
  2632. rc = 0;
  2633. break;
  2634. }
  2635. cprev = cnow;
  2636. }
  2637. remove_wait_queue(&info->status_event_wait_q, &wait);
  2638. set_current_state(TASK_RUNNING);
  2639. return rc;
  2640. }
  2641. /* return the state of the serial control and status signals
  2642. */
  2643. static int tiocmget(struct tty_struct *tty)
  2644. {
  2645. SLMP_INFO *info = tty->driver_data;
  2646. unsigned int result;
  2647. unsigned long flags;
  2648. spin_lock_irqsave(&info->lock,flags);
  2649. get_signals(info);
  2650. spin_unlock_irqrestore(&info->lock,flags);
  2651. result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS : 0) |
  2652. ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR : 0) |
  2653. ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR : 0) |
  2654. ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG : 0) |
  2655. ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR : 0) |
  2656. ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS : 0);
  2657. if (debug_level >= DEBUG_LEVEL_INFO)
  2658. printk("%s(%d):%s tiocmget() value=%08X\n",
  2659. __FILE__,__LINE__, info->device_name, result );
  2660. return result;
  2661. }
  2662. /* set modem control signals (DTR/RTS)
  2663. */
  2664. static int tiocmset(struct tty_struct *tty,
  2665. unsigned int set, unsigned int clear)
  2666. {
  2667. SLMP_INFO *info = tty->driver_data;
  2668. unsigned long flags;
  2669. if (debug_level >= DEBUG_LEVEL_INFO)
  2670. printk("%s(%d):%s tiocmset(%x,%x)\n",
  2671. __FILE__,__LINE__,info->device_name, set, clear);
  2672. if (set & TIOCM_RTS)
  2673. info->serial_signals |= SerialSignal_RTS;
  2674. if (set & TIOCM_DTR)
  2675. info->serial_signals |= SerialSignal_DTR;
  2676. if (clear & TIOCM_RTS)
  2677. info->serial_signals &= ~SerialSignal_RTS;
  2678. if (clear & TIOCM_DTR)
  2679. info->serial_signals &= ~SerialSignal_DTR;
  2680. spin_lock_irqsave(&info->lock,flags);
  2681. set_signals(info);
  2682. spin_unlock_irqrestore(&info->lock,flags);
  2683. return 0;
  2684. }
  2685. static int carrier_raised(struct tty_port *port)
  2686. {
  2687. SLMP_INFO *info = container_of(port, SLMP_INFO, port);
  2688. unsigned long flags;
  2689. spin_lock_irqsave(&info->lock,flags);
  2690. get_signals(info);
  2691. spin_unlock_irqrestore(&info->lock,flags);
  2692. return (info->serial_signals & SerialSignal_DCD) ? 1 : 0;
  2693. }
  2694. static void dtr_rts(struct tty_port *port, int on)
  2695. {
  2696. SLMP_INFO *info = container_of(port, SLMP_INFO, port);
  2697. unsigned long flags;
  2698. spin_lock_irqsave(&info->lock,flags);
  2699. if (on)
  2700. info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
  2701. else
  2702. info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
  2703. set_signals(info);
  2704. spin_unlock_irqrestore(&info->lock,flags);
  2705. }
  2706. /* Block the current process until the specified port is ready to open.
  2707. */
  2708. static int block_til_ready(struct tty_struct *tty, struct file *filp,
  2709. SLMP_INFO *info)
  2710. {
  2711. DECLARE_WAITQUEUE(wait, current);
  2712. int retval;
  2713. bool do_clocal = false;
  2714. unsigned long flags;
  2715. int cd;
  2716. struct tty_port *port = &info->port;
  2717. if (debug_level >= DEBUG_LEVEL_INFO)
  2718. printk("%s(%d):%s block_til_ready()\n",
  2719. __FILE__,__LINE__, tty->driver->name );
  2720. if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) {
  2721. /* nonblock mode is set or port is not enabled */
  2722. /* just verify that callout device is not active */
  2723. tty_port_set_active(port, 1);
  2724. return 0;
  2725. }
  2726. if (C_CLOCAL(tty))
  2727. do_clocal = true;
  2728. /* Wait for carrier detect and the line to become
  2729. * free (i.e., not in use by the callout). While we are in
  2730. * this loop, port->count is dropped by one, so that
  2731. * close() knows when to free things. We restore it upon
  2732. * exit, either normal or abnormal.
  2733. */
  2734. retval = 0;
  2735. add_wait_queue(&port->open_wait, &wait);
  2736. if (debug_level >= DEBUG_LEVEL_INFO)
  2737. printk("%s(%d):%s block_til_ready() before block, count=%d\n",
  2738. __FILE__,__LINE__, tty->driver->name, port->count );
  2739. spin_lock_irqsave(&info->lock, flags);
  2740. port->count--;
  2741. spin_unlock_irqrestore(&info->lock, flags);
  2742. port->blocked_open++;
  2743. while (1) {
  2744. if (C_BAUD(tty) && tty_port_initialized(port))
  2745. tty_port_raise_dtr_rts(port);
  2746. set_current_state(TASK_INTERRUPTIBLE);
  2747. if (tty_hung_up_p(filp) || !tty_port_initialized(port)) {
  2748. retval = (port->flags & ASYNC_HUP_NOTIFY) ?
  2749. -EAGAIN : -ERESTARTSYS;
  2750. break;
  2751. }
  2752. cd = tty_port_carrier_raised(port);
  2753. if (do_clocal || cd)
  2754. break;
  2755. if (signal_pending(current)) {
  2756. retval = -ERESTARTSYS;
  2757. break;
  2758. }
  2759. if (debug_level >= DEBUG_LEVEL_INFO)
  2760. printk("%s(%d):%s block_til_ready() count=%d\n",
  2761. __FILE__,__LINE__, tty->driver->name, port->count );
  2762. tty_unlock(tty);
  2763. schedule();
  2764. tty_lock(tty);
  2765. }
  2766. set_current_state(TASK_RUNNING);
  2767. remove_wait_queue(&port->open_wait, &wait);
  2768. if (!tty_hung_up_p(filp))
  2769. port->count++;
  2770. port->blocked_open--;
  2771. if (debug_level >= DEBUG_LEVEL_INFO)
  2772. printk("%s(%d):%s block_til_ready() after, count=%d\n",
  2773. __FILE__,__LINE__, tty->driver->name, port->count );
  2774. if (!retval)
  2775. tty_port_set_active(port, 1);
  2776. return retval;
  2777. }
  2778. static int alloc_dma_bufs(SLMP_INFO *info)
  2779. {
  2780. unsigned short BuffersPerFrame;
  2781. unsigned short BufferCount;
  2782. // Force allocation to start at 64K boundary for each port.
  2783. // This is necessary because *all* buffer descriptors for a port
  2784. // *must* be in the same 64K block. All descriptors on a port
  2785. // share a common 'base' address (upper 8 bits of 24 bits) programmed
  2786. // into the CBP register.
  2787. info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
  2788. /* Calculate the number of DMA buffers necessary to hold the */
  2789. /* largest allowable frame size. Note: If the max frame size is */
  2790. /* not an even multiple of the DMA buffer size then we need to */
  2791. /* round the buffer count per frame up one. */
  2792. BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
  2793. if ( info->max_frame_size % SCABUFSIZE )
  2794. BuffersPerFrame++;
  2795. /* calculate total number of data buffers (SCABUFSIZE) possible
  2796. * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
  2797. * for the descriptor list (BUFFERLISTSIZE).
  2798. */
  2799. BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
  2800. /* limit number of buffers to maximum amount of descriptors */
  2801. if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
  2802. BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
  2803. /* use enough buffers to transmit one max size frame */
  2804. info->tx_buf_count = BuffersPerFrame + 1;
  2805. /* never use more than half the available buffers for transmit */
  2806. if (info->tx_buf_count > (BufferCount/2))
  2807. info->tx_buf_count = BufferCount/2;
  2808. if (info->tx_buf_count > SCAMAXDESC)
  2809. info->tx_buf_count = SCAMAXDESC;
  2810. /* use remaining buffers for receive */
  2811. info->rx_buf_count = BufferCount - info->tx_buf_count;
  2812. if (info->rx_buf_count > SCAMAXDESC)
  2813. info->rx_buf_count = SCAMAXDESC;
  2814. if ( debug_level >= DEBUG_LEVEL_INFO )
  2815. printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
  2816. __FILE__,__LINE__, info->device_name,
  2817. info->tx_buf_count,info->rx_buf_count);
  2818. if ( alloc_buf_list( info ) < 0 ||
  2819. alloc_frame_bufs(info,
  2820. info->rx_buf_list,
  2821. info->rx_buf_list_ex,
  2822. info->rx_buf_count) < 0 ||
  2823. alloc_frame_bufs(info,
  2824. info->tx_buf_list,
  2825. info->tx_buf_list_ex,
  2826. info->tx_buf_count) < 0 ||
  2827. alloc_tmp_rx_buf(info) < 0 ) {
  2828. printk("%s(%d):%s Can't allocate DMA buffer memory\n",
  2829. __FILE__,__LINE__, info->device_name);
  2830. return -ENOMEM;
  2831. }
  2832. rx_reset_buffers( info );
  2833. return 0;
  2834. }
  2835. /* Allocate DMA buffers for the transmit and receive descriptor lists.
  2836. */
  2837. static int alloc_buf_list(SLMP_INFO *info)
  2838. {
  2839. unsigned int i;
  2840. /* build list in adapter shared memory */
  2841. info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
  2842. info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
  2843. info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
  2844. memset(info->buffer_list, 0, BUFFERLISTSIZE);
  2845. /* Save virtual address pointers to the receive and */
  2846. /* transmit buffer lists. (Receive 1st). These pointers will */
  2847. /* be used by the processor to access the lists. */
  2848. info->rx_buf_list = (SCADESC *)info->buffer_list;
  2849. info->tx_buf_list = (SCADESC *)info->buffer_list;
  2850. info->tx_buf_list += info->rx_buf_count;
  2851. /* Build links for circular buffer entry lists (tx and rx)
  2852. *
  2853. * Note: links are physical addresses read by the SCA device
  2854. * to determine the next buffer entry to use.
  2855. */
  2856. for ( i = 0; i < info->rx_buf_count; i++ ) {
  2857. /* calculate and store physical address of this buffer entry */
  2858. info->rx_buf_list_ex[i].phys_entry =
  2859. info->buffer_list_phys + (i * SCABUFSIZE);
  2860. /* calculate and store physical address of */
  2861. /* next entry in cirular list of entries */
  2862. info->rx_buf_list[i].next = info->buffer_list_phys;
  2863. if ( i < info->rx_buf_count - 1 )
  2864. info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
  2865. info->rx_buf_list[i].length = SCABUFSIZE;
  2866. }
  2867. for ( i = 0; i < info->tx_buf_count; i++ ) {
  2868. /* calculate and store physical address of this buffer entry */
  2869. info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
  2870. ((info->rx_buf_count + i) * sizeof(SCADESC));
  2871. /* calculate and store physical address of */
  2872. /* next entry in cirular list of entries */
  2873. info->tx_buf_list[i].next = info->buffer_list_phys +
  2874. info->rx_buf_count * sizeof(SCADESC);
  2875. if ( i < info->tx_buf_count - 1 )
  2876. info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
  2877. }
  2878. return 0;
  2879. }
  2880. /* Allocate the frame DMA buffers used by the specified buffer list.
  2881. */
  2882. static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
  2883. {
  2884. int i;
  2885. unsigned long phys_addr;
  2886. for ( i = 0; i < count; i++ ) {
  2887. buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
  2888. phys_addr = info->port_array[0]->last_mem_alloc;
  2889. info->port_array[0]->last_mem_alloc += SCABUFSIZE;
  2890. buf_list[i].buf_ptr = (unsigned short)phys_addr;
  2891. buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
  2892. }
  2893. return 0;
  2894. }
  2895. static void free_dma_bufs(SLMP_INFO *info)
  2896. {
  2897. info->buffer_list = NULL;
  2898. info->rx_buf_list = NULL;
  2899. info->tx_buf_list = NULL;
  2900. }
  2901. /* allocate buffer large enough to hold max_frame_size.
  2902. * This buffer is used to pass an assembled frame to the line discipline.
  2903. */
  2904. static int alloc_tmp_rx_buf(SLMP_INFO *info)
  2905. {
  2906. info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
  2907. if (info->tmp_rx_buf == NULL)
  2908. return -ENOMEM;
  2909. /* unused flag buffer to satisfy receive_buf calling interface */
  2910. info->flag_buf = kzalloc(info->max_frame_size, GFP_KERNEL);
  2911. if (!info->flag_buf) {
  2912. kfree(info->tmp_rx_buf);
  2913. info->tmp_rx_buf = NULL;
  2914. return -ENOMEM;
  2915. }
  2916. return 0;
  2917. }
  2918. static void free_tmp_rx_buf(SLMP_INFO *info)
  2919. {
  2920. kfree(info->tmp_rx_buf);
  2921. info->tmp_rx_buf = NULL;
  2922. kfree(info->flag_buf);
  2923. info->flag_buf = NULL;
  2924. }
  2925. static int claim_resources(SLMP_INFO *info)
  2926. {
  2927. if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
  2928. printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
  2929. __FILE__,__LINE__,info->device_name, info->phys_memory_base);
  2930. info->init_error = DiagStatus_AddressConflict;
  2931. goto errout;
  2932. }
  2933. else
  2934. info->shared_mem_requested = true;
  2935. if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
  2936. printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
  2937. __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
  2938. info->init_error = DiagStatus_AddressConflict;
  2939. goto errout;
  2940. }
  2941. else
  2942. info->lcr_mem_requested = true;
  2943. if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
  2944. printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
  2945. __FILE__,__LINE__,info->device_name, info->phys_sca_base);
  2946. info->init_error = DiagStatus_AddressConflict;
  2947. goto errout;
  2948. }
  2949. else
  2950. info->sca_base_requested = true;
  2951. if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
  2952. printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
  2953. __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
  2954. info->init_error = DiagStatus_AddressConflict;
  2955. goto errout;
  2956. }
  2957. else
  2958. info->sca_statctrl_requested = true;
  2959. info->memory_base = ioremap(info->phys_memory_base,
  2960. SCA_MEM_SIZE);
  2961. if (!info->memory_base) {
  2962. printk( "%s(%d):%s Can't map shared memory, MemAddr=%08X\n",
  2963. __FILE__,__LINE__,info->device_name, info->phys_memory_base );
  2964. info->init_error = DiagStatus_CantAssignPciResources;
  2965. goto errout;
  2966. }
  2967. info->lcr_base = ioremap(info->phys_lcr_base, PAGE_SIZE);
  2968. if (!info->lcr_base) {
  2969. printk( "%s(%d):%s Can't map LCR memory, MemAddr=%08X\n",
  2970. __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
  2971. info->init_error = DiagStatus_CantAssignPciResources;
  2972. goto errout;
  2973. }
  2974. info->lcr_base += info->lcr_offset;
  2975. info->sca_base = ioremap(info->phys_sca_base, PAGE_SIZE);
  2976. if (!info->sca_base) {
  2977. printk( "%s(%d):%s Can't map SCA memory, MemAddr=%08X\n",
  2978. __FILE__,__LINE__,info->device_name, info->phys_sca_base );
  2979. info->init_error = DiagStatus_CantAssignPciResources;
  2980. goto errout;
  2981. }
  2982. info->sca_base += info->sca_offset;
  2983. info->statctrl_base = ioremap(info->phys_statctrl_base,
  2984. PAGE_SIZE);
  2985. if (!info->statctrl_base) {
  2986. printk( "%s(%d):%s Can't map SCA Status/Control memory, MemAddr=%08X\n",
  2987. __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
  2988. info->init_error = DiagStatus_CantAssignPciResources;
  2989. goto errout;
  2990. }
  2991. info->statctrl_base += info->statctrl_offset;
  2992. if ( !memory_test(info) ) {
  2993. printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
  2994. __FILE__,__LINE__,info->device_name, info->phys_memory_base );
  2995. info->init_error = DiagStatus_MemoryError;
  2996. goto errout;
  2997. }
  2998. return 0;
  2999. errout:
  3000. release_resources( info );
  3001. return -ENODEV;
  3002. }
  3003. static void release_resources(SLMP_INFO *info)
  3004. {
  3005. if ( debug_level >= DEBUG_LEVEL_INFO )
  3006. printk( "%s(%d):%s release_resources() entry\n",
  3007. __FILE__,__LINE__,info->device_name );
  3008. if ( info->irq_requested ) {
  3009. free_irq(info->irq_level, info);
  3010. info->irq_requested = false;
  3011. }
  3012. if ( info->shared_mem_requested ) {
  3013. release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
  3014. info->shared_mem_requested = false;
  3015. }
  3016. if ( info->lcr_mem_requested ) {
  3017. release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
  3018. info->lcr_mem_requested = false;
  3019. }
  3020. if ( info->sca_base_requested ) {
  3021. release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
  3022. info->sca_base_requested = false;
  3023. }
  3024. if ( info->sca_statctrl_requested ) {
  3025. release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
  3026. info->sca_statctrl_requested = false;
  3027. }
  3028. if (info->memory_base){
  3029. iounmap(info->memory_base);
  3030. info->memory_base = NULL;
  3031. }
  3032. if (info->sca_base) {
  3033. iounmap(info->sca_base - info->sca_offset);
  3034. info->sca_base=NULL;
  3035. }
  3036. if (info->statctrl_base) {
  3037. iounmap(info->statctrl_base - info->statctrl_offset);
  3038. info->statctrl_base=NULL;
  3039. }
  3040. if (info->lcr_base){
  3041. iounmap(info->lcr_base - info->lcr_offset);
  3042. info->lcr_base = NULL;
  3043. }
  3044. if ( debug_level >= DEBUG_LEVEL_INFO )
  3045. printk( "%s(%d):%s release_resources() exit\n",
  3046. __FILE__,__LINE__,info->device_name );
  3047. }
  3048. /* Add the specified device instance data structure to the
  3049. * global linked list of devices and increment the device count.
  3050. */
  3051. static int add_device(SLMP_INFO *info)
  3052. {
  3053. info->next_device = NULL;
  3054. info->line = synclinkmp_device_count;
  3055. sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
  3056. if (info->line < MAX_DEVICES) {
  3057. if (maxframe[info->line])
  3058. info->max_frame_size = maxframe[info->line];
  3059. }
  3060. synclinkmp_device_count++;
  3061. if ( !synclinkmp_device_list )
  3062. synclinkmp_device_list = info;
  3063. else {
  3064. SLMP_INFO *current_dev = synclinkmp_device_list;
  3065. while( current_dev->next_device )
  3066. current_dev = current_dev->next_device;
  3067. current_dev->next_device = info;
  3068. }
  3069. if ( info->max_frame_size < 4096 )
  3070. info->max_frame_size = 4096;
  3071. else if ( info->max_frame_size > 65535 )
  3072. info->max_frame_size = 65535;
  3073. printk( "SyncLink MultiPort %s: "
  3074. "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
  3075. info->device_name,
  3076. info->phys_sca_base,
  3077. info->phys_memory_base,
  3078. info->phys_statctrl_base,
  3079. info->phys_lcr_base,
  3080. info->irq_level,
  3081. info->max_frame_size );
  3082. #if SYNCLINK_GENERIC_HDLC
  3083. return hdlcdev_init(info);
  3084. #else
  3085. return 0;
  3086. #endif
  3087. }
  3088. static const struct tty_port_operations port_ops = {
  3089. .carrier_raised = carrier_raised,
  3090. .dtr_rts = dtr_rts,
  3091. };
  3092. /* Allocate and initialize a device instance structure
  3093. *
  3094. * Return Value: pointer to SLMP_INFO if success, otherwise NULL
  3095. */
  3096. static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
  3097. {
  3098. SLMP_INFO *info;
  3099. info = kzalloc(sizeof(SLMP_INFO),
  3100. GFP_KERNEL);
  3101. if (!info) {
  3102. printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
  3103. __FILE__,__LINE__, adapter_num, port_num);
  3104. } else {
  3105. tty_port_init(&info->port);
  3106. info->port.ops = &port_ops;
  3107. info->magic = MGSL_MAGIC;
  3108. INIT_WORK(&info->task, bh_handler);
  3109. info->max_frame_size = 4096;
  3110. info->port.close_delay = 5*HZ/10;
  3111. info->port.closing_wait = 30*HZ;
  3112. init_waitqueue_head(&info->status_event_wait_q);
  3113. init_waitqueue_head(&info->event_wait_q);
  3114. spin_lock_init(&info->netlock);
  3115. memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
  3116. info->idle_mode = HDLC_TXIDLE_FLAGS;
  3117. info->adapter_num = adapter_num;
  3118. info->port_num = port_num;
  3119. /* Copy configuration info to device instance data */
  3120. info->irq_level = pdev->irq;
  3121. info->phys_lcr_base = pci_resource_start(pdev,0);
  3122. info->phys_sca_base = pci_resource_start(pdev,2);
  3123. info->phys_memory_base = pci_resource_start(pdev,3);
  3124. info->phys_statctrl_base = pci_resource_start(pdev,4);
  3125. /* Because veremap only works on page boundaries we must map
  3126. * a larger area than is actually implemented for the LCR
  3127. * memory range. We map a full page starting at the page boundary.
  3128. */
  3129. info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
  3130. info->phys_lcr_base &= ~(PAGE_SIZE-1);
  3131. info->sca_offset = info->phys_sca_base & (PAGE_SIZE-1);
  3132. info->phys_sca_base &= ~(PAGE_SIZE-1);
  3133. info->statctrl_offset = info->phys_statctrl_base & (PAGE_SIZE-1);
  3134. info->phys_statctrl_base &= ~(PAGE_SIZE-1);
  3135. info->bus_type = MGSL_BUS_TYPE_PCI;
  3136. info->irq_flags = IRQF_SHARED;
  3137. timer_setup(&info->tx_timer, tx_timeout, 0);
  3138. timer_setup(&info->status_timer, status_timeout, 0);
  3139. /* Store the PCI9050 misc control register value because a flaw
  3140. * in the PCI9050 prevents LCR registers from being read if
  3141. * BIOS assigns an LCR base address with bit 7 set.
  3142. *
  3143. * Only the misc control register is accessed for which only
  3144. * write access is needed, so set an initial value and change
  3145. * bits to the device instance data as we write the value
  3146. * to the actual misc control register.
  3147. */
  3148. info->misc_ctrl_value = 0x087e4546;
  3149. /* initial port state is unknown - if startup errors
  3150. * occur, init_error will be set to indicate the
  3151. * problem. Once the port is fully initialized,
  3152. * this value will be set to 0 to indicate the
  3153. * port is available.
  3154. */
  3155. info->init_error = -1;
  3156. }
  3157. return info;
  3158. }
  3159. static int device_init(int adapter_num, struct pci_dev *pdev)
  3160. {
  3161. SLMP_INFO *port_array[SCA_MAX_PORTS];
  3162. int port, rc;
  3163. /* allocate device instances for up to SCA_MAX_PORTS devices */
  3164. for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
  3165. port_array[port] = alloc_dev(adapter_num,port,pdev);
  3166. if( port_array[port] == NULL ) {
  3167. for (--port; port >= 0; --port) {
  3168. tty_port_destroy(&port_array[port]->port);
  3169. kfree(port_array[port]);
  3170. }
  3171. return -ENOMEM;
  3172. }
  3173. }
  3174. /* give copy of port_array to all ports and add to device list */
  3175. for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
  3176. memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
  3177. rc = add_device( port_array[port] );
  3178. if (rc)
  3179. goto err_add;
  3180. spin_lock_init(&port_array[port]->lock);
  3181. }
  3182. /* Allocate and claim adapter resources */
  3183. if ( !claim_resources(port_array[0]) ) {
  3184. alloc_dma_bufs(port_array[0]);
  3185. /* copy resource information from first port to others */
  3186. for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
  3187. port_array[port]->lock = port_array[0]->lock;
  3188. port_array[port]->irq_level = port_array[0]->irq_level;
  3189. port_array[port]->memory_base = port_array[0]->memory_base;
  3190. port_array[port]->sca_base = port_array[0]->sca_base;
  3191. port_array[port]->statctrl_base = port_array[0]->statctrl_base;
  3192. port_array[port]->lcr_base = port_array[0]->lcr_base;
  3193. alloc_dma_bufs(port_array[port]);
  3194. }
  3195. rc = request_irq(port_array[0]->irq_level,
  3196. synclinkmp_interrupt,
  3197. port_array[0]->irq_flags,
  3198. port_array[0]->device_name,
  3199. port_array[0]);
  3200. if ( rc ) {
  3201. printk( "%s(%d):%s Can't request interrupt, IRQ=%d\n",
  3202. __FILE__,__LINE__,
  3203. port_array[0]->device_name,
  3204. port_array[0]->irq_level );
  3205. goto err_irq;
  3206. }
  3207. port_array[0]->irq_requested = true;
  3208. adapter_test(port_array[0]);
  3209. }
  3210. return 0;
  3211. err_irq:
  3212. release_resources( port_array[0] );
  3213. err_add:
  3214. for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
  3215. tty_port_destroy(&port_array[port]->port);
  3216. kfree(port_array[port]);
  3217. }
  3218. return rc;
  3219. }
  3220. static const struct tty_operations ops = {
  3221. .install = install,
  3222. .open = open,
  3223. .close = close,
  3224. .write = write,
  3225. .put_char = put_char,
  3226. .flush_chars = flush_chars,
  3227. .write_room = write_room,
  3228. .chars_in_buffer = chars_in_buffer,
  3229. .flush_buffer = flush_buffer,
  3230. .ioctl = ioctl,
  3231. .throttle = throttle,
  3232. .unthrottle = unthrottle,
  3233. .send_xchar = send_xchar,
  3234. .break_ctl = set_break,
  3235. .wait_until_sent = wait_until_sent,
  3236. .set_termios = set_termios,
  3237. .stop = tx_hold,
  3238. .start = tx_release,
  3239. .hangup = hangup,
  3240. .tiocmget = tiocmget,
  3241. .tiocmset = tiocmset,
  3242. .get_icount = get_icount,
  3243. .proc_show = synclinkmp_proc_show,
  3244. };
  3245. static void synclinkmp_cleanup(void)
  3246. {
  3247. int rc;
  3248. SLMP_INFO *info;
  3249. SLMP_INFO *tmp;
  3250. printk("Unloading %s %s\n", driver_name, driver_version);
  3251. if (serial_driver) {
  3252. rc = tty_unregister_driver(serial_driver);
  3253. if (rc)
  3254. printk("%s(%d) failed to unregister tty driver err=%d\n",
  3255. __FILE__,__LINE__,rc);
  3256. put_tty_driver(serial_driver);
  3257. }
  3258. /* reset devices */
  3259. info = synclinkmp_device_list;
  3260. while(info) {
  3261. reset_port(info);
  3262. info = info->next_device;
  3263. }
  3264. /* release devices */
  3265. info = synclinkmp_device_list;
  3266. while(info) {
  3267. #if SYNCLINK_GENERIC_HDLC
  3268. hdlcdev_exit(info);
  3269. #endif
  3270. free_dma_bufs(info);
  3271. free_tmp_rx_buf(info);
  3272. if ( info->port_num == 0 ) {
  3273. if (info->sca_base)
  3274. write_reg(info, LPR, 1); /* set low power mode */
  3275. release_resources(info);
  3276. }
  3277. tmp = info;
  3278. info = info->next_device;
  3279. tty_port_destroy(&tmp->port);
  3280. kfree(tmp);
  3281. }
  3282. pci_unregister_driver(&synclinkmp_pci_driver);
  3283. }
  3284. /* Driver initialization entry point.
  3285. */
  3286. static int __init synclinkmp_init(void)
  3287. {
  3288. int rc;
  3289. if (break_on_load) {
  3290. synclinkmp_get_text_ptr();
  3291. BREAKPOINT();
  3292. }
  3293. printk("%s %s\n", driver_name, driver_version);
  3294. if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
  3295. printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
  3296. return rc;
  3297. }
  3298. serial_driver = alloc_tty_driver(128);
  3299. if (!serial_driver) {
  3300. rc = -ENOMEM;
  3301. goto error;
  3302. }
  3303. /* Initialize the tty_driver structure */
  3304. serial_driver->driver_name = "synclinkmp";
  3305. serial_driver->name = "ttySLM";
  3306. serial_driver->major = ttymajor;
  3307. serial_driver->minor_start = 64;
  3308. serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
  3309. serial_driver->subtype = SERIAL_TYPE_NORMAL;
  3310. serial_driver->init_termios = tty_std_termios;
  3311. serial_driver->init_termios.c_cflag =
  3312. B9600 | CS8 | CREAD | HUPCL | CLOCAL;
  3313. serial_driver->init_termios.c_ispeed = 9600;
  3314. serial_driver->init_termios.c_ospeed = 9600;
  3315. serial_driver->flags = TTY_DRIVER_REAL_RAW;
  3316. tty_set_operations(serial_driver, &ops);
  3317. if ((rc = tty_register_driver(serial_driver)) < 0) {
  3318. printk("%s(%d):Couldn't register serial driver\n",
  3319. __FILE__,__LINE__);
  3320. put_tty_driver(serial_driver);
  3321. serial_driver = NULL;
  3322. goto error;
  3323. }
  3324. printk("%s %s, tty major#%d\n",
  3325. driver_name, driver_version,
  3326. serial_driver->major);
  3327. return 0;
  3328. error:
  3329. synclinkmp_cleanup();
  3330. return rc;
  3331. }
  3332. static void __exit synclinkmp_exit(void)
  3333. {
  3334. synclinkmp_cleanup();
  3335. }
  3336. module_init(synclinkmp_init);
  3337. module_exit(synclinkmp_exit);
  3338. /* Set the port for internal loopback mode.
  3339. * The TxCLK and RxCLK signals are generated from the BRG and
  3340. * the TxD is looped back to the RxD internally.
  3341. */
  3342. static void enable_loopback(SLMP_INFO *info, int enable)
  3343. {
  3344. if (enable) {
  3345. /* MD2 (Mode Register 2)
  3346. * 01..00 CNCT<1..0> Channel Connection 11=Local Loopback
  3347. */
  3348. write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
  3349. /* degate external TxC clock source */
  3350. info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
  3351. write_control_reg(info);
  3352. /* RXS/TXS (Rx/Tx clock source)
  3353. * 07 Reserved, must be 0
  3354. * 06..04 Clock Source, 100=BRG
  3355. * 03..00 Clock Divisor, 0000=1
  3356. */
  3357. write_reg(info, RXS, 0x40);
  3358. write_reg(info, TXS, 0x40);
  3359. } else {
  3360. /* MD2 (Mode Register 2)
  3361. * 01..00 CNCT<1..0> Channel connection, 0=normal
  3362. */
  3363. write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
  3364. /* RXS/TXS (Rx/Tx clock source)
  3365. * 07 Reserved, must be 0
  3366. * 06..04 Clock Source, 000=RxC/TxC Pin
  3367. * 03..00 Clock Divisor, 0000=1
  3368. */
  3369. write_reg(info, RXS, 0x00);
  3370. write_reg(info, TXS, 0x00);
  3371. }
  3372. /* set LinkSpeed if available, otherwise default to 2Mbps */
  3373. if (info->params.clock_speed)
  3374. set_rate(info, info->params.clock_speed);
  3375. else
  3376. set_rate(info, 3686400);
  3377. }
  3378. /* Set the baud rate register to the desired speed
  3379. *
  3380. * data_rate data rate of clock in bits per second
  3381. * A data rate of 0 disables the AUX clock.
  3382. */
  3383. static void set_rate( SLMP_INFO *info, u32 data_rate )
  3384. {
  3385. u32 TMCValue;
  3386. unsigned char BRValue;
  3387. u32 Divisor=0;
  3388. /* fBRG = fCLK/(TMC * 2^BR)
  3389. */
  3390. if (data_rate != 0) {
  3391. Divisor = 14745600/data_rate;
  3392. if (!Divisor)
  3393. Divisor = 1;
  3394. TMCValue = Divisor;
  3395. BRValue = 0;
  3396. if (TMCValue != 1 && TMCValue != 2) {
  3397. /* BRValue of 0 provides 50/50 duty cycle *only* when
  3398. * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
  3399. * 50/50 duty cycle.
  3400. */
  3401. BRValue = 1;
  3402. TMCValue >>= 1;
  3403. }
  3404. /* while TMCValue is too big for TMC register, divide
  3405. * by 2 and increment BR exponent.
  3406. */
  3407. for(; TMCValue > 256 && BRValue < 10; BRValue++)
  3408. TMCValue >>= 1;
  3409. write_reg(info, TXS,
  3410. (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
  3411. write_reg(info, RXS,
  3412. (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
  3413. write_reg(info, TMC, (unsigned char)TMCValue);
  3414. }
  3415. else {
  3416. write_reg(info, TXS,0);
  3417. write_reg(info, RXS,0);
  3418. write_reg(info, TMC, 0);
  3419. }
  3420. }
  3421. /* Disable receiver
  3422. */
  3423. static void rx_stop(SLMP_INFO *info)
  3424. {
  3425. if (debug_level >= DEBUG_LEVEL_ISR)
  3426. printk("%s(%d):%s rx_stop()\n",
  3427. __FILE__,__LINE__, info->device_name );
  3428. write_reg(info, CMD, RXRESET);
  3429. info->ie0_value &= ~RXRDYE;
  3430. write_reg(info, IE0, info->ie0_value); /* disable Rx data interrupts */
  3431. write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
  3432. write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
  3433. write_reg(info, RXDMA + DIR, 0); /* disable Rx DMA interrupts */
  3434. info->rx_enabled = false;
  3435. info->rx_overflow = false;
  3436. }
  3437. /* enable the receiver
  3438. */
  3439. static void rx_start(SLMP_INFO *info)
  3440. {
  3441. int i;
  3442. if (debug_level >= DEBUG_LEVEL_ISR)
  3443. printk("%s(%d):%s rx_start()\n",
  3444. __FILE__,__LINE__, info->device_name );
  3445. write_reg(info, CMD, RXRESET);
  3446. if ( info->params.mode == MGSL_MODE_HDLC ) {
  3447. /* HDLC, disabe IRQ on rxdata */
  3448. info->ie0_value &= ~RXRDYE;
  3449. write_reg(info, IE0, info->ie0_value);
  3450. /* Reset all Rx DMA buffers and program rx dma */
  3451. write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
  3452. write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
  3453. for (i = 0; i < info->rx_buf_count; i++) {
  3454. info->rx_buf_list[i].status = 0xff;
  3455. // throttle to 4 shared memory writes at a time to prevent
  3456. // hogging local bus (keep latency time for DMA requests low).
  3457. if (!(i % 4))
  3458. read_status_reg(info);
  3459. }
  3460. info->current_rx_buf = 0;
  3461. /* set current/1st descriptor address */
  3462. write_reg16(info, RXDMA + CDA,
  3463. info->rx_buf_list_ex[0].phys_entry);
  3464. /* set new last rx descriptor address */
  3465. write_reg16(info, RXDMA + EDA,
  3466. info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
  3467. /* set buffer length (shared by all rx dma data buffers) */
  3468. write_reg16(info, RXDMA + BFL, SCABUFSIZE);
  3469. write_reg(info, RXDMA + DIR, 0x60); /* enable Rx DMA interrupts (EOM/BOF) */
  3470. write_reg(info, RXDMA + DSR, 0xf2); /* clear Rx DMA IRQs, enable Rx DMA */
  3471. } else {
  3472. /* async, enable IRQ on rxdata */
  3473. info->ie0_value |= RXRDYE;
  3474. write_reg(info, IE0, info->ie0_value);
  3475. }
  3476. write_reg(info, CMD, RXENABLE);
  3477. info->rx_overflow = false;
  3478. info->rx_enabled = true;
  3479. }
  3480. /* Enable the transmitter and send a transmit frame if
  3481. * one is loaded in the DMA buffers.
  3482. */
  3483. static void tx_start(SLMP_INFO *info)
  3484. {
  3485. if (debug_level >= DEBUG_LEVEL_ISR)
  3486. printk("%s(%d):%s tx_start() tx_count=%d\n",
  3487. __FILE__,__LINE__, info->device_name,info->tx_count );
  3488. if (!info->tx_enabled ) {
  3489. write_reg(info, CMD, TXRESET);
  3490. write_reg(info, CMD, TXENABLE);
  3491. info->tx_enabled = true;
  3492. }
  3493. if ( info->tx_count ) {
  3494. /* If auto RTS enabled and RTS is inactive, then assert */
  3495. /* RTS and set a flag indicating that the driver should */
  3496. /* negate RTS when the transmission completes. */
  3497. info->drop_rts_on_tx_done = false;
  3498. if (info->params.mode != MGSL_MODE_ASYNC) {
  3499. if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
  3500. get_signals( info );
  3501. if ( !(info->serial_signals & SerialSignal_RTS) ) {
  3502. info->serial_signals |= SerialSignal_RTS;
  3503. set_signals( info );
  3504. info->drop_rts_on_tx_done = true;
  3505. }
  3506. }
  3507. write_reg16(info, TRC0,
  3508. (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
  3509. write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
  3510. write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
  3511. /* set TX CDA (current descriptor address) */
  3512. write_reg16(info, TXDMA + CDA,
  3513. info->tx_buf_list_ex[0].phys_entry);
  3514. /* set TX EDA (last descriptor address) */
  3515. write_reg16(info, TXDMA + EDA,
  3516. info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
  3517. /* enable underrun IRQ */
  3518. info->ie1_value &= ~IDLE;
  3519. info->ie1_value |= UDRN;
  3520. write_reg(info, IE1, info->ie1_value);
  3521. write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
  3522. write_reg(info, TXDMA + DIR, 0x40); /* enable Tx DMA interrupts (EOM) */
  3523. write_reg(info, TXDMA + DSR, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */
  3524. mod_timer(&info->tx_timer, jiffies +
  3525. msecs_to_jiffies(5000));
  3526. }
  3527. else {
  3528. tx_load_fifo(info);
  3529. /* async, enable IRQ on txdata */
  3530. info->ie0_value |= TXRDYE;
  3531. write_reg(info, IE0, info->ie0_value);
  3532. }
  3533. info->tx_active = true;
  3534. }
  3535. }
  3536. /* stop the transmitter and DMA
  3537. */
  3538. static void tx_stop( SLMP_INFO *info )
  3539. {
  3540. if (debug_level >= DEBUG_LEVEL_ISR)
  3541. printk("%s(%d):%s tx_stop()\n",
  3542. __FILE__,__LINE__, info->device_name );
  3543. del_timer(&info->tx_timer);
  3544. write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
  3545. write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
  3546. write_reg(info, CMD, TXRESET);
  3547. info->ie1_value &= ~(UDRN + IDLE);
  3548. write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
  3549. write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
  3550. info->ie0_value &= ~TXRDYE;
  3551. write_reg(info, IE0, info->ie0_value); /* disable tx data interrupts */
  3552. info->tx_enabled = false;
  3553. info->tx_active = false;
  3554. }
  3555. /* Fill the transmit FIFO until the FIFO is full or
  3556. * there is no more data to load.
  3557. */
  3558. static void tx_load_fifo(SLMP_INFO *info)
  3559. {
  3560. u8 TwoBytes[2];
  3561. /* do nothing is now tx data available and no XON/XOFF pending */
  3562. if ( !info->tx_count && !info->x_char )
  3563. return;
  3564. /* load the Transmit FIFO until FIFOs full or all data sent */
  3565. while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
  3566. /* there is more space in the transmit FIFO and */
  3567. /* there is more data in transmit buffer */
  3568. if ( (info->tx_count > 1) && !info->x_char ) {
  3569. /* write 16-bits */
  3570. TwoBytes[0] = info->tx_buf[info->tx_get++];
  3571. if (info->tx_get >= info->max_frame_size)
  3572. info->tx_get -= info->max_frame_size;
  3573. TwoBytes[1] = info->tx_buf[info->tx_get++];
  3574. if (info->tx_get >= info->max_frame_size)
  3575. info->tx_get -= info->max_frame_size;
  3576. write_reg16(info, TRB, *((u16 *)TwoBytes));
  3577. info->tx_count -= 2;
  3578. info->icount.tx += 2;
  3579. } else {
  3580. /* only 1 byte left to transmit or 1 FIFO slot left */
  3581. if (info->x_char) {
  3582. /* transmit pending high priority char */
  3583. write_reg(info, TRB, info->x_char);
  3584. info->x_char = 0;
  3585. } else {
  3586. write_reg(info, TRB, info->tx_buf[info->tx_get++]);
  3587. if (info->tx_get >= info->max_frame_size)
  3588. info->tx_get -= info->max_frame_size;
  3589. info->tx_count--;
  3590. }
  3591. info->icount.tx++;
  3592. }
  3593. }
  3594. }
  3595. /* Reset a port to a known state
  3596. */
  3597. static void reset_port(SLMP_INFO *info)
  3598. {
  3599. if (info->sca_base) {
  3600. tx_stop(info);
  3601. rx_stop(info);
  3602. info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
  3603. set_signals(info);
  3604. /* disable all port interrupts */
  3605. info->ie0_value = 0;
  3606. info->ie1_value = 0;
  3607. info->ie2_value = 0;
  3608. write_reg(info, IE0, info->ie0_value);
  3609. write_reg(info, IE1, info->ie1_value);
  3610. write_reg(info, IE2, info->ie2_value);
  3611. write_reg(info, CMD, CHRESET);
  3612. }
  3613. }
  3614. /* Reset all the ports to a known state.
  3615. */
  3616. static void reset_adapter(SLMP_INFO *info)
  3617. {
  3618. int i;
  3619. for ( i=0; i < SCA_MAX_PORTS; ++i) {
  3620. if (info->port_array[i])
  3621. reset_port(info->port_array[i]);
  3622. }
  3623. }
  3624. /* Program port for asynchronous communications.
  3625. */
  3626. static void async_mode(SLMP_INFO *info)
  3627. {
  3628. unsigned char RegValue;
  3629. tx_stop(info);
  3630. rx_stop(info);
  3631. /* MD0, Mode Register 0
  3632. *
  3633. * 07..05 PRCTL<2..0>, Protocol Mode, 000=async
  3634. * 04 AUTO, Auto-enable (RTS/CTS/DCD)
  3635. * 03 Reserved, must be 0
  3636. * 02 CRCCC, CRC Calculation, 0=disabled
  3637. * 01..00 STOP<1..0> Stop bits (00=1,10=2)
  3638. *
  3639. * 0000 0000
  3640. */
  3641. RegValue = 0x00;
  3642. if (info->params.stop_bits != 1)
  3643. RegValue |= BIT1;
  3644. write_reg(info, MD0, RegValue);
  3645. /* MD1, Mode Register 1
  3646. *
  3647. * 07..06 BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
  3648. * 05..04 TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
  3649. * 03..02 RXCHR<1..0>, rx char size
  3650. * 01..00 PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
  3651. *
  3652. * 0100 0000
  3653. */
  3654. RegValue = 0x40;
  3655. switch (info->params.data_bits) {
  3656. case 7: RegValue |= BIT4 + BIT2; break;
  3657. case 6: RegValue |= BIT5 + BIT3; break;
  3658. case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
  3659. }
  3660. if (info->params.parity != ASYNC_PARITY_NONE) {
  3661. RegValue |= BIT1;
  3662. if (info->params.parity == ASYNC_PARITY_ODD)
  3663. RegValue |= BIT0;
  3664. }
  3665. write_reg(info, MD1, RegValue);
  3666. /* MD2, Mode Register 2
  3667. *
  3668. * 07..02 Reserved, must be 0
  3669. * 01..00 CNCT<1..0> Channel connection, 00=normal 11=local loopback
  3670. *
  3671. * 0000 0000
  3672. */
  3673. RegValue = 0x00;
  3674. if (info->params.loopback)
  3675. RegValue |= (BIT1 + BIT0);
  3676. write_reg(info, MD2, RegValue);
  3677. /* RXS, Receive clock source
  3678. *
  3679. * 07 Reserved, must be 0
  3680. * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
  3681. * 03..00 RXBR<3..0>, rate divisor, 0000=1
  3682. */
  3683. RegValue=BIT6;
  3684. write_reg(info, RXS, RegValue);
  3685. /* TXS, Transmit clock source
  3686. *
  3687. * 07 Reserved, must be 0
  3688. * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
  3689. * 03..00 RXBR<3..0>, rate divisor, 0000=1
  3690. */
  3691. RegValue=BIT6;
  3692. write_reg(info, TXS, RegValue);
  3693. /* Control Register
  3694. *
  3695. * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
  3696. */
  3697. info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
  3698. write_control_reg(info);
  3699. tx_set_idle(info);
  3700. /* RRC Receive Ready Control 0
  3701. *
  3702. * 07..05 Reserved, must be 0
  3703. * 04..00 RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
  3704. */
  3705. write_reg(info, RRC, 0x00);
  3706. /* TRC0 Transmit Ready Control 0
  3707. *
  3708. * 07..05 Reserved, must be 0
  3709. * 04..00 TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
  3710. */
  3711. write_reg(info, TRC0, 0x10);
  3712. /* TRC1 Transmit Ready Control 1
  3713. *
  3714. * 07..05 Reserved, must be 0
  3715. * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
  3716. */
  3717. write_reg(info, TRC1, 0x1e);
  3718. /* CTL, MSCI control register
  3719. *
  3720. * 07..06 Reserved, set to 0
  3721. * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
  3722. * 04 IDLC, idle control, 0=mark 1=idle register
  3723. * 03 BRK, break, 0=off 1 =on (async)
  3724. * 02 SYNCLD, sync char load enable (BSC) 1=enabled
  3725. * 01 GOP, go active on poll (LOOP mode) 1=enabled
  3726. * 00 RTS, RTS output control, 0=active 1=inactive
  3727. *
  3728. * 0001 0001
  3729. */
  3730. RegValue = 0x10;
  3731. if (!(info->serial_signals & SerialSignal_RTS))
  3732. RegValue |= 0x01;
  3733. write_reg(info, CTL, RegValue);
  3734. /* enable status interrupts */
  3735. info->ie0_value |= TXINTE + RXINTE;
  3736. write_reg(info, IE0, info->ie0_value);
  3737. /* enable break detect interrupt */
  3738. info->ie1_value = BRKD;
  3739. write_reg(info, IE1, info->ie1_value);
  3740. /* enable rx overrun interrupt */
  3741. info->ie2_value = OVRN;
  3742. write_reg(info, IE2, info->ie2_value);
  3743. set_rate( info, info->params.data_rate * 16 );
  3744. }
  3745. /* Program the SCA for HDLC communications.
  3746. */
  3747. static void hdlc_mode(SLMP_INFO *info)
  3748. {
  3749. unsigned char RegValue;
  3750. u32 DpllDivisor;
  3751. // Can't use DPLL because SCA outputs recovered clock on RxC when
  3752. // DPLL mode selected. This causes output contention with RxC receiver.
  3753. // Use of DPLL would require external hardware to disable RxC receiver
  3754. // when DPLL mode selected.
  3755. info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
  3756. /* disable DMA interrupts */
  3757. write_reg(info, TXDMA + DIR, 0);
  3758. write_reg(info, RXDMA + DIR, 0);
  3759. /* MD0, Mode Register 0
  3760. *
  3761. * 07..05 PRCTL<2..0>, Protocol Mode, 100=HDLC
  3762. * 04 AUTO, Auto-enable (RTS/CTS/DCD)
  3763. * 03 Reserved, must be 0
  3764. * 02 CRCCC, CRC Calculation, 1=enabled
  3765. * 01 CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
  3766. * 00 CRC0, CRC initial value, 1 = all 1s
  3767. *
  3768. * 1000 0001
  3769. */
  3770. RegValue = 0x81;
  3771. if (info->params.flags & HDLC_FLAG_AUTO_CTS)
  3772. RegValue |= BIT4;
  3773. if (info->params.flags & HDLC_FLAG_AUTO_DCD)
  3774. RegValue |= BIT4;
  3775. if (info->params.crc_type == HDLC_CRC_16_CCITT)
  3776. RegValue |= BIT2 + BIT1;
  3777. write_reg(info, MD0, RegValue);
  3778. /* MD1, Mode Register 1
  3779. *
  3780. * 07..06 ADDRS<1..0>, Address detect, 00=no addr check
  3781. * 05..04 TXCHR<1..0>, tx char size, 00=8 bits
  3782. * 03..02 RXCHR<1..0>, rx char size, 00=8 bits
  3783. * 01..00 PMPM<1..0>, Parity mode, 00=no parity
  3784. *
  3785. * 0000 0000
  3786. */
  3787. RegValue = 0x00;
  3788. write_reg(info, MD1, RegValue);
  3789. /* MD2, Mode Register 2
  3790. *
  3791. * 07 NRZFM, 0=NRZ, 1=FM
  3792. * 06..05 CODE<1..0> Encoding, 00=NRZ
  3793. * 04..03 DRATE<1..0> DPLL Divisor, 00=8
  3794. * 02 Reserved, must be 0
  3795. * 01..00 CNCT<1..0> Channel connection, 0=normal
  3796. *
  3797. * 0000 0000
  3798. */
  3799. RegValue = 0x00;
  3800. switch(info->params.encoding) {
  3801. case HDLC_ENCODING_NRZI: RegValue |= BIT5; break;
  3802. case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT7 + BIT5; break; /* aka FM1 */
  3803. case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
  3804. case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break; /* aka Manchester */
  3805. #if 0
  3806. case HDLC_ENCODING_NRZB: /* not supported */
  3807. case HDLC_ENCODING_NRZI_MARK: /* not supported */
  3808. case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: /* not supported */
  3809. #endif
  3810. }
  3811. if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
  3812. DpllDivisor = 16;
  3813. RegValue |= BIT3;
  3814. } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
  3815. DpllDivisor = 8;
  3816. } else {
  3817. DpllDivisor = 32;
  3818. RegValue |= BIT4;
  3819. }
  3820. write_reg(info, MD2, RegValue);
  3821. /* RXS, Receive clock source
  3822. *
  3823. * 07 Reserved, must be 0
  3824. * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
  3825. * 03..00 RXBR<3..0>, rate divisor, 0000=1
  3826. */
  3827. RegValue=0;
  3828. if (info->params.flags & HDLC_FLAG_RXC_BRG)
  3829. RegValue |= BIT6;
  3830. if (info->params.flags & HDLC_FLAG_RXC_DPLL)
  3831. RegValue |= BIT6 + BIT5;
  3832. write_reg(info, RXS, RegValue);
  3833. /* TXS, Transmit clock source
  3834. *
  3835. * 07 Reserved, must be 0
  3836. * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
  3837. * 03..00 RXBR<3..0>, rate divisor, 0000=1
  3838. */
  3839. RegValue=0;
  3840. if (info->params.flags & HDLC_FLAG_TXC_BRG)
  3841. RegValue |= BIT6;
  3842. if (info->params.flags & HDLC_FLAG_TXC_DPLL)
  3843. RegValue |= BIT6 + BIT5;
  3844. write_reg(info, TXS, RegValue);
  3845. if (info->params.flags & HDLC_FLAG_RXC_DPLL)
  3846. set_rate(info, info->params.clock_speed * DpllDivisor);
  3847. else
  3848. set_rate(info, info->params.clock_speed);
  3849. /* GPDATA (General Purpose I/O Data Register)
  3850. *
  3851. * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
  3852. */
  3853. if (info->params.flags & HDLC_FLAG_TXC_BRG)
  3854. info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
  3855. else
  3856. info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
  3857. write_control_reg(info);
  3858. /* RRC Receive Ready Control 0
  3859. *
  3860. * 07..05 Reserved, must be 0
  3861. * 04..00 RRC<4..0> Rx FIFO trigger active
  3862. */
  3863. write_reg(info, RRC, rx_active_fifo_level);
  3864. /* TRC0 Transmit Ready Control 0
  3865. *
  3866. * 07..05 Reserved, must be 0
  3867. * 04..00 TRC<4..0> Tx FIFO trigger active
  3868. */
  3869. write_reg(info, TRC0, tx_active_fifo_level);
  3870. /* TRC1 Transmit Ready Control 1
  3871. *
  3872. * 07..05 Reserved, must be 0
  3873. * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
  3874. */
  3875. write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
  3876. /* DMR, DMA Mode Register
  3877. *
  3878. * 07..05 Reserved, must be 0
  3879. * 04 TMOD, Transfer Mode: 1=chained-block
  3880. * 03 Reserved, must be 0
  3881. * 02 NF, Number of Frames: 1=multi-frame
  3882. * 01 CNTE, Frame End IRQ Counter enable: 0=disabled
  3883. * 00 Reserved, must be 0
  3884. *
  3885. * 0001 0100
  3886. */
  3887. write_reg(info, TXDMA + DMR, 0x14);
  3888. write_reg(info, RXDMA + DMR, 0x14);
  3889. /* Set chain pointer base (upper 8 bits of 24 bit addr) */
  3890. write_reg(info, RXDMA + CPB,
  3891. (unsigned char)(info->buffer_list_phys >> 16));
  3892. /* Set chain pointer base (upper 8 bits of 24 bit addr) */
  3893. write_reg(info, TXDMA + CPB,
  3894. (unsigned char)(info->buffer_list_phys >> 16));
  3895. /* enable status interrupts. other code enables/disables
  3896. * the individual sources for these two interrupt classes.
  3897. */
  3898. info->ie0_value |= TXINTE + RXINTE;
  3899. write_reg(info, IE0, info->ie0_value);
  3900. /* CTL, MSCI control register
  3901. *
  3902. * 07..06 Reserved, set to 0
  3903. * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
  3904. * 04 IDLC, idle control, 0=mark 1=idle register
  3905. * 03 BRK, break, 0=off 1 =on (async)
  3906. * 02 SYNCLD, sync char load enable (BSC) 1=enabled
  3907. * 01 GOP, go active on poll (LOOP mode) 1=enabled
  3908. * 00 RTS, RTS output control, 0=active 1=inactive
  3909. *
  3910. * 0001 0001
  3911. */
  3912. RegValue = 0x10;
  3913. if (!(info->serial_signals & SerialSignal_RTS))
  3914. RegValue |= 0x01;
  3915. write_reg(info, CTL, RegValue);
  3916. /* preamble not supported ! */
  3917. tx_set_idle(info);
  3918. tx_stop(info);
  3919. rx_stop(info);
  3920. set_rate(info, info->params.clock_speed);
  3921. if (info->params.loopback)
  3922. enable_loopback(info,1);
  3923. }
  3924. /* Set the transmit HDLC idle mode
  3925. */
  3926. static void tx_set_idle(SLMP_INFO *info)
  3927. {
  3928. unsigned char RegValue = 0xff;
  3929. /* Map API idle mode to SCA register bits */
  3930. switch(info->idle_mode) {
  3931. case HDLC_TXIDLE_FLAGS: RegValue = 0x7e; break;
  3932. case HDLC_TXIDLE_ALT_ZEROS_ONES: RegValue = 0xaa; break;
  3933. case HDLC_TXIDLE_ZEROS: RegValue = 0x00; break;
  3934. case HDLC_TXIDLE_ONES: RegValue = 0xff; break;
  3935. case HDLC_TXIDLE_ALT_MARK_SPACE: RegValue = 0xaa; break;
  3936. case HDLC_TXIDLE_SPACE: RegValue = 0x00; break;
  3937. case HDLC_TXIDLE_MARK: RegValue = 0xff; break;
  3938. }
  3939. write_reg(info, IDL, RegValue);
  3940. }
  3941. /* Query the adapter for the state of the V24 status (input) signals.
  3942. */
  3943. static void get_signals(SLMP_INFO *info)
  3944. {
  3945. u16 status = read_reg(info, SR3);
  3946. u16 gpstatus = read_status_reg(info);
  3947. u16 testbit;
  3948. /* clear all serial signals except RTS and DTR */
  3949. info->serial_signals &= SerialSignal_RTS | SerialSignal_DTR;
  3950. /* set serial signal bits to reflect MISR */
  3951. if (!(status & BIT3))
  3952. info->serial_signals |= SerialSignal_CTS;
  3953. if ( !(status & BIT2))
  3954. info->serial_signals |= SerialSignal_DCD;
  3955. testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
  3956. if (!(gpstatus & testbit))
  3957. info->serial_signals |= SerialSignal_RI;
  3958. testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
  3959. if (!(gpstatus & testbit))
  3960. info->serial_signals |= SerialSignal_DSR;
  3961. }
  3962. /* Set the state of RTS and DTR based on contents of
  3963. * serial_signals member of device context.
  3964. */
  3965. static void set_signals(SLMP_INFO *info)
  3966. {
  3967. unsigned char RegValue;
  3968. u16 EnableBit;
  3969. RegValue = read_reg(info, CTL);
  3970. if (info->serial_signals & SerialSignal_RTS)
  3971. RegValue &= ~BIT0;
  3972. else
  3973. RegValue |= BIT0;
  3974. write_reg(info, CTL, RegValue);
  3975. // Port 0..3 DTR is ctrl reg <1,3,5,7>
  3976. EnableBit = BIT1 << (info->port_num*2);
  3977. if (info->serial_signals & SerialSignal_DTR)
  3978. info->port_array[0]->ctrlreg_value &= ~EnableBit;
  3979. else
  3980. info->port_array[0]->ctrlreg_value |= EnableBit;
  3981. write_control_reg(info);
  3982. }
  3983. /*******************/
  3984. /* DMA Buffer Code */
  3985. /*******************/
  3986. /* Set the count for all receive buffers to SCABUFSIZE
  3987. * and set the current buffer to the first buffer. This effectively
  3988. * makes all buffers free and discards any data in buffers.
  3989. */
  3990. static void rx_reset_buffers(SLMP_INFO *info)
  3991. {
  3992. rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
  3993. }
  3994. /* Free the buffers used by a received frame
  3995. *
  3996. * info pointer to device instance data
  3997. * first index of 1st receive buffer of frame
  3998. * last index of last receive buffer of frame
  3999. */
  4000. static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
  4001. {
  4002. bool done = false;
  4003. while(!done) {
  4004. /* reset current buffer for reuse */
  4005. info->rx_buf_list[first].status = 0xff;
  4006. if (first == last) {
  4007. done = true;
  4008. /* set new last rx descriptor address */
  4009. write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
  4010. }
  4011. first++;
  4012. if (first == info->rx_buf_count)
  4013. first = 0;
  4014. }
  4015. /* set current buffer to next buffer after last buffer of frame */
  4016. info->current_rx_buf = first;
  4017. }
  4018. /* Return a received frame from the receive DMA buffers.
  4019. * Only frames received without errors are returned.
  4020. *
  4021. * Return Value: true if frame returned, otherwise false
  4022. */
  4023. static bool rx_get_frame(SLMP_INFO *info)
  4024. {
  4025. unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
  4026. unsigned short status;
  4027. unsigned int framesize = 0;
  4028. bool ReturnCode = false;
  4029. unsigned long flags;
  4030. struct tty_struct *tty = info->port.tty;
  4031. unsigned char addr_field = 0xff;
  4032. SCADESC *desc;
  4033. SCADESC_EX *desc_ex;
  4034. CheckAgain:
  4035. /* assume no frame returned, set zero length */
  4036. framesize = 0;
  4037. addr_field = 0xff;
  4038. /*
  4039. * current_rx_buf points to the 1st buffer of the next available
  4040. * receive frame. To find the last buffer of the frame look for
  4041. * a non-zero status field in the buffer entries. (The status
  4042. * field is set by the 16C32 after completing a receive frame.
  4043. */
  4044. StartIndex = EndIndex = info->current_rx_buf;
  4045. for ( ;; ) {
  4046. desc = &info->rx_buf_list[EndIndex];
  4047. desc_ex = &info->rx_buf_list_ex[EndIndex];
  4048. if (desc->status == 0xff)
  4049. goto Cleanup; /* current desc still in use, no frames available */
  4050. if (framesize == 0 && info->params.addr_filter != 0xff)
  4051. addr_field = desc_ex->virt_addr[0];
  4052. framesize += desc->length;
  4053. /* Status != 0 means last buffer of frame */
  4054. if (desc->status)
  4055. break;
  4056. EndIndex++;
  4057. if (EndIndex == info->rx_buf_count)
  4058. EndIndex = 0;
  4059. if (EndIndex == info->current_rx_buf) {
  4060. /* all buffers have been 'used' but none mark */
  4061. /* the end of a frame. Reset buffers and receiver. */
  4062. if ( info->rx_enabled ){
  4063. spin_lock_irqsave(&info->lock,flags);
  4064. rx_start(info);
  4065. spin_unlock_irqrestore(&info->lock,flags);
  4066. }
  4067. goto Cleanup;
  4068. }
  4069. }
  4070. /* check status of receive frame */
  4071. /* frame status is byte stored after frame data
  4072. *
  4073. * 7 EOM (end of msg), 1 = last buffer of frame
  4074. * 6 Short Frame, 1 = short frame
  4075. * 5 Abort, 1 = frame aborted
  4076. * 4 Residue, 1 = last byte is partial
  4077. * 3 Overrun, 1 = overrun occurred during frame reception
  4078. * 2 CRC, 1 = CRC error detected
  4079. *
  4080. */
  4081. status = desc->status;
  4082. /* ignore CRC bit if not using CRC (bit is undefined) */
  4083. /* Note:CRC is not save to data buffer */
  4084. if (info->params.crc_type == HDLC_CRC_NONE)
  4085. status &= ~BIT2;
  4086. if (framesize == 0 ||
  4087. (addr_field != 0xff && addr_field != info->params.addr_filter)) {
  4088. /* discard 0 byte frames, this seems to occur sometime
  4089. * when remote is idling flags.
  4090. */
  4091. rx_free_frame_buffers(info, StartIndex, EndIndex);
  4092. goto CheckAgain;
  4093. }
  4094. if (framesize < 2)
  4095. status |= BIT6;
  4096. if (status & (BIT6+BIT5+BIT3+BIT2)) {
  4097. /* received frame has errors,
  4098. * update counts and mark frame size as 0
  4099. */
  4100. if (status & BIT6)
  4101. info->icount.rxshort++;
  4102. else if (status & BIT5)
  4103. info->icount.rxabort++;
  4104. else if (status & BIT3)
  4105. info->icount.rxover++;
  4106. else
  4107. info->icount.rxcrc++;
  4108. framesize = 0;
  4109. #if SYNCLINK_GENERIC_HDLC
  4110. {
  4111. info->netdev->stats.rx_errors++;
  4112. info->netdev->stats.rx_frame_errors++;
  4113. }
  4114. #endif
  4115. }
  4116. if ( debug_level >= DEBUG_LEVEL_BH )
  4117. printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
  4118. __FILE__,__LINE__,info->device_name,status,framesize);
  4119. if ( debug_level >= DEBUG_LEVEL_DATA )
  4120. trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
  4121. min_t(unsigned int, framesize, SCABUFSIZE), 0);
  4122. if (framesize) {
  4123. if (framesize > info->max_frame_size)
  4124. info->icount.rxlong++;
  4125. else {
  4126. /* copy dma buffer(s) to contiguous intermediate buffer */
  4127. int copy_count = framesize;
  4128. int index = StartIndex;
  4129. unsigned char *ptmp = info->tmp_rx_buf;
  4130. info->tmp_rx_buf_count = framesize;
  4131. info->icount.rxok++;
  4132. while(copy_count) {
  4133. int partial_count = min(copy_count,SCABUFSIZE);
  4134. memcpy( ptmp,
  4135. info->rx_buf_list_ex[index].virt_addr,
  4136. partial_count );
  4137. ptmp += partial_count;
  4138. copy_count -= partial_count;
  4139. if ( ++index == info->rx_buf_count )
  4140. index = 0;
  4141. }
  4142. #if SYNCLINK_GENERIC_HDLC
  4143. if (info->netcount)
  4144. hdlcdev_rx(info,info->tmp_rx_buf,framesize);
  4145. else
  4146. #endif
  4147. ldisc_receive_buf(tty,info->tmp_rx_buf,
  4148. info->flag_buf, framesize);
  4149. }
  4150. }
  4151. /* Free the buffers used by this frame. */
  4152. rx_free_frame_buffers( info, StartIndex, EndIndex );
  4153. ReturnCode = true;
  4154. Cleanup:
  4155. if ( info->rx_enabled && info->rx_overflow ) {
  4156. /* Receiver is enabled, but needs to restarted due to
  4157. * rx buffer overflow. If buffers are empty, restart receiver.
  4158. */
  4159. if (info->rx_buf_list[EndIndex].status == 0xff) {
  4160. spin_lock_irqsave(&info->lock,flags);
  4161. rx_start(info);
  4162. spin_unlock_irqrestore(&info->lock,flags);
  4163. }
  4164. }
  4165. return ReturnCode;
  4166. }
  4167. /* load the transmit DMA buffer with data
  4168. */
  4169. static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
  4170. {
  4171. unsigned short copy_count;
  4172. unsigned int i = 0;
  4173. SCADESC *desc;
  4174. SCADESC_EX *desc_ex;
  4175. if ( debug_level >= DEBUG_LEVEL_DATA )
  4176. trace_block(info, buf, min_t(unsigned int, count, SCABUFSIZE), 1);
  4177. /* Copy source buffer to one or more DMA buffers, starting with
  4178. * the first transmit dma buffer.
  4179. */
  4180. for(i=0;;)
  4181. {
  4182. copy_count = min_t(unsigned int, count, SCABUFSIZE);
  4183. desc = &info->tx_buf_list[i];
  4184. desc_ex = &info->tx_buf_list_ex[i];
  4185. load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
  4186. desc->length = copy_count;
  4187. desc->status = 0;
  4188. buf += copy_count;
  4189. count -= copy_count;
  4190. if (!count)
  4191. break;
  4192. i++;
  4193. if (i >= info->tx_buf_count)
  4194. i = 0;
  4195. }
  4196. info->tx_buf_list[i].status = 0x81; /* set EOM and EOT status */
  4197. info->last_tx_buf = ++i;
  4198. }
  4199. static bool register_test(SLMP_INFO *info)
  4200. {
  4201. static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
  4202. static unsigned int count = ARRAY_SIZE(testval);
  4203. unsigned int i;
  4204. bool rc = true;
  4205. unsigned long flags;
  4206. spin_lock_irqsave(&info->lock,flags);
  4207. reset_port(info);
  4208. /* assume failure */
  4209. info->init_error = DiagStatus_AddressFailure;
  4210. /* Write bit patterns to various registers but do it out of */
  4211. /* sync, then read back and verify values. */
  4212. for (i = 0 ; i < count ; i++) {
  4213. write_reg(info, TMC, testval[i]);
  4214. write_reg(info, IDL, testval[(i+1)%count]);
  4215. write_reg(info, SA0, testval[(i+2)%count]);
  4216. write_reg(info, SA1, testval[(i+3)%count]);
  4217. if ( (read_reg(info, TMC) != testval[i]) ||
  4218. (read_reg(info, IDL) != testval[(i+1)%count]) ||
  4219. (read_reg(info, SA0) != testval[(i+2)%count]) ||
  4220. (read_reg(info, SA1) != testval[(i+3)%count]) )
  4221. {
  4222. rc = false;
  4223. break;
  4224. }
  4225. }
  4226. reset_port(info);
  4227. spin_unlock_irqrestore(&info->lock,flags);
  4228. return rc;
  4229. }
  4230. static bool irq_test(SLMP_INFO *info)
  4231. {
  4232. unsigned long timeout;
  4233. unsigned long flags;
  4234. unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
  4235. spin_lock_irqsave(&info->lock,flags);
  4236. reset_port(info);
  4237. /* assume failure */
  4238. info->init_error = DiagStatus_IrqFailure;
  4239. info->irq_occurred = false;
  4240. /* setup timer0 on SCA0 to interrupt */
  4241. /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
  4242. write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
  4243. write_reg(info, (unsigned char)(timer + TEPR), 0); /* timer expand prescale */
  4244. write_reg16(info, (unsigned char)(timer + TCONR), 1); /* timer constant */
  4245. /* TMCS, Timer Control/Status Register
  4246. *
  4247. * 07 CMF, Compare match flag (read only) 1=match
  4248. * 06 ECMI, CMF Interrupt Enable: 1=enabled
  4249. * 05 Reserved, must be 0
  4250. * 04 TME, Timer Enable
  4251. * 03..00 Reserved, must be 0
  4252. *
  4253. * 0101 0000
  4254. */
  4255. write_reg(info, (unsigned char)(timer + TMCS), 0x50);
  4256. spin_unlock_irqrestore(&info->lock,flags);
  4257. timeout=100;
  4258. while( timeout-- && !info->irq_occurred ) {
  4259. msleep_interruptible(10);
  4260. }
  4261. spin_lock_irqsave(&info->lock,flags);
  4262. reset_port(info);
  4263. spin_unlock_irqrestore(&info->lock,flags);
  4264. return info->irq_occurred;
  4265. }
  4266. /* initialize individual SCA device (2 ports)
  4267. */
  4268. static bool sca_init(SLMP_INFO *info)
  4269. {
  4270. /* set wait controller to single mem partition (low), no wait states */
  4271. write_reg(info, PABR0, 0); /* wait controller addr boundary 0 */
  4272. write_reg(info, PABR1, 0); /* wait controller addr boundary 1 */
  4273. write_reg(info, WCRL, 0); /* wait controller low range */
  4274. write_reg(info, WCRM, 0); /* wait controller mid range */
  4275. write_reg(info, WCRH, 0); /* wait controller high range */
  4276. /* DPCR, DMA Priority Control
  4277. *
  4278. * 07..05 Not used, must be 0
  4279. * 04 BRC, bus release condition: 0=all transfers complete
  4280. * 03 CCC, channel change condition: 0=every cycle
  4281. * 02..00 PR<2..0>, priority 100=round robin
  4282. *
  4283. * 00000100 = 0x04
  4284. */
  4285. write_reg(info, DPCR, dma_priority);
  4286. /* DMA Master Enable, BIT7: 1=enable all channels */
  4287. write_reg(info, DMER, 0x80);
  4288. /* enable all interrupt classes */
  4289. write_reg(info, IER0, 0xff); /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
  4290. write_reg(info, IER1, 0xff); /* DMIB,DMIA (channels 0-3) */
  4291. write_reg(info, IER2, 0xf0); /* TIRQ (timers 0-3) */
  4292. /* ITCR, interrupt control register
  4293. * 07 IPC, interrupt priority, 0=MSCI->DMA
  4294. * 06..05 IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
  4295. * 04 VOS, Vector Output, 0=unmodified vector
  4296. * 03..00 Reserved, must be 0
  4297. */
  4298. write_reg(info, ITCR, 0);
  4299. return true;
  4300. }
  4301. /* initialize adapter hardware
  4302. */
  4303. static bool init_adapter(SLMP_INFO *info)
  4304. {
  4305. int i;
  4306. /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
  4307. volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
  4308. u32 readval;
  4309. info->misc_ctrl_value |= BIT30;
  4310. *MiscCtrl = info->misc_ctrl_value;
  4311. /*
  4312. * Force at least 170ns delay before clearing
  4313. * reset bit. Each read from LCR takes at least
  4314. * 30ns so 10 times for 300ns to be safe.
  4315. */
  4316. for(i=0;i<10;i++)
  4317. readval = *MiscCtrl;
  4318. info->misc_ctrl_value &= ~BIT30;
  4319. *MiscCtrl = info->misc_ctrl_value;
  4320. /* init control reg (all DTRs off, all clksel=input) */
  4321. info->ctrlreg_value = 0xaa;
  4322. write_control_reg(info);
  4323. {
  4324. volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
  4325. lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
  4326. switch(read_ahead_count)
  4327. {
  4328. case 16:
  4329. lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
  4330. break;
  4331. case 8:
  4332. lcr1_brdr_value |= BIT5 + BIT4;
  4333. break;
  4334. case 4:
  4335. lcr1_brdr_value |= BIT5 + BIT3;
  4336. break;
  4337. case 0:
  4338. lcr1_brdr_value |= BIT5;
  4339. break;
  4340. }
  4341. *LCR1BRDR = lcr1_brdr_value;
  4342. *MiscCtrl = misc_ctrl_value;
  4343. }
  4344. sca_init(info->port_array[0]);
  4345. sca_init(info->port_array[2]);
  4346. return true;
  4347. }
  4348. /* Loopback an HDLC frame to test the hardware
  4349. * interrupt and DMA functions.
  4350. */
  4351. static bool loopback_test(SLMP_INFO *info)
  4352. {
  4353. #define TESTFRAMESIZE 20
  4354. unsigned long timeout;
  4355. u16 count = TESTFRAMESIZE;
  4356. unsigned char buf[TESTFRAMESIZE];
  4357. bool rc = false;
  4358. unsigned long flags;
  4359. struct tty_struct *oldtty = info->port.tty;
  4360. u32 speed = info->params.clock_speed;
  4361. info->params.clock_speed = 3686400;
  4362. info->port.tty = NULL;
  4363. /* assume failure */
  4364. info->init_error = DiagStatus_DmaFailure;
  4365. /* build and send transmit frame */
  4366. for (count = 0; count < TESTFRAMESIZE;++count)
  4367. buf[count] = (unsigned char)count;
  4368. memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
  4369. /* program hardware for HDLC and enabled receiver */
  4370. spin_lock_irqsave(&info->lock,flags);
  4371. hdlc_mode(info);
  4372. enable_loopback(info,1);
  4373. rx_start(info);
  4374. info->tx_count = count;
  4375. tx_load_dma_buffer(info,buf,count);
  4376. tx_start(info);
  4377. spin_unlock_irqrestore(&info->lock,flags);
  4378. /* wait for receive complete */
  4379. /* Set a timeout for waiting for interrupt. */
  4380. for ( timeout = 100; timeout; --timeout ) {
  4381. msleep_interruptible(10);
  4382. if (rx_get_frame(info)) {
  4383. rc = true;
  4384. break;
  4385. }
  4386. }
  4387. /* verify received frame length and contents */
  4388. if (rc &&
  4389. ( info->tmp_rx_buf_count != count ||
  4390. memcmp(buf, info->tmp_rx_buf,count))) {
  4391. rc = false;
  4392. }
  4393. spin_lock_irqsave(&info->lock,flags);
  4394. reset_adapter(info);
  4395. spin_unlock_irqrestore(&info->lock,flags);
  4396. info->params.clock_speed = speed;
  4397. info->port.tty = oldtty;
  4398. return rc;
  4399. }
  4400. /* Perform diagnostics on hardware
  4401. */
  4402. static int adapter_test( SLMP_INFO *info )
  4403. {
  4404. unsigned long flags;
  4405. if ( debug_level >= DEBUG_LEVEL_INFO )
  4406. printk( "%s(%d):Testing device %s\n",
  4407. __FILE__,__LINE__,info->device_name );
  4408. spin_lock_irqsave(&info->lock,flags);
  4409. init_adapter(info);
  4410. spin_unlock_irqrestore(&info->lock,flags);
  4411. info->port_array[0]->port_count = 0;
  4412. if ( register_test(info->port_array[0]) &&
  4413. register_test(info->port_array[1])) {
  4414. info->port_array[0]->port_count = 2;
  4415. if ( register_test(info->port_array[2]) &&
  4416. register_test(info->port_array[3]) )
  4417. info->port_array[0]->port_count += 2;
  4418. }
  4419. else {
  4420. printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
  4421. __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
  4422. return -ENODEV;
  4423. }
  4424. if ( !irq_test(info->port_array[0]) ||
  4425. !irq_test(info->port_array[1]) ||
  4426. (info->port_count == 4 && !irq_test(info->port_array[2])) ||
  4427. (info->port_count == 4 && !irq_test(info->port_array[3]))) {
  4428. printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
  4429. __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
  4430. return -ENODEV;
  4431. }
  4432. if (!loopback_test(info->port_array[0]) ||
  4433. !loopback_test(info->port_array[1]) ||
  4434. (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
  4435. (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
  4436. printk( "%s(%d):DMA test failure for device %s\n",
  4437. __FILE__,__LINE__,info->device_name);
  4438. return -ENODEV;
  4439. }
  4440. if ( debug_level >= DEBUG_LEVEL_INFO )
  4441. printk( "%s(%d):device %s passed diagnostics\n",
  4442. __FILE__,__LINE__,info->device_name );
  4443. info->port_array[0]->init_error = 0;
  4444. info->port_array[1]->init_error = 0;
  4445. if ( info->port_count > 2 ) {
  4446. info->port_array[2]->init_error = 0;
  4447. info->port_array[3]->init_error = 0;
  4448. }
  4449. return 0;
  4450. }
  4451. /* Test the shared memory on a PCI adapter.
  4452. */
  4453. static bool memory_test(SLMP_INFO *info)
  4454. {
  4455. static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
  4456. 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
  4457. unsigned long count = ARRAY_SIZE(testval);
  4458. unsigned long i;
  4459. unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
  4460. unsigned long * addr = (unsigned long *)info->memory_base;
  4461. /* Test data lines with test pattern at one location. */
  4462. for ( i = 0 ; i < count ; i++ ) {
  4463. *addr = testval[i];
  4464. if ( *addr != testval[i] )
  4465. return false;
  4466. }
  4467. /* Test address lines with incrementing pattern over */
  4468. /* entire address range. */
  4469. for ( i = 0 ; i < limit ; i++ ) {
  4470. *addr = i * 4;
  4471. addr++;
  4472. }
  4473. addr = (unsigned long *)info->memory_base;
  4474. for ( i = 0 ; i < limit ; i++ ) {
  4475. if ( *addr != i * 4 )
  4476. return false;
  4477. addr++;
  4478. }
  4479. memset( info->memory_base, 0, SCA_MEM_SIZE );
  4480. return true;
  4481. }
  4482. /* Load data into PCI adapter shared memory.
  4483. *
  4484. * The PCI9050 releases control of the local bus
  4485. * after completing the current read or write operation.
  4486. *
  4487. * While the PCI9050 write FIFO not empty, the
  4488. * PCI9050 treats all of the writes as a single transaction
  4489. * and does not release the bus. This causes DMA latency problems
  4490. * at high speeds when copying large data blocks to the shared memory.
  4491. *
  4492. * This function breaks a write into multiple transations by
  4493. * interleaving a read which flushes the write FIFO and 'completes'
  4494. * the write transation. This allows any pending DMA request to gain control
  4495. * of the local bus in a timely fasion.
  4496. */
  4497. static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
  4498. {
  4499. /* A load interval of 16 allows for 4 32-bit writes at */
  4500. /* 136ns each for a maximum latency of 542ns on the local bus.*/
  4501. unsigned short interval = count / sca_pci_load_interval;
  4502. unsigned short i;
  4503. for ( i = 0 ; i < interval ; i++ )
  4504. {
  4505. memcpy(dest, src, sca_pci_load_interval);
  4506. read_status_reg(info);
  4507. dest += sca_pci_load_interval;
  4508. src += sca_pci_load_interval;
  4509. }
  4510. memcpy(dest, src, count % sca_pci_load_interval);
  4511. }
  4512. static void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
  4513. {
  4514. int i;
  4515. int linecount;
  4516. if (xmit)
  4517. printk("%s tx data:\n",info->device_name);
  4518. else
  4519. printk("%s rx data:\n",info->device_name);
  4520. while(count) {
  4521. if (count > 16)
  4522. linecount = 16;
  4523. else
  4524. linecount = count;
  4525. for(i=0;i<linecount;i++)
  4526. printk("%02X ",(unsigned char)data[i]);
  4527. for(;i<17;i++)
  4528. printk(" ");
  4529. for(i=0;i<linecount;i++) {
  4530. if (data[i]>=040 && data[i]<=0176)
  4531. printk("%c",data[i]);
  4532. else
  4533. printk(".");
  4534. }
  4535. printk("\n");
  4536. data += linecount;
  4537. count -= linecount;
  4538. }
  4539. } /* end of trace_block() */
  4540. /* called when HDLC frame times out
  4541. * update stats and do tx completion processing
  4542. */
  4543. static void tx_timeout(struct timer_list *t)
  4544. {
  4545. SLMP_INFO *info = from_timer(info, t, tx_timer);
  4546. unsigned long flags;
  4547. if ( debug_level >= DEBUG_LEVEL_INFO )
  4548. printk( "%s(%d):%s tx_timeout()\n",
  4549. __FILE__,__LINE__,info->device_name);
  4550. if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
  4551. info->icount.txtimeout++;
  4552. }
  4553. spin_lock_irqsave(&info->lock,flags);
  4554. info->tx_active = false;
  4555. info->tx_count = info->tx_put = info->tx_get = 0;
  4556. spin_unlock_irqrestore(&info->lock,flags);
  4557. #if SYNCLINK_GENERIC_HDLC
  4558. if (info->netcount)
  4559. hdlcdev_tx_done(info);
  4560. else
  4561. #endif
  4562. bh_transmit(info);
  4563. }
  4564. /* called to periodically check the DSR/RI modem signal input status
  4565. */
  4566. static void status_timeout(struct timer_list *t)
  4567. {
  4568. u16 status = 0;
  4569. SLMP_INFO *info = from_timer(info, t, status_timer);
  4570. unsigned long flags;
  4571. unsigned char delta;
  4572. spin_lock_irqsave(&info->lock,flags);
  4573. get_signals(info);
  4574. spin_unlock_irqrestore(&info->lock,flags);
  4575. /* check for DSR/RI state change */
  4576. delta = info->old_signals ^ info->serial_signals;
  4577. info->old_signals = info->serial_signals;
  4578. if (delta & SerialSignal_DSR)
  4579. status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
  4580. if (delta & SerialSignal_RI)
  4581. status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
  4582. if (delta & SerialSignal_DCD)
  4583. status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
  4584. if (delta & SerialSignal_CTS)
  4585. status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
  4586. if (status)
  4587. isr_io_pin(info,status);
  4588. mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
  4589. }
  4590. /* Register Access Routines -
  4591. * All registers are memory mapped
  4592. */
  4593. #define CALC_REGADDR() \
  4594. unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
  4595. if (info->port_num > 1) \
  4596. RegAddr += 256; /* port 0-1 SCA0, 2-3 SCA1 */ \
  4597. if ( info->port_num & 1) { \
  4598. if (Addr > 0x7f) \
  4599. RegAddr += 0x40; /* DMA access */ \
  4600. else if (Addr > 0x1f && Addr < 0x60) \
  4601. RegAddr += 0x20; /* MSCI access */ \
  4602. }
  4603. static unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
  4604. {
  4605. CALC_REGADDR();
  4606. return *RegAddr;
  4607. }
  4608. static void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
  4609. {
  4610. CALC_REGADDR();
  4611. *RegAddr = Value;
  4612. }
  4613. static u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
  4614. {
  4615. CALC_REGADDR();
  4616. return *((u16 *)RegAddr);
  4617. }
  4618. static void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
  4619. {
  4620. CALC_REGADDR();
  4621. *((u16 *)RegAddr) = Value;
  4622. }
  4623. static unsigned char read_status_reg(SLMP_INFO * info)
  4624. {
  4625. unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
  4626. return *RegAddr;
  4627. }
  4628. static void write_control_reg(SLMP_INFO * info)
  4629. {
  4630. unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
  4631. *RegAddr = info->port_array[0]->ctrlreg_value;
  4632. }
  4633. static int synclinkmp_init_one (struct pci_dev *dev,
  4634. const struct pci_device_id *ent)
  4635. {
  4636. if (pci_enable_device(dev)) {
  4637. printk("error enabling pci device %p\n", dev);
  4638. return -EIO;
  4639. }
  4640. return device_init( ++synclinkmp_adapter_count, dev );
  4641. }
  4642. static void synclinkmp_remove_one (struct pci_dev *dev)
  4643. {
  4644. }