synclink_gt.c 128 KB

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  1. // SPDX-License-Identifier: GPL-1.0+
  2. /*
  3. * Device driver for Microgate SyncLink GT serial adapters.
  4. *
  5. * written by Paul Fulghum for Microgate Corporation
  6. * paulkf@microgate.com
  7. *
  8. * Microgate and SyncLink are trademarks of Microgate Corporation
  9. *
  10. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  11. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  12. * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  13. * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  14. * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  15. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  16. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  17. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  18. * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  19. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  20. * OF THE POSSIBILITY OF SUCH DAMAGE.
  21. */
  22. /*
  23. * DEBUG OUTPUT DEFINITIONS
  24. *
  25. * uncomment lines below to enable specific types of debug output
  26. *
  27. * DBGINFO information - most verbose output
  28. * DBGERR serious errors
  29. * DBGBH bottom half service routine debugging
  30. * DBGISR interrupt service routine debugging
  31. * DBGDATA output receive and transmit data
  32. * DBGTBUF output transmit DMA buffers and registers
  33. * DBGRBUF output receive DMA buffers and registers
  34. */
  35. #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
  36. #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
  37. #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
  38. #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
  39. #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
  40. /*#define DBGTBUF(info) dump_tbufs(info)*/
  41. /*#define DBGRBUF(info) dump_rbufs(info)*/
  42. #include <linux/module.h>
  43. #include <linux/errno.h>
  44. #include <linux/signal.h>
  45. #include <linux/sched.h>
  46. #include <linux/timer.h>
  47. #include <linux/interrupt.h>
  48. #include <linux/pci.h>
  49. #include <linux/tty.h>
  50. #include <linux/tty_flip.h>
  51. #include <linux/serial.h>
  52. #include <linux/major.h>
  53. #include <linux/string.h>
  54. #include <linux/fcntl.h>
  55. #include <linux/ptrace.h>
  56. #include <linux/ioport.h>
  57. #include <linux/mm.h>
  58. #include <linux/seq_file.h>
  59. #include <linux/slab.h>
  60. #include <linux/netdevice.h>
  61. #include <linux/vmalloc.h>
  62. #include <linux/init.h>
  63. #include <linux/delay.h>
  64. #include <linux/ioctl.h>
  65. #include <linux/termios.h>
  66. #include <linux/bitops.h>
  67. #include <linux/workqueue.h>
  68. #include <linux/hdlc.h>
  69. #include <linux/synclink.h>
  70. #include <asm/io.h>
  71. #include <asm/irq.h>
  72. #include <asm/dma.h>
  73. #include <asm/types.h>
  74. #include <linux/uaccess.h>
  75. #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
  76. #define SYNCLINK_GENERIC_HDLC 1
  77. #else
  78. #define SYNCLINK_GENERIC_HDLC 0
  79. #endif
  80. /*
  81. * module identification
  82. */
  83. static char *driver_name = "SyncLink GT";
  84. static char *slgt_driver_name = "synclink_gt";
  85. static char *tty_dev_prefix = "ttySLG";
  86. MODULE_LICENSE("GPL");
  87. #define MGSL_MAGIC 0x5401
  88. #define MAX_DEVICES 32
  89. static const struct pci_device_id pci_table[] = {
  90. {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
  91. {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
  92. {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
  93. {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
  94. {0,}, /* terminate list */
  95. };
  96. MODULE_DEVICE_TABLE(pci, pci_table);
  97. static int init_one(struct pci_dev *dev,const struct pci_device_id *ent);
  98. static void remove_one(struct pci_dev *dev);
  99. static struct pci_driver pci_driver = {
  100. .name = "synclink_gt",
  101. .id_table = pci_table,
  102. .probe = init_one,
  103. .remove = remove_one,
  104. };
  105. static bool pci_registered;
  106. /*
  107. * module configuration and status
  108. */
  109. static struct slgt_info *slgt_device_list;
  110. static int slgt_device_count;
  111. static int ttymajor;
  112. static int debug_level;
  113. static int maxframe[MAX_DEVICES];
  114. module_param(ttymajor, int, 0);
  115. module_param(debug_level, int, 0);
  116. module_param_array(maxframe, int, NULL, 0);
  117. MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
  118. MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
  119. MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
  120. /*
  121. * tty support and callbacks
  122. */
  123. static struct tty_driver *serial_driver;
  124. static void wait_until_sent(struct tty_struct *tty, int timeout);
  125. static void flush_buffer(struct tty_struct *tty);
  126. static void tx_release(struct tty_struct *tty);
  127. /*
  128. * generic HDLC support
  129. */
  130. #define dev_to_port(D) (dev_to_hdlc(D)->priv)
  131. /*
  132. * device specific structures, macros and functions
  133. */
  134. #define SLGT_MAX_PORTS 4
  135. #define SLGT_REG_SIZE 256
  136. /*
  137. * conditional wait facility
  138. */
  139. struct cond_wait {
  140. struct cond_wait *next;
  141. wait_queue_head_t q;
  142. wait_queue_entry_t wait;
  143. unsigned int data;
  144. };
  145. static void flush_cond_wait(struct cond_wait **head);
  146. /*
  147. * DMA buffer descriptor and access macros
  148. */
  149. struct slgt_desc
  150. {
  151. __le16 count;
  152. __le16 status;
  153. __le32 pbuf; /* physical address of data buffer */
  154. __le32 next; /* physical address of next descriptor */
  155. /* driver book keeping */
  156. char *buf; /* virtual address of data buffer */
  157. unsigned int pdesc; /* physical address of this descriptor */
  158. dma_addr_t buf_dma_addr;
  159. unsigned short buf_count;
  160. };
  161. #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
  162. #define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
  163. #define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
  164. #define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
  165. #define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
  166. #define desc_count(a) (le16_to_cpu((a).count))
  167. #define desc_status(a) (le16_to_cpu((a).status))
  168. #define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
  169. #define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
  170. #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
  171. #define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
  172. #define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
  173. struct _input_signal_events {
  174. int ri_up;
  175. int ri_down;
  176. int dsr_up;
  177. int dsr_down;
  178. int dcd_up;
  179. int dcd_down;
  180. int cts_up;
  181. int cts_down;
  182. };
  183. /*
  184. * device instance data structure
  185. */
  186. struct slgt_info {
  187. void *if_ptr; /* General purpose pointer (used by SPPP) */
  188. struct tty_port port;
  189. struct slgt_info *next_device; /* device list link */
  190. int magic;
  191. char device_name[25];
  192. struct pci_dev *pdev;
  193. int port_count; /* count of ports on adapter */
  194. int adapter_num; /* adapter instance number */
  195. int port_num; /* port instance number */
  196. /* array of pointers to port contexts on this adapter */
  197. struct slgt_info *port_array[SLGT_MAX_PORTS];
  198. int line; /* tty line instance number */
  199. struct mgsl_icount icount;
  200. int timeout;
  201. int x_char; /* xon/xoff character */
  202. unsigned int read_status_mask;
  203. unsigned int ignore_status_mask;
  204. wait_queue_head_t status_event_wait_q;
  205. wait_queue_head_t event_wait_q;
  206. struct timer_list tx_timer;
  207. struct timer_list rx_timer;
  208. unsigned int gpio_present;
  209. struct cond_wait *gpio_wait_q;
  210. spinlock_t lock; /* spinlock for synchronizing with ISR */
  211. struct work_struct task;
  212. u32 pending_bh;
  213. bool bh_requested;
  214. bool bh_running;
  215. int isr_overflow;
  216. bool irq_requested; /* true if IRQ requested */
  217. bool irq_occurred; /* for diagnostics use */
  218. /* device configuration */
  219. unsigned int bus_type;
  220. unsigned int irq_level;
  221. unsigned long irq_flags;
  222. unsigned char __iomem * reg_addr; /* memory mapped registers address */
  223. u32 phys_reg_addr;
  224. bool reg_addr_requested;
  225. MGSL_PARAMS params; /* communications parameters */
  226. u32 idle_mode;
  227. u32 max_frame_size; /* as set by device config */
  228. unsigned int rbuf_fill_level;
  229. unsigned int rx_pio;
  230. unsigned int if_mode;
  231. unsigned int base_clock;
  232. unsigned int xsync;
  233. unsigned int xctrl;
  234. /* device status */
  235. bool rx_enabled;
  236. bool rx_restart;
  237. bool tx_enabled;
  238. bool tx_active;
  239. unsigned char signals; /* serial signal states */
  240. int init_error; /* initialization error */
  241. unsigned char *tx_buf;
  242. int tx_count;
  243. char *flag_buf;
  244. bool drop_rts_on_tx_done;
  245. struct _input_signal_events input_signal_events;
  246. int dcd_chkcount; /* check counts to prevent */
  247. int cts_chkcount; /* too many IRQs if a signal */
  248. int dsr_chkcount; /* is floating */
  249. int ri_chkcount;
  250. char *bufs; /* virtual address of DMA buffer lists */
  251. dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
  252. unsigned int rbuf_count;
  253. struct slgt_desc *rbufs;
  254. unsigned int rbuf_current;
  255. unsigned int rbuf_index;
  256. unsigned int rbuf_fill_index;
  257. unsigned short rbuf_fill_count;
  258. unsigned int tbuf_count;
  259. struct slgt_desc *tbufs;
  260. unsigned int tbuf_current;
  261. unsigned int tbuf_start;
  262. unsigned char *tmp_rbuf;
  263. unsigned int tmp_rbuf_count;
  264. /* SPPP/Cisco HDLC device parts */
  265. int netcount;
  266. spinlock_t netlock;
  267. #if SYNCLINK_GENERIC_HDLC
  268. struct net_device *netdev;
  269. #endif
  270. };
  271. static MGSL_PARAMS default_params = {
  272. .mode = MGSL_MODE_HDLC,
  273. .loopback = 0,
  274. .flags = HDLC_FLAG_UNDERRUN_ABORT15,
  275. .encoding = HDLC_ENCODING_NRZI_SPACE,
  276. .clock_speed = 0,
  277. .addr_filter = 0xff,
  278. .crc_type = HDLC_CRC_16_CCITT,
  279. .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
  280. .preamble = HDLC_PREAMBLE_PATTERN_NONE,
  281. .data_rate = 9600,
  282. .data_bits = 8,
  283. .stop_bits = 1,
  284. .parity = ASYNC_PARITY_NONE
  285. };
  286. #define BH_RECEIVE 1
  287. #define BH_TRANSMIT 2
  288. #define BH_STATUS 4
  289. #define IO_PIN_SHUTDOWN_LIMIT 100
  290. #define DMABUFSIZE 256
  291. #define DESC_LIST_SIZE 4096
  292. #define MASK_PARITY BIT1
  293. #define MASK_FRAMING BIT0
  294. #define MASK_BREAK BIT14
  295. #define MASK_OVERRUN BIT4
  296. #define GSR 0x00 /* global status */
  297. #define JCR 0x04 /* JTAG control */
  298. #define IODR 0x08 /* GPIO direction */
  299. #define IOER 0x0c /* GPIO interrupt enable */
  300. #define IOVR 0x10 /* GPIO value */
  301. #define IOSR 0x14 /* GPIO interrupt status */
  302. #define TDR 0x80 /* tx data */
  303. #define RDR 0x80 /* rx data */
  304. #define TCR 0x82 /* tx control */
  305. #define TIR 0x84 /* tx idle */
  306. #define TPR 0x85 /* tx preamble */
  307. #define RCR 0x86 /* rx control */
  308. #define VCR 0x88 /* V.24 control */
  309. #define CCR 0x89 /* clock control */
  310. #define BDR 0x8a /* baud divisor */
  311. #define SCR 0x8c /* serial control */
  312. #define SSR 0x8e /* serial status */
  313. #define RDCSR 0x90 /* rx DMA control/status */
  314. #define TDCSR 0x94 /* tx DMA control/status */
  315. #define RDDAR 0x98 /* rx DMA descriptor address */
  316. #define TDDAR 0x9c /* tx DMA descriptor address */
  317. #define XSR 0x40 /* extended sync pattern */
  318. #define XCR 0x44 /* extended control */
  319. #define RXIDLE BIT14
  320. #define RXBREAK BIT14
  321. #define IRQ_TXDATA BIT13
  322. #define IRQ_TXIDLE BIT12
  323. #define IRQ_TXUNDER BIT11 /* HDLC */
  324. #define IRQ_RXDATA BIT10
  325. #define IRQ_RXIDLE BIT9 /* HDLC */
  326. #define IRQ_RXBREAK BIT9 /* async */
  327. #define IRQ_RXOVER BIT8
  328. #define IRQ_DSR BIT7
  329. #define IRQ_CTS BIT6
  330. #define IRQ_DCD BIT5
  331. #define IRQ_RI BIT4
  332. #define IRQ_ALL 0x3ff0
  333. #define IRQ_MASTER BIT0
  334. #define slgt_irq_on(info, mask) \
  335. wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
  336. #define slgt_irq_off(info, mask) \
  337. wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
  338. static __u8 rd_reg8(struct slgt_info *info, unsigned int addr);
  339. static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
  340. static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
  341. static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
  342. static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
  343. static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
  344. static void msc_set_vcr(struct slgt_info *info);
  345. static int startup(struct slgt_info *info);
  346. static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
  347. static void shutdown(struct slgt_info *info);
  348. static void program_hw(struct slgt_info *info);
  349. static void change_params(struct slgt_info *info);
  350. static int adapter_test(struct slgt_info *info);
  351. static void reset_port(struct slgt_info *info);
  352. static void async_mode(struct slgt_info *info);
  353. static void sync_mode(struct slgt_info *info);
  354. static void rx_stop(struct slgt_info *info);
  355. static void rx_start(struct slgt_info *info);
  356. static void reset_rbufs(struct slgt_info *info);
  357. static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
  358. static bool rx_get_frame(struct slgt_info *info);
  359. static bool rx_get_buf(struct slgt_info *info);
  360. static void tx_start(struct slgt_info *info);
  361. static void tx_stop(struct slgt_info *info);
  362. static void tx_set_idle(struct slgt_info *info);
  363. static unsigned int tbuf_bytes(struct slgt_info *info);
  364. static void reset_tbufs(struct slgt_info *info);
  365. static void tdma_reset(struct slgt_info *info);
  366. static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count);
  367. static void get_gtsignals(struct slgt_info *info);
  368. static void set_gtsignals(struct slgt_info *info);
  369. static void set_rate(struct slgt_info *info, u32 data_rate);
  370. static void bh_transmit(struct slgt_info *info);
  371. static void isr_txeom(struct slgt_info *info, unsigned short status);
  372. static void tx_timeout(struct timer_list *t);
  373. static void rx_timeout(struct timer_list *t);
  374. /*
  375. * ioctl handlers
  376. */
  377. static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
  378. static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
  379. static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
  380. static int get_txidle(struct slgt_info *info, int __user *idle_mode);
  381. static int set_txidle(struct slgt_info *info, int idle_mode);
  382. static int tx_enable(struct slgt_info *info, int enable);
  383. static int tx_abort(struct slgt_info *info);
  384. static int rx_enable(struct slgt_info *info, int enable);
  385. static int modem_input_wait(struct slgt_info *info,int arg);
  386. static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
  387. static int get_interface(struct slgt_info *info, int __user *if_mode);
  388. static int set_interface(struct slgt_info *info, int if_mode);
  389. static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
  390. static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
  391. static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
  392. static int get_xsync(struct slgt_info *info, int __user *if_mode);
  393. static int set_xsync(struct slgt_info *info, int if_mode);
  394. static int get_xctrl(struct slgt_info *info, int __user *if_mode);
  395. static int set_xctrl(struct slgt_info *info, int if_mode);
  396. /*
  397. * driver functions
  398. */
  399. static void release_resources(struct slgt_info *info);
  400. /*
  401. * DEBUG OUTPUT CODE
  402. */
  403. #ifndef DBGINFO
  404. #define DBGINFO(fmt)
  405. #endif
  406. #ifndef DBGERR
  407. #define DBGERR(fmt)
  408. #endif
  409. #ifndef DBGBH
  410. #define DBGBH(fmt)
  411. #endif
  412. #ifndef DBGISR
  413. #define DBGISR(fmt)
  414. #endif
  415. #ifdef DBGDATA
  416. static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
  417. {
  418. int i;
  419. int linecount;
  420. printk("%s %s data:\n",info->device_name, label);
  421. while(count) {
  422. linecount = (count > 16) ? 16 : count;
  423. for(i=0; i < linecount; i++)
  424. printk("%02X ",(unsigned char)data[i]);
  425. for(;i<17;i++)
  426. printk(" ");
  427. for(i=0;i<linecount;i++) {
  428. if (data[i]>=040 && data[i]<=0176)
  429. printk("%c",data[i]);
  430. else
  431. printk(".");
  432. }
  433. printk("\n");
  434. data += linecount;
  435. count -= linecount;
  436. }
  437. }
  438. #else
  439. #define DBGDATA(info, buf, size, label)
  440. #endif
  441. #ifdef DBGTBUF
  442. static void dump_tbufs(struct slgt_info *info)
  443. {
  444. int i;
  445. printk("tbuf_current=%d\n", info->tbuf_current);
  446. for (i=0 ; i < info->tbuf_count ; i++) {
  447. printk("%d: count=%04X status=%04X\n",
  448. i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
  449. }
  450. }
  451. #else
  452. #define DBGTBUF(info)
  453. #endif
  454. #ifdef DBGRBUF
  455. static void dump_rbufs(struct slgt_info *info)
  456. {
  457. int i;
  458. printk("rbuf_current=%d\n", info->rbuf_current);
  459. for (i=0 ; i < info->rbuf_count ; i++) {
  460. printk("%d: count=%04X status=%04X\n",
  461. i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
  462. }
  463. }
  464. #else
  465. #define DBGRBUF(info)
  466. #endif
  467. static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
  468. {
  469. #ifdef SANITY_CHECK
  470. if (!info) {
  471. printk("null struct slgt_info for (%s) in %s\n", devname, name);
  472. return 1;
  473. }
  474. if (info->magic != MGSL_MAGIC) {
  475. printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
  476. return 1;
  477. }
  478. #else
  479. if (!info)
  480. return 1;
  481. #endif
  482. return 0;
  483. }
  484. /**
  485. * line discipline callback wrappers
  486. *
  487. * The wrappers maintain line discipline references
  488. * while calling into the line discipline.
  489. *
  490. * ldisc_receive_buf - pass receive data to line discipline
  491. */
  492. static void ldisc_receive_buf(struct tty_struct *tty,
  493. const __u8 *data, char *flags, int count)
  494. {
  495. struct tty_ldisc *ld;
  496. if (!tty)
  497. return;
  498. ld = tty_ldisc_ref(tty);
  499. if (ld) {
  500. if (ld->ops->receive_buf)
  501. ld->ops->receive_buf(tty, data, flags, count);
  502. tty_ldisc_deref(ld);
  503. }
  504. }
  505. /* tty callbacks */
  506. static int open(struct tty_struct *tty, struct file *filp)
  507. {
  508. struct slgt_info *info;
  509. int retval, line;
  510. unsigned long flags;
  511. line = tty->index;
  512. if (line >= slgt_device_count) {
  513. DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
  514. return -ENODEV;
  515. }
  516. info = slgt_device_list;
  517. while(info && info->line != line)
  518. info = info->next_device;
  519. if (sanity_check(info, tty->name, "open"))
  520. return -ENODEV;
  521. if (info->init_error) {
  522. DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
  523. return -ENODEV;
  524. }
  525. tty->driver_data = info;
  526. info->port.tty = tty;
  527. DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
  528. mutex_lock(&info->port.mutex);
  529. info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
  530. spin_lock_irqsave(&info->netlock, flags);
  531. if (info->netcount) {
  532. retval = -EBUSY;
  533. spin_unlock_irqrestore(&info->netlock, flags);
  534. mutex_unlock(&info->port.mutex);
  535. goto cleanup;
  536. }
  537. info->port.count++;
  538. spin_unlock_irqrestore(&info->netlock, flags);
  539. if (info->port.count == 1) {
  540. /* 1st open on this device, init hardware */
  541. retval = startup(info);
  542. if (retval < 0) {
  543. mutex_unlock(&info->port.mutex);
  544. goto cleanup;
  545. }
  546. }
  547. mutex_unlock(&info->port.mutex);
  548. retval = block_til_ready(tty, filp, info);
  549. if (retval) {
  550. DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
  551. goto cleanup;
  552. }
  553. retval = 0;
  554. cleanup:
  555. if (retval) {
  556. if (tty->count == 1)
  557. info->port.tty = NULL; /* tty layer will release tty struct */
  558. if(info->port.count)
  559. info->port.count--;
  560. }
  561. DBGINFO(("%s open rc=%d\n", info->device_name, retval));
  562. return retval;
  563. }
  564. static void close(struct tty_struct *tty, struct file *filp)
  565. {
  566. struct slgt_info *info = tty->driver_data;
  567. if (sanity_check(info, tty->name, "close"))
  568. return;
  569. DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
  570. if (tty_port_close_start(&info->port, tty, filp) == 0)
  571. goto cleanup;
  572. mutex_lock(&info->port.mutex);
  573. if (tty_port_initialized(&info->port))
  574. wait_until_sent(tty, info->timeout);
  575. flush_buffer(tty);
  576. tty_ldisc_flush(tty);
  577. shutdown(info);
  578. mutex_unlock(&info->port.mutex);
  579. tty_port_close_end(&info->port, tty);
  580. info->port.tty = NULL;
  581. cleanup:
  582. DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
  583. }
  584. static void hangup(struct tty_struct *tty)
  585. {
  586. struct slgt_info *info = tty->driver_data;
  587. unsigned long flags;
  588. if (sanity_check(info, tty->name, "hangup"))
  589. return;
  590. DBGINFO(("%s hangup\n", info->device_name));
  591. flush_buffer(tty);
  592. mutex_lock(&info->port.mutex);
  593. shutdown(info);
  594. spin_lock_irqsave(&info->port.lock, flags);
  595. info->port.count = 0;
  596. info->port.tty = NULL;
  597. spin_unlock_irqrestore(&info->port.lock, flags);
  598. tty_port_set_active(&info->port, 0);
  599. mutex_unlock(&info->port.mutex);
  600. wake_up_interruptible(&info->port.open_wait);
  601. }
  602. static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
  603. {
  604. struct slgt_info *info = tty->driver_data;
  605. unsigned long flags;
  606. DBGINFO(("%s set_termios\n", tty->driver->name));
  607. change_params(info);
  608. /* Handle transition to B0 status */
  609. if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
  610. info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
  611. spin_lock_irqsave(&info->lock,flags);
  612. set_gtsignals(info);
  613. spin_unlock_irqrestore(&info->lock,flags);
  614. }
  615. /* Handle transition away from B0 status */
  616. if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
  617. info->signals |= SerialSignal_DTR;
  618. if (!C_CRTSCTS(tty) || !tty_throttled(tty))
  619. info->signals |= SerialSignal_RTS;
  620. spin_lock_irqsave(&info->lock,flags);
  621. set_gtsignals(info);
  622. spin_unlock_irqrestore(&info->lock,flags);
  623. }
  624. /* Handle turning off CRTSCTS */
  625. if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) {
  626. tty->hw_stopped = 0;
  627. tx_release(tty);
  628. }
  629. }
  630. static void update_tx_timer(struct slgt_info *info)
  631. {
  632. /*
  633. * use worst case speed of 1200bps to calculate transmit timeout
  634. * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
  635. */
  636. if (info->params.mode == MGSL_MODE_HDLC) {
  637. int timeout = (tbuf_bytes(info) * 7) + 1000;
  638. mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
  639. }
  640. }
  641. static int write(struct tty_struct *tty,
  642. const unsigned char *buf, int count)
  643. {
  644. int ret = 0;
  645. struct slgt_info *info = tty->driver_data;
  646. unsigned long flags;
  647. if (sanity_check(info, tty->name, "write"))
  648. return -EIO;
  649. DBGINFO(("%s write count=%d\n", info->device_name, count));
  650. if (!info->tx_buf || (count > info->max_frame_size))
  651. return -EIO;
  652. if (!count || tty->stopped || tty->hw_stopped)
  653. return 0;
  654. spin_lock_irqsave(&info->lock, flags);
  655. if (info->tx_count) {
  656. /* send accumulated data from send_char() */
  657. if (!tx_load(info, info->tx_buf, info->tx_count))
  658. goto cleanup;
  659. info->tx_count = 0;
  660. }
  661. if (tx_load(info, buf, count))
  662. ret = count;
  663. cleanup:
  664. spin_unlock_irqrestore(&info->lock, flags);
  665. DBGINFO(("%s write rc=%d\n", info->device_name, ret));
  666. return ret;
  667. }
  668. static int put_char(struct tty_struct *tty, unsigned char ch)
  669. {
  670. struct slgt_info *info = tty->driver_data;
  671. unsigned long flags;
  672. int ret = 0;
  673. if (sanity_check(info, tty->name, "put_char"))
  674. return 0;
  675. DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
  676. if (!info->tx_buf)
  677. return 0;
  678. spin_lock_irqsave(&info->lock,flags);
  679. if (info->tx_count < info->max_frame_size) {
  680. info->tx_buf[info->tx_count++] = ch;
  681. ret = 1;
  682. }
  683. spin_unlock_irqrestore(&info->lock,flags);
  684. return ret;
  685. }
  686. static void send_xchar(struct tty_struct *tty, char ch)
  687. {
  688. struct slgt_info *info = tty->driver_data;
  689. unsigned long flags;
  690. if (sanity_check(info, tty->name, "send_xchar"))
  691. return;
  692. DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
  693. info->x_char = ch;
  694. if (ch) {
  695. spin_lock_irqsave(&info->lock,flags);
  696. if (!info->tx_enabled)
  697. tx_start(info);
  698. spin_unlock_irqrestore(&info->lock,flags);
  699. }
  700. }
  701. static void wait_until_sent(struct tty_struct *tty, int timeout)
  702. {
  703. struct slgt_info *info = tty->driver_data;
  704. unsigned long orig_jiffies, char_time;
  705. if (!info )
  706. return;
  707. if (sanity_check(info, tty->name, "wait_until_sent"))
  708. return;
  709. DBGINFO(("%s wait_until_sent entry\n", info->device_name));
  710. if (!tty_port_initialized(&info->port))
  711. goto exit;
  712. orig_jiffies = jiffies;
  713. /* Set check interval to 1/5 of estimated time to
  714. * send a character, and make it at least 1. The check
  715. * interval should also be less than the timeout.
  716. * Note: use tight timings here to satisfy the NIST-PCTS.
  717. */
  718. if (info->params.data_rate) {
  719. char_time = info->timeout/(32 * 5);
  720. if (!char_time)
  721. char_time++;
  722. } else
  723. char_time = 1;
  724. if (timeout)
  725. char_time = min_t(unsigned long, char_time, timeout);
  726. while (info->tx_active) {
  727. msleep_interruptible(jiffies_to_msecs(char_time));
  728. if (signal_pending(current))
  729. break;
  730. if (timeout && time_after(jiffies, orig_jiffies + timeout))
  731. break;
  732. }
  733. exit:
  734. DBGINFO(("%s wait_until_sent exit\n", info->device_name));
  735. }
  736. static int write_room(struct tty_struct *tty)
  737. {
  738. struct slgt_info *info = tty->driver_data;
  739. int ret;
  740. if (sanity_check(info, tty->name, "write_room"))
  741. return 0;
  742. ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
  743. DBGINFO(("%s write_room=%d\n", info->device_name, ret));
  744. return ret;
  745. }
  746. static void flush_chars(struct tty_struct *tty)
  747. {
  748. struct slgt_info *info = tty->driver_data;
  749. unsigned long flags;
  750. if (sanity_check(info, tty->name, "flush_chars"))
  751. return;
  752. DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
  753. if (info->tx_count <= 0 || tty->stopped ||
  754. tty->hw_stopped || !info->tx_buf)
  755. return;
  756. DBGINFO(("%s flush_chars start transmit\n", info->device_name));
  757. spin_lock_irqsave(&info->lock,flags);
  758. if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
  759. info->tx_count = 0;
  760. spin_unlock_irqrestore(&info->lock,flags);
  761. }
  762. static void flush_buffer(struct tty_struct *tty)
  763. {
  764. struct slgt_info *info = tty->driver_data;
  765. unsigned long flags;
  766. if (sanity_check(info, tty->name, "flush_buffer"))
  767. return;
  768. DBGINFO(("%s flush_buffer\n", info->device_name));
  769. spin_lock_irqsave(&info->lock, flags);
  770. info->tx_count = 0;
  771. spin_unlock_irqrestore(&info->lock, flags);
  772. tty_wakeup(tty);
  773. }
  774. /*
  775. * throttle (stop) transmitter
  776. */
  777. static void tx_hold(struct tty_struct *tty)
  778. {
  779. struct slgt_info *info = tty->driver_data;
  780. unsigned long flags;
  781. if (sanity_check(info, tty->name, "tx_hold"))
  782. return;
  783. DBGINFO(("%s tx_hold\n", info->device_name));
  784. spin_lock_irqsave(&info->lock,flags);
  785. if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
  786. tx_stop(info);
  787. spin_unlock_irqrestore(&info->lock,flags);
  788. }
  789. /*
  790. * release (start) transmitter
  791. */
  792. static void tx_release(struct tty_struct *tty)
  793. {
  794. struct slgt_info *info = tty->driver_data;
  795. unsigned long flags;
  796. if (sanity_check(info, tty->name, "tx_release"))
  797. return;
  798. DBGINFO(("%s tx_release\n", info->device_name));
  799. spin_lock_irqsave(&info->lock, flags);
  800. if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
  801. info->tx_count = 0;
  802. spin_unlock_irqrestore(&info->lock, flags);
  803. }
  804. /*
  805. * Service an IOCTL request
  806. *
  807. * Arguments
  808. *
  809. * tty pointer to tty instance data
  810. * cmd IOCTL command code
  811. * arg command argument/context
  812. *
  813. * Return 0 if success, otherwise error code
  814. */
  815. static int ioctl(struct tty_struct *tty,
  816. unsigned int cmd, unsigned long arg)
  817. {
  818. struct slgt_info *info = tty->driver_data;
  819. void __user *argp = (void __user *)arg;
  820. int ret;
  821. if (sanity_check(info, tty->name, "ioctl"))
  822. return -ENODEV;
  823. DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
  824. if (cmd != TIOCMIWAIT) {
  825. if (tty_io_error(tty))
  826. return -EIO;
  827. }
  828. switch (cmd) {
  829. case MGSL_IOCWAITEVENT:
  830. return wait_mgsl_event(info, argp);
  831. case TIOCMIWAIT:
  832. return modem_input_wait(info,(int)arg);
  833. case MGSL_IOCSGPIO:
  834. return set_gpio(info, argp);
  835. case MGSL_IOCGGPIO:
  836. return get_gpio(info, argp);
  837. case MGSL_IOCWAITGPIO:
  838. return wait_gpio(info, argp);
  839. case MGSL_IOCGXSYNC:
  840. return get_xsync(info, argp);
  841. case MGSL_IOCSXSYNC:
  842. return set_xsync(info, (int)arg);
  843. case MGSL_IOCGXCTRL:
  844. return get_xctrl(info, argp);
  845. case MGSL_IOCSXCTRL:
  846. return set_xctrl(info, (int)arg);
  847. }
  848. mutex_lock(&info->port.mutex);
  849. switch (cmd) {
  850. case MGSL_IOCGPARAMS:
  851. ret = get_params(info, argp);
  852. break;
  853. case MGSL_IOCSPARAMS:
  854. ret = set_params(info, argp);
  855. break;
  856. case MGSL_IOCGTXIDLE:
  857. ret = get_txidle(info, argp);
  858. break;
  859. case MGSL_IOCSTXIDLE:
  860. ret = set_txidle(info, (int)arg);
  861. break;
  862. case MGSL_IOCTXENABLE:
  863. ret = tx_enable(info, (int)arg);
  864. break;
  865. case MGSL_IOCRXENABLE:
  866. ret = rx_enable(info, (int)arg);
  867. break;
  868. case MGSL_IOCTXABORT:
  869. ret = tx_abort(info);
  870. break;
  871. case MGSL_IOCGSTATS:
  872. ret = get_stats(info, argp);
  873. break;
  874. case MGSL_IOCGIF:
  875. ret = get_interface(info, argp);
  876. break;
  877. case MGSL_IOCSIF:
  878. ret = set_interface(info,(int)arg);
  879. break;
  880. default:
  881. ret = -ENOIOCTLCMD;
  882. }
  883. mutex_unlock(&info->port.mutex);
  884. return ret;
  885. }
  886. static int get_icount(struct tty_struct *tty,
  887. struct serial_icounter_struct *icount)
  888. {
  889. struct slgt_info *info = tty->driver_data;
  890. struct mgsl_icount cnow; /* kernel counter temps */
  891. unsigned long flags;
  892. spin_lock_irqsave(&info->lock,flags);
  893. cnow = info->icount;
  894. spin_unlock_irqrestore(&info->lock,flags);
  895. icount->cts = cnow.cts;
  896. icount->dsr = cnow.dsr;
  897. icount->rng = cnow.rng;
  898. icount->dcd = cnow.dcd;
  899. icount->rx = cnow.rx;
  900. icount->tx = cnow.tx;
  901. icount->frame = cnow.frame;
  902. icount->overrun = cnow.overrun;
  903. icount->parity = cnow.parity;
  904. icount->brk = cnow.brk;
  905. icount->buf_overrun = cnow.buf_overrun;
  906. return 0;
  907. }
  908. /*
  909. * support for 32 bit ioctl calls on 64 bit systems
  910. */
  911. #ifdef CONFIG_COMPAT
  912. static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
  913. {
  914. struct MGSL_PARAMS32 tmp_params;
  915. DBGINFO(("%s get_params32\n", info->device_name));
  916. memset(&tmp_params, 0, sizeof(tmp_params));
  917. tmp_params.mode = (compat_ulong_t)info->params.mode;
  918. tmp_params.loopback = info->params.loopback;
  919. tmp_params.flags = info->params.flags;
  920. tmp_params.encoding = info->params.encoding;
  921. tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed;
  922. tmp_params.addr_filter = info->params.addr_filter;
  923. tmp_params.crc_type = info->params.crc_type;
  924. tmp_params.preamble_length = info->params.preamble_length;
  925. tmp_params.preamble = info->params.preamble;
  926. tmp_params.data_rate = (compat_ulong_t)info->params.data_rate;
  927. tmp_params.data_bits = info->params.data_bits;
  928. tmp_params.stop_bits = info->params.stop_bits;
  929. tmp_params.parity = info->params.parity;
  930. if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
  931. return -EFAULT;
  932. return 0;
  933. }
  934. static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
  935. {
  936. struct MGSL_PARAMS32 tmp_params;
  937. DBGINFO(("%s set_params32\n", info->device_name));
  938. if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
  939. return -EFAULT;
  940. spin_lock(&info->lock);
  941. if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
  942. info->base_clock = tmp_params.clock_speed;
  943. } else {
  944. info->params.mode = tmp_params.mode;
  945. info->params.loopback = tmp_params.loopback;
  946. info->params.flags = tmp_params.flags;
  947. info->params.encoding = tmp_params.encoding;
  948. info->params.clock_speed = tmp_params.clock_speed;
  949. info->params.addr_filter = tmp_params.addr_filter;
  950. info->params.crc_type = tmp_params.crc_type;
  951. info->params.preamble_length = tmp_params.preamble_length;
  952. info->params.preamble = tmp_params.preamble;
  953. info->params.data_rate = tmp_params.data_rate;
  954. info->params.data_bits = tmp_params.data_bits;
  955. info->params.stop_bits = tmp_params.stop_bits;
  956. info->params.parity = tmp_params.parity;
  957. }
  958. spin_unlock(&info->lock);
  959. program_hw(info);
  960. return 0;
  961. }
  962. static long slgt_compat_ioctl(struct tty_struct *tty,
  963. unsigned int cmd, unsigned long arg)
  964. {
  965. struct slgt_info *info = tty->driver_data;
  966. int rc;
  967. if (sanity_check(info, tty->name, "compat_ioctl"))
  968. return -ENODEV;
  969. DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
  970. switch (cmd) {
  971. case MGSL_IOCSPARAMS32:
  972. rc = set_params32(info, compat_ptr(arg));
  973. break;
  974. case MGSL_IOCGPARAMS32:
  975. rc = get_params32(info, compat_ptr(arg));
  976. break;
  977. case MGSL_IOCGPARAMS:
  978. case MGSL_IOCSPARAMS:
  979. case MGSL_IOCGTXIDLE:
  980. case MGSL_IOCGSTATS:
  981. case MGSL_IOCWAITEVENT:
  982. case MGSL_IOCGIF:
  983. case MGSL_IOCSGPIO:
  984. case MGSL_IOCGGPIO:
  985. case MGSL_IOCWAITGPIO:
  986. case MGSL_IOCGXSYNC:
  987. case MGSL_IOCGXCTRL:
  988. rc = ioctl(tty, cmd, (unsigned long)compat_ptr(arg));
  989. break;
  990. default:
  991. rc = ioctl(tty, cmd, arg);
  992. }
  993. DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
  994. return rc;
  995. }
  996. #else
  997. #define slgt_compat_ioctl NULL
  998. #endif /* ifdef CONFIG_COMPAT */
  999. /*
  1000. * proc fs support
  1001. */
  1002. static inline void line_info(struct seq_file *m, struct slgt_info *info)
  1003. {
  1004. char stat_buf[30];
  1005. unsigned long flags;
  1006. seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
  1007. info->device_name, info->phys_reg_addr,
  1008. info->irq_level, info->max_frame_size);
  1009. /* output current serial signal states */
  1010. spin_lock_irqsave(&info->lock,flags);
  1011. get_gtsignals(info);
  1012. spin_unlock_irqrestore(&info->lock,flags);
  1013. stat_buf[0] = 0;
  1014. stat_buf[1] = 0;
  1015. if (info->signals & SerialSignal_RTS)
  1016. strcat(stat_buf, "|RTS");
  1017. if (info->signals & SerialSignal_CTS)
  1018. strcat(stat_buf, "|CTS");
  1019. if (info->signals & SerialSignal_DTR)
  1020. strcat(stat_buf, "|DTR");
  1021. if (info->signals & SerialSignal_DSR)
  1022. strcat(stat_buf, "|DSR");
  1023. if (info->signals & SerialSignal_DCD)
  1024. strcat(stat_buf, "|CD");
  1025. if (info->signals & SerialSignal_RI)
  1026. strcat(stat_buf, "|RI");
  1027. if (info->params.mode != MGSL_MODE_ASYNC) {
  1028. seq_printf(m, "\tHDLC txok:%d rxok:%d",
  1029. info->icount.txok, info->icount.rxok);
  1030. if (info->icount.txunder)
  1031. seq_printf(m, " txunder:%d", info->icount.txunder);
  1032. if (info->icount.txabort)
  1033. seq_printf(m, " txabort:%d", info->icount.txabort);
  1034. if (info->icount.rxshort)
  1035. seq_printf(m, " rxshort:%d", info->icount.rxshort);
  1036. if (info->icount.rxlong)
  1037. seq_printf(m, " rxlong:%d", info->icount.rxlong);
  1038. if (info->icount.rxover)
  1039. seq_printf(m, " rxover:%d", info->icount.rxover);
  1040. if (info->icount.rxcrc)
  1041. seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
  1042. } else {
  1043. seq_printf(m, "\tASYNC tx:%d rx:%d",
  1044. info->icount.tx, info->icount.rx);
  1045. if (info->icount.frame)
  1046. seq_printf(m, " fe:%d", info->icount.frame);
  1047. if (info->icount.parity)
  1048. seq_printf(m, " pe:%d", info->icount.parity);
  1049. if (info->icount.brk)
  1050. seq_printf(m, " brk:%d", info->icount.brk);
  1051. if (info->icount.overrun)
  1052. seq_printf(m, " oe:%d", info->icount.overrun);
  1053. }
  1054. /* Append serial signal status to end */
  1055. seq_printf(m, " %s\n", stat_buf+1);
  1056. seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
  1057. info->tx_active,info->bh_requested,info->bh_running,
  1058. info->pending_bh);
  1059. }
  1060. /* Called to print information about devices
  1061. */
  1062. static int synclink_gt_proc_show(struct seq_file *m, void *v)
  1063. {
  1064. struct slgt_info *info;
  1065. seq_puts(m, "synclink_gt driver\n");
  1066. info = slgt_device_list;
  1067. while( info ) {
  1068. line_info(m, info);
  1069. info = info->next_device;
  1070. }
  1071. return 0;
  1072. }
  1073. /*
  1074. * return count of bytes in transmit buffer
  1075. */
  1076. static int chars_in_buffer(struct tty_struct *tty)
  1077. {
  1078. struct slgt_info *info = tty->driver_data;
  1079. int count;
  1080. if (sanity_check(info, tty->name, "chars_in_buffer"))
  1081. return 0;
  1082. count = tbuf_bytes(info);
  1083. DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count));
  1084. return count;
  1085. }
  1086. /*
  1087. * signal remote device to throttle send data (our receive data)
  1088. */
  1089. static void throttle(struct tty_struct * tty)
  1090. {
  1091. struct slgt_info *info = tty->driver_data;
  1092. unsigned long flags;
  1093. if (sanity_check(info, tty->name, "throttle"))
  1094. return;
  1095. DBGINFO(("%s throttle\n", info->device_name));
  1096. if (I_IXOFF(tty))
  1097. send_xchar(tty, STOP_CHAR(tty));
  1098. if (C_CRTSCTS(tty)) {
  1099. spin_lock_irqsave(&info->lock,flags);
  1100. info->signals &= ~SerialSignal_RTS;
  1101. set_gtsignals(info);
  1102. spin_unlock_irqrestore(&info->lock,flags);
  1103. }
  1104. }
  1105. /*
  1106. * signal remote device to stop throttling send data (our receive data)
  1107. */
  1108. static void unthrottle(struct tty_struct * tty)
  1109. {
  1110. struct slgt_info *info = tty->driver_data;
  1111. unsigned long flags;
  1112. if (sanity_check(info, tty->name, "unthrottle"))
  1113. return;
  1114. DBGINFO(("%s unthrottle\n", info->device_name));
  1115. if (I_IXOFF(tty)) {
  1116. if (info->x_char)
  1117. info->x_char = 0;
  1118. else
  1119. send_xchar(tty, START_CHAR(tty));
  1120. }
  1121. if (C_CRTSCTS(tty)) {
  1122. spin_lock_irqsave(&info->lock,flags);
  1123. info->signals |= SerialSignal_RTS;
  1124. set_gtsignals(info);
  1125. spin_unlock_irqrestore(&info->lock,flags);
  1126. }
  1127. }
  1128. /*
  1129. * set or clear transmit break condition
  1130. * break_state -1=set break condition, 0=clear
  1131. */
  1132. static int set_break(struct tty_struct *tty, int break_state)
  1133. {
  1134. struct slgt_info *info = tty->driver_data;
  1135. unsigned short value;
  1136. unsigned long flags;
  1137. if (sanity_check(info, tty->name, "set_break"))
  1138. return -EINVAL;
  1139. DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
  1140. spin_lock_irqsave(&info->lock,flags);
  1141. value = rd_reg16(info, TCR);
  1142. if (break_state == -1)
  1143. value |= BIT6;
  1144. else
  1145. value &= ~BIT6;
  1146. wr_reg16(info, TCR, value);
  1147. spin_unlock_irqrestore(&info->lock,flags);
  1148. return 0;
  1149. }
  1150. #if SYNCLINK_GENERIC_HDLC
  1151. /**
  1152. * hdlcdev_attach - called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
  1153. * @dev: pointer to network device structure
  1154. * @encoding: serial encoding setting
  1155. * @parity: FCS setting
  1156. *
  1157. * Set encoding and frame check sequence (FCS) options.
  1158. *
  1159. * Return: 0 if success, otherwise error code
  1160. */
  1161. static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
  1162. unsigned short parity)
  1163. {
  1164. struct slgt_info *info = dev_to_port(dev);
  1165. unsigned char new_encoding;
  1166. unsigned short new_crctype;
  1167. /* return error if TTY interface open */
  1168. if (info->port.count)
  1169. return -EBUSY;
  1170. DBGINFO(("%s hdlcdev_attach\n", info->device_name));
  1171. switch (encoding)
  1172. {
  1173. case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
  1174. case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
  1175. case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
  1176. case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
  1177. case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
  1178. default: return -EINVAL;
  1179. }
  1180. switch (parity)
  1181. {
  1182. case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
  1183. case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
  1184. case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
  1185. default: return -EINVAL;
  1186. }
  1187. info->params.encoding = new_encoding;
  1188. info->params.crc_type = new_crctype;
  1189. /* if network interface up, reprogram hardware */
  1190. if (info->netcount)
  1191. program_hw(info);
  1192. return 0;
  1193. }
  1194. /**
  1195. * hdlcdev_xmit - called by generic HDLC layer to send a frame
  1196. * @skb: socket buffer containing HDLC frame
  1197. * @dev: pointer to network device structure
  1198. */
  1199. static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
  1200. struct net_device *dev)
  1201. {
  1202. struct slgt_info *info = dev_to_port(dev);
  1203. unsigned long flags;
  1204. DBGINFO(("%s hdlc_xmit\n", dev->name));
  1205. if (!skb->len)
  1206. return NETDEV_TX_OK;
  1207. /* stop sending until this frame completes */
  1208. netif_stop_queue(dev);
  1209. /* update network statistics */
  1210. dev->stats.tx_packets++;
  1211. dev->stats.tx_bytes += skb->len;
  1212. /* save start time for transmit timeout detection */
  1213. netif_trans_update(dev);
  1214. spin_lock_irqsave(&info->lock, flags);
  1215. tx_load(info, skb->data, skb->len);
  1216. spin_unlock_irqrestore(&info->lock, flags);
  1217. /* done with socket buffer, so free it */
  1218. dev_kfree_skb(skb);
  1219. return NETDEV_TX_OK;
  1220. }
  1221. /**
  1222. * hdlcdev_open - called by network layer when interface enabled
  1223. * @dev: pointer to network device structure
  1224. *
  1225. * Claim resources and initialize hardware.
  1226. *
  1227. * Return: 0 if success, otherwise error code
  1228. */
  1229. static int hdlcdev_open(struct net_device *dev)
  1230. {
  1231. struct slgt_info *info = dev_to_port(dev);
  1232. int rc;
  1233. unsigned long flags;
  1234. if (!try_module_get(THIS_MODULE))
  1235. return -EBUSY;
  1236. DBGINFO(("%s hdlcdev_open\n", dev->name));
  1237. /* generic HDLC layer open processing */
  1238. rc = hdlc_open(dev);
  1239. if (rc)
  1240. return rc;
  1241. /* arbitrate between network and tty opens */
  1242. spin_lock_irqsave(&info->netlock, flags);
  1243. if (info->port.count != 0 || info->netcount != 0) {
  1244. DBGINFO(("%s hdlc_open busy\n", dev->name));
  1245. spin_unlock_irqrestore(&info->netlock, flags);
  1246. return -EBUSY;
  1247. }
  1248. info->netcount=1;
  1249. spin_unlock_irqrestore(&info->netlock, flags);
  1250. /* claim resources and init adapter */
  1251. if ((rc = startup(info)) != 0) {
  1252. spin_lock_irqsave(&info->netlock, flags);
  1253. info->netcount=0;
  1254. spin_unlock_irqrestore(&info->netlock, flags);
  1255. return rc;
  1256. }
  1257. /* assert RTS and DTR, apply hardware settings */
  1258. info->signals |= SerialSignal_RTS | SerialSignal_DTR;
  1259. program_hw(info);
  1260. /* enable network layer transmit */
  1261. netif_trans_update(dev);
  1262. netif_start_queue(dev);
  1263. /* inform generic HDLC layer of current DCD status */
  1264. spin_lock_irqsave(&info->lock, flags);
  1265. get_gtsignals(info);
  1266. spin_unlock_irqrestore(&info->lock, flags);
  1267. if (info->signals & SerialSignal_DCD)
  1268. netif_carrier_on(dev);
  1269. else
  1270. netif_carrier_off(dev);
  1271. return 0;
  1272. }
  1273. /**
  1274. * hdlcdev_close - called by network layer when interface is disabled
  1275. * @dev: pointer to network device structure
  1276. *
  1277. * Shutdown hardware and release resources.
  1278. *
  1279. * Return: 0 if success, otherwise error code
  1280. */
  1281. static int hdlcdev_close(struct net_device *dev)
  1282. {
  1283. struct slgt_info *info = dev_to_port(dev);
  1284. unsigned long flags;
  1285. DBGINFO(("%s hdlcdev_close\n", dev->name));
  1286. netif_stop_queue(dev);
  1287. /* shutdown adapter and release resources */
  1288. shutdown(info);
  1289. hdlc_close(dev);
  1290. spin_lock_irqsave(&info->netlock, flags);
  1291. info->netcount=0;
  1292. spin_unlock_irqrestore(&info->netlock, flags);
  1293. module_put(THIS_MODULE);
  1294. return 0;
  1295. }
  1296. /**
  1297. * hdlcdev_ioctl - called by network layer to process IOCTL call to network device
  1298. * @dev: pointer to network device structure
  1299. * @ifr: pointer to network interface request structure
  1300. * @cmd: IOCTL command code
  1301. *
  1302. * Return: 0 if success, otherwise error code
  1303. */
  1304. static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  1305. {
  1306. const size_t size = sizeof(sync_serial_settings);
  1307. sync_serial_settings new_line;
  1308. sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
  1309. struct slgt_info *info = dev_to_port(dev);
  1310. unsigned int flags;
  1311. DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
  1312. /* return error if TTY interface open */
  1313. if (info->port.count)
  1314. return -EBUSY;
  1315. if (cmd != SIOCWANDEV)
  1316. return hdlc_ioctl(dev, ifr, cmd);
  1317. memset(&new_line, 0, sizeof(new_line));
  1318. switch(ifr->ifr_settings.type) {
  1319. case IF_GET_IFACE: /* return current sync_serial_settings */
  1320. ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
  1321. if (ifr->ifr_settings.size < size) {
  1322. ifr->ifr_settings.size = size; /* data size wanted */
  1323. return -ENOBUFS;
  1324. }
  1325. flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  1326. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  1327. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  1328. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
  1329. switch (flags){
  1330. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
  1331. case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
  1332. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
  1333. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
  1334. default: new_line.clock_type = CLOCK_DEFAULT;
  1335. }
  1336. new_line.clock_rate = info->params.clock_speed;
  1337. new_line.loopback = info->params.loopback ? 1:0;
  1338. if (copy_to_user(line, &new_line, size))
  1339. return -EFAULT;
  1340. return 0;
  1341. case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
  1342. if(!capable(CAP_NET_ADMIN))
  1343. return -EPERM;
  1344. if (copy_from_user(&new_line, line, size))
  1345. return -EFAULT;
  1346. switch (new_line.clock_type)
  1347. {
  1348. case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
  1349. case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
  1350. case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
  1351. case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
  1352. case CLOCK_DEFAULT: flags = info->params.flags &
  1353. (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  1354. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  1355. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  1356. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
  1357. default: return -EINVAL;
  1358. }
  1359. if (new_line.loopback != 0 && new_line.loopback != 1)
  1360. return -EINVAL;
  1361. info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  1362. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  1363. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  1364. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
  1365. info->params.flags |= flags;
  1366. info->params.loopback = new_line.loopback;
  1367. if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
  1368. info->params.clock_speed = new_line.clock_rate;
  1369. else
  1370. info->params.clock_speed = 0;
  1371. /* if network interface up, reprogram hardware */
  1372. if (info->netcount)
  1373. program_hw(info);
  1374. return 0;
  1375. default:
  1376. return hdlc_ioctl(dev, ifr, cmd);
  1377. }
  1378. }
  1379. /**
  1380. * hdlcdev_tx_timeout - called by network layer when transmit timeout is detected
  1381. * @dev: pointer to network device structure
  1382. */
  1383. static void hdlcdev_tx_timeout(struct net_device *dev, unsigned int txqueue)
  1384. {
  1385. struct slgt_info *info = dev_to_port(dev);
  1386. unsigned long flags;
  1387. DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
  1388. dev->stats.tx_errors++;
  1389. dev->stats.tx_aborted_errors++;
  1390. spin_lock_irqsave(&info->lock,flags);
  1391. tx_stop(info);
  1392. spin_unlock_irqrestore(&info->lock,flags);
  1393. netif_wake_queue(dev);
  1394. }
  1395. /**
  1396. * hdlcdev_tx_done - called by device driver when transmit completes
  1397. * @info: pointer to device instance information
  1398. *
  1399. * Reenable network layer transmit if stopped.
  1400. */
  1401. static void hdlcdev_tx_done(struct slgt_info *info)
  1402. {
  1403. if (netif_queue_stopped(info->netdev))
  1404. netif_wake_queue(info->netdev);
  1405. }
  1406. /**
  1407. * hdlcdev_rx - called by device driver when frame received
  1408. * @info: pointer to device instance information
  1409. * @buf: pointer to buffer contianing frame data
  1410. * @size: count of data bytes in buf
  1411. *
  1412. * Pass frame to network layer.
  1413. */
  1414. static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
  1415. {
  1416. struct sk_buff *skb = dev_alloc_skb(size);
  1417. struct net_device *dev = info->netdev;
  1418. DBGINFO(("%s hdlcdev_rx\n", dev->name));
  1419. if (skb == NULL) {
  1420. DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
  1421. dev->stats.rx_dropped++;
  1422. return;
  1423. }
  1424. skb_put_data(skb, buf, size);
  1425. skb->protocol = hdlc_type_trans(skb, dev);
  1426. dev->stats.rx_packets++;
  1427. dev->stats.rx_bytes += size;
  1428. netif_rx(skb);
  1429. }
  1430. static const struct net_device_ops hdlcdev_ops = {
  1431. .ndo_open = hdlcdev_open,
  1432. .ndo_stop = hdlcdev_close,
  1433. .ndo_start_xmit = hdlc_start_xmit,
  1434. .ndo_do_ioctl = hdlcdev_ioctl,
  1435. .ndo_tx_timeout = hdlcdev_tx_timeout,
  1436. };
  1437. /**
  1438. * hdlcdev_init - called by device driver when adding device instance
  1439. * @info: pointer to device instance information
  1440. *
  1441. * Do generic HDLC initialization.
  1442. *
  1443. * Return: 0 if success, otherwise error code
  1444. */
  1445. static int hdlcdev_init(struct slgt_info *info)
  1446. {
  1447. int rc;
  1448. struct net_device *dev;
  1449. hdlc_device *hdlc;
  1450. /* allocate and initialize network and HDLC layer objects */
  1451. dev = alloc_hdlcdev(info);
  1452. if (!dev) {
  1453. printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
  1454. return -ENOMEM;
  1455. }
  1456. /* for network layer reporting purposes only */
  1457. dev->mem_start = info->phys_reg_addr;
  1458. dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1;
  1459. dev->irq = info->irq_level;
  1460. /* network layer callbacks and settings */
  1461. dev->netdev_ops = &hdlcdev_ops;
  1462. dev->watchdog_timeo = 10 * HZ;
  1463. dev->tx_queue_len = 50;
  1464. /* generic HDLC layer callbacks and settings */
  1465. hdlc = dev_to_hdlc(dev);
  1466. hdlc->attach = hdlcdev_attach;
  1467. hdlc->xmit = hdlcdev_xmit;
  1468. /* register objects with HDLC layer */
  1469. rc = register_hdlc_device(dev);
  1470. if (rc) {
  1471. printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
  1472. free_netdev(dev);
  1473. return rc;
  1474. }
  1475. info->netdev = dev;
  1476. return 0;
  1477. }
  1478. /**
  1479. * hdlcdev_exit - called by device driver when removing device instance
  1480. * @info: pointer to device instance information
  1481. *
  1482. * Do generic HDLC cleanup.
  1483. */
  1484. static void hdlcdev_exit(struct slgt_info *info)
  1485. {
  1486. unregister_hdlc_device(info->netdev);
  1487. free_netdev(info->netdev);
  1488. info->netdev = NULL;
  1489. }
  1490. #endif /* ifdef CONFIG_HDLC */
  1491. /*
  1492. * get async data from rx DMA buffers
  1493. */
  1494. static void rx_async(struct slgt_info *info)
  1495. {
  1496. struct mgsl_icount *icount = &info->icount;
  1497. unsigned int start, end;
  1498. unsigned char *p;
  1499. unsigned char status;
  1500. struct slgt_desc *bufs = info->rbufs;
  1501. int i, count;
  1502. int chars = 0;
  1503. int stat;
  1504. unsigned char ch;
  1505. start = end = info->rbuf_current;
  1506. while(desc_complete(bufs[end])) {
  1507. count = desc_count(bufs[end]) - info->rbuf_index;
  1508. p = bufs[end].buf + info->rbuf_index;
  1509. DBGISR(("%s rx_async count=%d\n", info->device_name, count));
  1510. DBGDATA(info, p, count, "rx");
  1511. for(i=0 ; i < count; i+=2, p+=2) {
  1512. ch = *p;
  1513. icount->rx++;
  1514. stat = 0;
  1515. status = *(p + 1) & (BIT1 + BIT0);
  1516. if (status) {
  1517. if (status & BIT1)
  1518. icount->parity++;
  1519. else if (status & BIT0)
  1520. icount->frame++;
  1521. /* discard char if tty control flags say so */
  1522. if (status & info->ignore_status_mask)
  1523. continue;
  1524. if (status & BIT1)
  1525. stat = TTY_PARITY;
  1526. else if (status & BIT0)
  1527. stat = TTY_FRAME;
  1528. }
  1529. tty_insert_flip_char(&info->port, ch, stat);
  1530. chars++;
  1531. }
  1532. if (i < count) {
  1533. /* receive buffer not completed */
  1534. info->rbuf_index += i;
  1535. mod_timer(&info->rx_timer, jiffies + 1);
  1536. break;
  1537. }
  1538. info->rbuf_index = 0;
  1539. free_rbufs(info, end, end);
  1540. if (++end == info->rbuf_count)
  1541. end = 0;
  1542. /* if entire list searched then no frame available */
  1543. if (end == start)
  1544. break;
  1545. }
  1546. if (chars)
  1547. tty_flip_buffer_push(&info->port);
  1548. }
  1549. /*
  1550. * return next bottom half action to perform
  1551. */
  1552. static int bh_action(struct slgt_info *info)
  1553. {
  1554. unsigned long flags;
  1555. int rc;
  1556. spin_lock_irqsave(&info->lock,flags);
  1557. if (info->pending_bh & BH_RECEIVE) {
  1558. info->pending_bh &= ~BH_RECEIVE;
  1559. rc = BH_RECEIVE;
  1560. } else if (info->pending_bh & BH_TRANSMIT) {
  1561. info->pending_bh &= ~BH_TRANSMIT;
  1562. rc = BH_TRANSMIT;
  1563. } else if (info->pending_bh & BH_STATUS) {
  1564. info->pending_bh &= ~BH_STATUS;
  1565. rc = BH_STATUS;
  1566. } else {
  1567. /* Mark BH routine as complete */
  1568. info->bh_running = false;
  1569. info->bh_requested = false;
  1570. rc = 0;
  1571. }
  1572. spin_unlock_irqrestore(&info->lock,flags);
  1573. return rc;
  1574. }
  1575. /*
  1576. * perform bottom half processing
  1577. */
  1578. static void bh_handler(struct work_struct *work)
  1579. {
  1580. struct slgt_info *info = container_of(work, struct slgt_info, task);
  1581. int action;
  1582. info->bh_running = true;
  1583. while((action = bh_action(info))) {
  1584. switch (action) {
  1585. case BH_RECEIVE:
  1586. DBGBH(("%s bh receive\n", info->device_name));
  1587. switch(info->params.mode) {
  1588. case MGSL_MODE_ASYNC:
  1589. rx_async(info);
  1590. break;
  1591. case MGSL_MODE_HDLC:
  1592. while(rx_get_frame(info));
  1593. break;
  1594. case MGSL_MODE_RAW:
  1595. case MGSL_MODE_MONOSYNC:
  1596. case MGSL_MODE_BISYNC:
  1597. case MGSL_MODE_XSYNC:
  1598. while(rx_get_buf(info));
  1599. break;
  1600. }
  1601. /* restart receiver if rx DMA buffers exhausted */
  1602. if (info->rx_restart)
  1603. rx_start(info);
  1604. break;
  1605. case BH_TRANSMIT:
  1606. bh_transmit(info);
  1607. break;
  1608. case BH_STATUS:
  1609. DBGBH(("%s bh status\n", info->device_name));
  1610. info->ri_chkcount = 0;
  1611. info->dsr_chkcount = 0;
  1612. info->dcd_chkcount = 0;
  1613. info->cts_chkcount = 0;
  1614. break;
  1615. default:
  1616. DBGBH(("%s unknown action\n", info->device_name));
  1617. break;
  1618. }
  1619. }
  1620. DBGBH(("%s bh_handler exit\n", info->device_name));
  1621. }
  1622. static void bh_transmit(struct slgt_info *info)
  1623. {
  1624. struct tty_struct *tty = info->port.tty;
  1625. DBGBH(("%s bh_transmit\n", info->device_name));
  1626. if (tty)
  1627. tty_wakeup(tty);
  1628. }
  1629. static void dsr_change(struct slgt_info *info, unsigned short status)
  1630. {
  1631. if (status & BIT3) {
  1632. info->signals |= SerialSignal_DSR;
  1633. info->input_signal_events.dsr_up++;
  1634. } else {
  1635. info->signals &= ~SerialSignal_DSR;
  1636. info->input_signal_events.dsr_down++;
  1637. }
  1638. DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
  1639. if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
  1640. slgt_irq_off(info, IRQ_DSR);
  1641. return;
  1642. }
  1643. info->icount.dsr++;
  1644. wake_up_interruptible(&info->status_event_wait_q);
  1645. wake_up_interruptible(&info->event_wait_q);
  1646. info->pending_bh |= BH_STATUS;
  1647. }
  1648. static void cts_change(struct slgt_info *info, unsigned short status)
  1649. {
  1650. if (status & BIT2) {
  1651. info->signals |= SerialSignal_CTS;
  1652. info->input_signal_events.cts_up++;
  1653. } else {
  1654. info->signals &= ~SerialSignal_CTS;
  1655. info->input_signal_events.cts_down++;
  1656. }
  1657. DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
  1658. if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
  1659. slgt_irq_off(info, IRQ_CTS);
  1660. return;
  1661. }
  1662. info->icount.cts++;
  1663. wake_up_interruptible(&info->status_event_wait_q);
  1664. wake_up_interruptible(&info->event_wait_q);
  1665. info->pending_bh |= BH_STATUS;
  1666. if (tty_port_cts_enabled(&info->port)) {
  1667. if (info->port.tty) {
  1668. if (info->port.tty->hw_stopped) {
  1669. if (info->signals & SerialSignal_CTS) {
  1670. info->port.tty->hw_stopped = 0;
  1671. info->pending_bh |= BH_TRANSMIT;
  1672. return;
  1673. }
  1674. } else {
  1675. if (!(info->signals & SerialSignal_CTS))
  1676. info->port.tty->hw_stopped = 1;
  1677. }
  1678. }
  1679. }
  1680. }
  1681. static void dcd_change(struct slgt_info *info, unsigned short status)
  1682. {
  1683. if (status & BIT1) {
  1684. info->signals |= SerialSignal_DCD;
  1685. info->input_signal_events.dcd_up++;
  1686. } else {
  1687. info->signals &= ~SerialSignal_DCD;
  1688. info->input_signal_events.dcd_down++;
  1689. }
  1690. DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
  1691. if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
  1692. slgt_irq_off(info, IRQ_DCD);
  1693. return;
  1694. }
  1695. info->icount.dcd++;
  1696. #if SYNCLINK_GENERIC_HDLC
  1697. if (info->netcount) {
  1698. if (info->signals & SerialSignal_DCD)
  1699. netif_carrier_on(info->netdev);
  1700. else
  1701. netif_carrier_off(info->netdev);
  1702. }
  1703. #endif
  1704. wake_up_interruptible(&info->status_event_wait_q);
  1705. wake_up_interruptible(&info->event_wait_q);
  1706. info->pending_bh |= BH_STATUS;
  1707. if (tty_port_check_carrier(&info->port)) {
  1708. if (info->signals & SerialSignal_DCD)
  1709. wake_up_interruptible(&info->port.open_wait);
  1710. else {
  1711. if (info->port.tty)
  1712. tty_hangup(info->port.tty);
  1713. }
  1714. }
  1715. }
  1716. static void ri_change(struct slgt_info *info, unsigned short status)
  1717. {
  1718. if (status & BIT0) {
  1719. info->signals |= SerialSignal_RI;
  1720. info->input_signal_events.ri_up++;
  1721. } else {
  1722. info->signals &= ~SerialSignal_RI;
  1723. info->input_signal_events.ri_down++;
  1724. }
  1725. DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
  1726. if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
  1727. slgt_irq_off(info, IRQ_RI);
  1728. return;
  1729. }
  1730. info->icount.rng++;
  1731. wake_up_interruptible(&info->status_event_wait_q);
  1732. wake_up_interruptible(&info->event_wait_q);
  1733. info->pending_bh |= BH_STATUS;
  1734. }
  1735. static void isr_rxdata(struct slgt_info *info)
  1736. {
  1737. unsigned int count = info->rbuf_fill_count;
  1738. unsigned int i = info->rbuf_fill_index;
  1739. unsigned short reg;
  1740. while (rd_reg16(info, SSR) & IRQ_RXDATA) {
  1741. reg = rd_reg16(info, RDR);
  1742. DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
  1743. if (desc_complete(info->rbufs[i])) {
  1744. /* all buffers full */
  1745. rx_stop(info);
  1746. info->rx_restart = true;
  1747. continue;
  1748. }
  1749. info->rbufs[i].buf[count++] = (unsigned char)reg;
  1750. /* async mode saves status byte to buffer for each data byte */
  1751. if (info->params.mode == MGSL_MODE_ASYNC)
  1752. info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
  1753. if (count == info->rbuf_fill_level || (reg & BIT10)) {
  1754. /* buffer full or end of frame */
  1755. set_desc_count(info->rbufs[i], count);
  1756. set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
  1757. info->rbuf_fill_count = count = 0;
  1758. if (++i == info->rbuf_count)
  1759. i = 0;
  1760. info->pending_bh |= BH_RECEIVE;
  1761. }
  1762. }
  1763. info->rbuf_fill_index = i;
  1764. info->rbuf_fill_count = count;
  1765. }
  1766. static void isr_serial(struct slgt_info *info)
  1767. {
  1768. unsigned short status = rd_reg16(info, SSR);
  1769. DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
  1770. wr_reg16(info, SSR, status); /* clear pending */
  1771. info->irq_occurred = true;
  1772. if (info->params.mode == MGSL_MODE_ASYNC) {
  1773. if (status & IRQ_TXIDLE) {
  1774. if (info->tx_active)
  1775. isr_txeom(info, status);
  1776. }
  1777. if (info->rx_pio && (status & IRQ_RXDATA))
  1778. isr_rxdata(info);
  1779. if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
  1780. info->icount.brk++;
  1781. /* process break detection if tty control allows */
  1782. if (info->port.tty) {
  1783. if (!(status & info->ignore_status_mask)) {
  1784. if (info->read_status_mask & MASK_BREAK) {
  1785. tty_insert_flip_char(&info->port, 0, TTY_BREAK);
  1786. if (info->port.flags & ASYNC_SAK)
  1787. do_SAK(info->port.tty);
  1788. }
  1789. }
  1790. }
  1791. }
  1792. } else {
  1793. if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
  1794. isr_txeom(info, status);
  1795. if (info->rx_pio && (status & IRQ_RXDATA))
  1796. isr_rxdata(info);
  1797. if (status & IRQ_RXIDLE) {
  1798. if (status & RXIDLE)
  1799. info->icount.rxidle++;
  1800. else
  1801. info->icount.exithunt++;
  1802. wake_up_interruptible(&info->event_wait_q);
  1803. }
  1804. if (status & IRQ_RXOVER)
  1805. rx_start(info);
  1806. }
  1807. if (status & IRQ_DSR)
  1808. dsr_change(info, status);
  1809. if (status & IRQ_CTS)
  1810. cts_change(info, status);
  1811. if (status & IRQ_DCD)
  1812. dcd_change(info, status);
  1813. if (status & IRQ_RI)
  1814. ri_change(info, status);
  1815. }
  1816. static void isr_rdma(struct slgt_info *info)
  1817. {
  1818. unsigned int status = rd_reg32(info, RDCSR);
  1819. DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
  1820. /* RDCSR (rx DMA control/status)
  1821. *
  1822. * 31..07 reserved
  1823. * 06 save status byte to DMA buffer
  1824. * 05 error
  1825. * 04 eol (end of list)
  1826. * 03 eob (end of buffer)
  1827. * 02 IRQ enable
  1828. * 01 reset
  1829. * 00 enable
  1830. */
  1831. wr_reg32(info, RDCSR, status); /* clear pending */
  1832. if (status & (BIT5 + BIT4)) {
  1833. DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
  1834. info->rx_restart = true;
  1835. }
  1836. info->pending_bh |= BH_RECEIVE;
  1837. }
  1838. static void isr_tdma(struct slgt_info *info)
  1839. {
  1840. unsigned int status = rd_reg32(info, TDCSR);
  1841. DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
  1842. /* TDCSR (tx DMA control/status)
  1843. *
  1844. * 31..06 reserved
  1845. * 05 error
  1846. * 04 eol (end of list)
  1847. * 03 eob (end of buffer)
  1848. * 02 IRQ enable
  1849. * 01 reset
  1850. * 00 enable
  1851. */
  1852. wr_reg32(info, TDCSR, status); /* clear pending */
  1853. if (status & (BIT5 + BIT4 + BIT3)) {
  1854. // another transmit buffer has completed
  1855. // run bottom half to get more send data from user
  1856. info->pending_bh |= BH_TRANSMIT;
  1857. }
  1858. }
  1859. /*
  1860. * return true if there are unsent tx DMA buffers, otherwise false
  1861. *
  1862. * if there are unsent buffers then info->tbuf_start
  1863. * is set to index of first unsent buffer
  1864. */
  1865. static bool unsent_tbufs(struct slgt_info *info)
  1866. {
  1867. unsigned int i = info->tbuf_current;
  1868. bool rc = false;
  1869. /*
  1870. * search backwards from last loaded buffer (precedes tbuf_current)
  1871. * for first unsent buffer (desc_count > 0)
  1872. */
  1873. do {
  1874. if (i)
  1875. i--;
  1876. else
  1877. i = info->tbuf_count - 1;
  1878. if (!desc_count(info->tbufs[i]))
  1879. break;
  1880. info->tbuf_start = i;
  1881. rc = true;
  1882. } while (i != info->tbuf_current);
  1883. return rc;
  1884. }
  1885. static void isr_txeom(struct slgt_info *info, unsigned short status)
  1886. {
  1887. DBGISR(("%s txeom status=%04x\n", info->device_name, status));
  1888. slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
  1889. tdma_reset(info);
  1890. if (status & IRQ_TXUNDER) {
  1891. unsigned short val = rd_reg16(info, TCR);
  1892. wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
  1893. wr_reg16(info, TCR, val); /* clear reset bit */
  1894. }
  1895. if (info->tx_active) {
  1896. if (info->params.mode != MGSL_MODE_ASYNC) {
  1897. if (status & IRQ_TXUNDER)
  1898. info->icount.txunder++;
  1899. else if (status & IRQ_TXIDLE)
  1900. info->icount.txok++;
  1901. }
  1902. if (unsent_tbufs(info)) {
  1903. tx_start(info);
  1904. update_tx_timer(info);
  1905. return;
  1906. }
  1907. info->tx_active = false;
  1908. del_timer(&info->tx_timer);
  1909. if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
  1910. info->signals &= ~SerialSignal_RTS;
  1911. info->drop_rts_on_tx_done = false;
  1912. set_gtsignals(info);
  1913. }
  1914. #if SYNCLINK_GENERIC_HDLC
  1915. if (info->netcount)
  1916. hdlcdev_tx_done(info);
  1917. else
  1918. #endif
  1919. {
  1920. if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
  1921. tx_stop(info);
  1922. return;
  1923. }
  1924. info->pending_bh |= BH_TRANSMIT;
  1925. }
  1926. }
  1927. }
  1928. static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
  1929. {
  1930. struct cond_wait *w, *prev;
  1931. /* wake processes waiting for specific transitions */
  1932. for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
  1933. if (w->data & changed) {
  1934. w->data = state;
  1935. wake_up_interruptible(&w->q);
  1936. if (prev != NULL)
  1937. prev->next = w->next;
  1938. else
  1939. info->gpio_wait_q = w->next;
  1940. } else
  1941. prev = w;
  1942. }
  1943. }
  1944. /* interrupt service routine
  1945. *
  1946. * irq interrupt number
  1947. * dev_id device ID supplied during interrupt registration
  1948. */
  1949. static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
  1950. {
  1951. struct slgt_info *info = dev_id;
  1952. unsigned int gsr;
  1953. unsigned int i;
  1954. DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
  1955. while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
  1956. DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
  1957. info->irq_occurred = true;
  1958. for(i=0; i < info->port_count ; i++) {
  1959. if (info->port_array[i] == NULL)
  1960. continue;
  1961. spin_lock(&info->port_array[i]->lock);
  1962. if (gsr & (BIT8 << i))
  1963. isr_serial(info->port_array[i]);
  1964. if (gsr & (BIT16 << (i*2)))
  1965. isr_rdma(info->port_array[i]);
  1966. if (gsr & (BIT17 << (i*2)))
  1967. isr_tdma(info->port_array[i]);
  1968. spin_unlock(&info->port_array[i]->lock);
  1969. }
  1970. }
  1971. if (info->gpio_present) {
  1972. unsigned int state;
  1973. unsigned int changed;
  1974. spin_lock(&info->lock);
  1975. while ((changed = rd_reg32(info, IOSR)) != 0) {
  1976. DBGISR(("%s iosr=%08x\n", info->device_name, changed));
  1977. /* read latched state of GPIO signals */
  1978. state = rd_reg32(info, IOVR);
  1979. /* clear pending GPIO interrupt bits */
  1980. wr_reg32(info, IOSR, changed);
  1981. for (i=0 ; i < info->port_count ; i++) {
  1982. if (info->port_array[i] != NULL)
  1983. isr_gpio(info->port_array[i], changed, state);
  1984. }
  1985. }
  1986. spin_unlock(&info->lock);
  1987. }
  1988. for(i=0; i < info->port_count ; i++) {
  1989. struct slgt_info *port = info->port_array[i];
  1990. if (port == NULL)
  1991. continue;
  1992. spin_lock(&port->lock);
  1993. if ((port->port.count || port->netcount) &&
  1994. port->pending_bh && !port->bh_running &&
  1995. !port->bh_requested) {
  1996. DBGISR(("%s bh queued\n", port->device_name));
  1997. schedule_work(&port->task);
  1998. port->bh_requested = true;
  1999. }
  2000. spin_unlock(&port->lock);
  2001. }
  2002. DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
  2003. return IRQ_HANDLED;
  2004. }
  2005. static int startup(struct slgt_info *info)
  2006. {
  2007. DBGINFO(("%s startup\n", info->device_name));
  2008. if (tty_port_initialized(&info->port))
  2009. return 0;
  2010. if (!info->tx_buf) {
  2011. info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
  2012. if (!info->tx_buf) {
  2013. DBGERR(("%s can't allocate tx buffer\n", info->device_name));
  2014. return -ENOMEM;
  2015. }
  2016. }
  2017. info->pending_bh = 0;
  2018. memset(&info->icount, 0, sizeof(info->icount));
  2019. /* program hardware for current parameters */
  2020. change_params(info);
  2021. if (info->port.tty)
  2022. clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
  2023. tty_port_set_initialized(&info->port, 1);
  2024. return 0;
  2025. }
  2026. /*
  2027. * called by close() and hangup() to shutdown hardware
  2028. */
  2029. static void shutdown(struct slgt_info *info)
  2030. {
  2031. unsigned long flags;
  2032. if (!tty_port_initialized(&info->port))
  2033. return;
  2034. DBGINFO(("%s shutdown\n", info->device_name));
  2035. /* clear status wait queue because status changes */
  2036. /* can't happen after shutting down the hardware */
  2037. wake_up_interruptible(&info->status_event_wait_q);
  2038. wake_up_interruptible(&info->event_wait_q);
  2039. del_timer_sync(&info->tx_timer);
  2040. del_timer_sync(&info->rx_timer);
  2041. kfree(info->tx_buf);
  2042. info->tx_buf = NULL;
  2043. spin_lock_irqsave(&info->lock,flags);
  2044. tx_stop(info);
  2045. rx_stop(info);
  2046. slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
  2047. if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
  2048. info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
  2049. set_gtsignals(info);
  2050. }
  2051. flush_cond_wait(&info->gpio_wait_q);
  2052. spin_unlock_irqrestore(&info->lock,flags);
  2053. if (info->port.tty)
  2054. set_bit(TTY_IO_ERROR, &info->port.tty->flags);
  2055. tty_port_set_initialized(&info->port, 0);
  2056. }
  2057. static void program_hw(struct slgt_info *info)
  2058. {
  2059. unsigned long flags;
  2060. spin_lock_irqsave(&info->lock,flags);
  2061. rx_stop(info);
  2062. tx_stop(info);
  2063. if (info->params.mode != MGSL_MODE_ASYNC ||
  2064. info->netcount)
  2065. sync_mode(info);
  2066. else
  2067. async_mode(info);
  2068. set_gtsignals(info);
  2069. info->dcd_chkcount = 0;
  2070. info->cts_chkcount = 0;
  2071. info->ri_chkcount = 0;
  2072. info->dsr_chkcount = 0;
  2073. slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
  2074. get_gtsignals(info);
  2075. if (info->netcount ||
  2076. (info->port.tty && info->port.tty->termios.c_cflag & CREAD))
  2077. rx_start(info);
  2078. spin_unlock_irqrestore(&info->lock,flags);
  2079. }
  2080. /*
  2081. * reconfigure adapter based on new parameters
  2082. */
  2083. static void change_params(struct slgt_info *info)
  2084. {
  2085. unsigned cflag;
  2086. int bits_per_char;
  2087. if (!info->port.tty)
  2088. return;
  2089. DBGINFO(("%s change_params\n", info->device_name));
  2090. cflag = info->port.tty->termios.c_cflag;
  2091. /* if B0 rate (hangup) specified then negate RTS and DTR */
  2092. /* otherwise assert RTS and DTR */
  2093. if (cflag & CBAUD)
  2094. info->signals |= SerialSignal_RTS | SerialSignal_DTR;
  2095. else
  2096. info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
  2097. /* byte size and parity */
  2098. switch (cflag & CSIZE) {
  2099. case CS5: info->params.data_bits = 5; break;
  2100. case CS6: info->params.data_bits = 6; break;
  2101. case CS7: info->params.data_bits = 7; break;
  2102. case CS8: info->params.data_bits = 8; break;
  2103. default: info->params.data_bits = 7; break;
  2104. }
  2105. info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
  2106. if (cflag & PARENB)
  2107. info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
  2108. else
  2109. info->params.parity = ASYNC_PARITY_NONE;
  2110. /* calculate number of jiffies to transmit a full
  2111. * FIFO (32 bytes) at specified data rate
  2112. */
  2113. bits_per_char = info->params.data_bits +
  2114. info->params.stop_bits + 1;
  2115. info->params.data_rate = tty_get_baud_rate(info->port.tty);
  2116. if (info->params.data_rate) {
  2117. info->timeout = (32*HZ*bits_per_char) /
  2118. info->params.data_rate;
  2119. }
  2120. info->timeout += HZ/50; /* Add .02 seconds of slop */
  2121. tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
  2122. tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
  2123. /* process tty input control flags */
  2124. info->read_status_mask = IRQ_RXOVER;
  2125. if (I_INPCK(info->port.tty))
  2126. info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
  2127. if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
  2128. info->read_status_mask |= MASK_BREAK;
  2129. if (I_IGNPAR(info->port.tty))
  2130. info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
  2131. if (I_IGNBRK(info->port.tty)) {
  2132. info->ignore_status_mask |= MASK_BREAK;
  2133. /* If ignoring parity and break indicators, ignore
  2134. * overruns too. (For real raw support).
  2135. */
  2136. if (I_IGNPAR(info->port.tty))
  2137. info->ignore_status_mask |= MASK_OVERRUN;
  2138. }
  2139. program_hw(info);
  2140. }
  2141. static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
  2142. {
  2143. DBGINFO(("%s get_stats\n", info->device_name));
  2144. if (!user_icount) {
  2145. memset(&info->icount, 0, sizeof(info->icount));
  2146. } else {
  2147. if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
  2148. return -EFAULT;
  2149. }
  2150. return 0;
  2151. }
  2152. static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
  2153. {
  2154. DBGINFO(("%s get_params\n", info->device_name));
  2155. if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
  2156. return -EFAULT;
  2157. return 0;
  2158. }
  2159. static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
  2160. {
  2161. unsigned long flags;
  2162. MGSL_PARAMS tmp_params;
  2163. DBGINFO(("%s set_params\n", info->device_name));
  2164. if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
  2165. return -EFAULT;
  2166. spin_lock_irqsave(&info->lock, flags);
  2167. if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
  2168. info->base_clock = tmp_params.clock_speed;
  2169. else
  2170. memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
  2171. spin_unlock_irqrestore(&info->lock, flags);
  2172. program_hw(info);
  2173. return 0;
  2174. }
  2175. static int get_txidle(struct slgt_info *info, int __user *idle_mode)
  2176. {
  2177. DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
  2178. if (put_user(info->idle_mode, idle_mode))
  2179. return -EFAULT;
  2180. return 0;
  2181. }
  2182. static int set_txidle(struct slgt_info *info, int idle_mode)
  2183. {
  2184. unsigned long flags;
  2185. DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
  2186. spin_lock_irqsave(&info->lock,flags);
  2187. info->idle_mode = idle_mode;
  2188. if (info->params.mode != MGSL_MODE_ASYNC)
  2189. tx_set_idle(info);
  2190. spin_unlock_irqrestore(&info->lock,flags);
  2191. return 0;
  2192. }
  2193. static int tx_enable(struct slgt_info *info, int enable)
  2194. {
  2195. unsigned long flags;
  2196. DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
  2197. spin_lock_irqsave(&info->lock,flags);
  2198. if (enable) {
  2199. if (!info->tx_enabled)
  2200. tx_start(info);
  2201. } else {
  2202. if (info->tx_enabled)
  2203. tx_stop(info);
  2204. }
  2205. spin_unlock_irqrestore(&info->lock,flags);
  2206. return 0;
  2207. }
  2208. /*
  2209. * abort transmit HDLC frame
  2210. */
  2211. static int tx_abort(struct slgt_info *info)
  2212. {
  2213. unsigned long flags;
  2214. DBGINFO(("%s tx_abort\n", info->device_name));
  2215. spin_lock_irqsave(&info->lock,flags);
  2216. tdma_reset(info);
  2217. spin_unlock_irqrestore(&info->lock,flags);
  2218. return 0;
  2219. }
  2220. static int rx_enable(struct slgt_info *info, int enable)
  2221. {
  2222. unsigned long flags;
  2223. unsigned int rbuf_fill_level;
  2224. DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
  2225. spin_lock_irqsave(&info->lock,flags);
  2226. /*
  2227. * enable[31..16] = receive DMA buffer fill level
  2228. * 0 = noop (leave fill level unchanged)
  2229. * fill level must be multiple of 4 and <= buffer size
  2230. */
  2231. rbuf_fill_level = ((unsigned int)enable) >> 16;
  2232. if (rbuf_fill_level) {
  2233. if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
  2234. spin_unlock_irqrestore(&info->lock, flags);
  2235. return -EINVAL;
  2236. }
  2237. info->rbuf_fill_level = rbuf_fill_level;
  2238. if (rbuf_fill_level < 128)
  2239. info->rx_pio = 1; /* PIO mode */
  2240. else
  2241. info->rx_pio = 0; /* DMA mode */
  2242. rx_stop(info); /* restart receiver to use new fill level */
  2243. }
  2244. /*
  2245. * enable[1..0] = receiver enable command
  2246. * 0 = disable
  2247. * 1 = enable
  2248. * 2 = enable or force hunt mode if already enabled
  2249. */
  2250. enable &= 3;
  2251. if (enable) {
  2252. if (!info->rx_enabled)
  2253. rx_start(info);
  2254. else if (enable == 2) {
  2255. /* force hunt mode (write 1 to RCR[3]) */
  2256. wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
  2257. }
  2258. } else {
  2259. if (info->rx_enabled)
  2260. rx_stop(info);
  2261. }
  2262. spin_unlock_irqrestore(&info->lock,flags);
  2263. return 0;
  2264. }
  2265. /*
  2266. * wait for specified event to occur
  2267. */
  2268. static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
  2269. {
  2270. unsigned long flags;
  2271. int s;
  2272. int rc=0;
  2273. struct mgsl_icount cprev, cnow;
  2274. int events;
  2275. int mask;
  2276. struct _input_signal_events oldsigs, newsigs;
  2277. DECLARE_WAITQUEUE(wait, current);
  2278. if (get_user(mask, mask_ptr))
  2279. return -EFAULT;
  2280. DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
  2281. spin_lock_irqsave(&info->lock,flags);
  2282. /* return immediately if state matches requested events */
  2283. get_gtsignals(info);
  2284. s = info->signals;
  2285. events = mask &
  2286. ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
  2287. ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
  2288. ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
  2289. ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
  2290. if (events) {
  2291. spin_unlock_irqrestore(&info->lock,flags);
  2292. goto exit;
  2293. }
  2294. /* save current irq counts */
  2295. cprev = info->icount;
  2296. oldsigs = info->input_signal_events;
  2297. /* enable hunt and idle irqs if needed */
  2298. if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
  2299. unsigned short val = rd_reg16(info, SCR);
  2300. if (!(val & IRQ_RXIDLE))
  2301. wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
  2302. }
  2303. set_current_state(TASK_INTERRUPTIBLE);
  2304. add_wait_queue(&info->event_wait_q, &wait);
  2305. spin_unlock_irqrestore(&info->lock,flags);
  2306. for(;;) {
  2307. schedule();
  2308. if (signal_pending(current)) {
  2309. rc = -ERESTARTSYS;
  2310. break;
  2311. }
  2312. /* get current irq counts */
  2313. spin_lock_irqsave(&info->lock,flags);
  2314. cnow = info->icount;
  2315. newsigs = info->input_signal_events;
  2316. set_current_state(TASK_INTERRUPTIBLE);
  2317. spin_unlock_irqrestore(&info->lock,flags);
  2318. /* if no change, wait aborted for some reason */
  2319. if (newsigs.dsr_up == oldsigs.dsr_up &&
  2320. newsigs.dsr_down == oldsigs.dsr_down &&
  2321. newsigs.dcd_up == oldsigs.dcd_up &&
  2322. newsigs.dcd_down == oldsigs.dcd_down &&
  2323. newsigs.cts_up == oldsigs.cts_up &&
  2324. newsigs.cts_down == oldsigs.cts_down &&
  2325. newsigs.ri_up == oldsigs.ri_up &&
  2326. newsigs.ri_down == oldsigs.ri_down &&
  2327. cnow.exithunt == cprev.exithunt &&
  2328. cnow.rxidle == cprev.rxidle) {
  2329. rc = -EIO;
  2330. break;
  2331. }
  2332. events = mask &
  2333. ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
  2334. (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
  2335. (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
  2336. (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
  2337. (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
  2338. (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
  2339. (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
  2340. (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
  2341. (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
  2342. (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
  2343. if (events)
  2344. break;
  2345. cprev = cnow;
  2346. oldsigs = newsigs;
  2347. }
  2348. remove_wait_queue(&info->event_wait_q, &wait);
  2349. set_current_state(TASK_RUNNING);
  2350. if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
  2351. spin_lock_irqsave(&info->lock,flags);
  2352. if (!waitqueue_active(&info->event_wait_q)) {
  2353. /* disable enable exit hunt mode/idle rcvd IRQs */
  2354. wr_reg16(info, SCR,
  2355. (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
  2356. }
  2357. spin_unlock_irqrestore(&info->lock,flags);
  2358. }
  2359. exit:
  2360. if (rc == 0)
  2361. rc = put_user(events, mask_ptr);
  2362. return rc;
  2363. }
  2364. static int get_interface(struct slgt_info *info, int __user *if_mode)
  2365. {
  2366. DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
  2367. if (put_user(info->if_mode, if_mode))
  2368. return -EFAULT;
  2369. return 0;
  2370. }
  2371. static int set_interface(struct slgt_info *info, int if_mode)
  2372. {
  2373. unsigned long flags;
  2374. unsigned short val;
  2375. DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
  2376. spin_lock_irqsave(&info->lock,flags);
  2377. info->if_mode = if_mode;
  2378. msc_set_vcr(info);
  2379. /* TCR (tx control) 07 1=RTS driver control */
  2380. val = rd_reg16(info, TCR);
  2381. if (info->if_mode & MGSL_INTERFACE_RTS_EN)
  2382. val |= BIT7;
  2383. else
  2384. val &= ~BIT7;
  2385. wr_reg16(info, TCR, val);
  2386. spin_unlock_irqrestore(&info->lock,flags);
  2387. return 0;
  2388. }
  2389. static int get_xsync(struct slgt_info *info, int __user *xsync)
  2390. {
  2391. DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync));
  2392. if (put_user(info->xsync, xsync))
  2393. return -EFAULT;
  2394. return 0;
  2395. }
  2396. /*
  2397. * set extended sync pattern (1 to 4 bytes) for extended sync mode
  2398. *
  2399. * sync pattern is contained in least significant bytes of value
  2400. * most significant byte of sync pattern is oldest (1st sent/detected)
  2401. */
  2402. static int set_xsync(struct slgt_info *info, int xsync)
  2403. {
  2404. unsigned long flags;
  2405. DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync));
  2406. spin_lock_irqsave(&info->lock, flags);
  2407. info->xsync = xsync;
  2408. wr_reg32(info, XSR, xsync);
  2409. spin_unlock_irqrestore(&info->lock, flags);
  2410. return 0;
  2411. }
  2412. static int get_xctrl(struct slgt_info *info, int __user *xctrl)
  2413. {
  2414. DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl));
  2415. if (put_user(info->xctrl, xctrl))
  2416. return -EFAULT;
  2417. return 0;
  2418. }
  2419. /*
  2420. * set extended control options
  2421. *
  2422. * xctrl[31:19] reserved, must be zero
  2423. * xctrl[18:17] extended sync pattern length in bytes
  2424. * 00 = 1 byte in xsr[7:0]
  2425. * 01 = 2 bytes in xsr[15:0]
  2426. * 10 = 3 bytes in xsr[23:0]
  2427. * 11 = 4 bytes in xsr[31:0]
  2428. * xctrl[16] 1 = enable terminal count, 0=disabled
  2429. * xctrl[15:0] receive terminal count for fixed length packets
  2430. * value is count minus one (0 = 1 byte packet)
  2431. * when terminal count is reached, receiver
  2432. * automatically returns to hunt mode and receive
  2433. * FIFO contents are flushed to DMA buffers with
  2434. * end of frame (EOF) status
  2435. */
  2436. static int set_xctrl(struct slgt_info *info, int xctrl)
  2437. {
  2438. unsigned long flags;
  2439. DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl));
  2440. spin_lock_irqsave(&info->lock, flags);
  2441. info->xctrl = xctrl;
  2442. wr_reg32(info, XCR, xctrl);
  2443. spin_unlock_irqrestore(&info->lock, flags);
  2444. return 0;
  2445. }
  2446. /*
  2447. * set general purpose IO pin state and direction
  2448. *
  2449. * user_gpio fields:
  2450. * state each bit indicates a pin state
  2451. * smask set bit indicates pin state to set
  2452. * dir each bit indicates a pin direction (0=input, 1=output)
  2453. * dmask set bit indicates pin direction to set
  2454. */
  2455. static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
  2456. {
  2457. unsigned long flags;
  2458. struct gpio_desc gpio;
  2459. __u32 data;
  2460. if (!info->gpio_present)
  2461. return -EINVAL;
  2462. if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
  2463. return -EFAULT;
  2464. DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
  2465. info->device_name, gpio.state, gpio.smask,
  2466. gpio.dir, gpio.dmask));
  2467. spin_lock_irqsave(&info->port_array[0]->lock, flags);
  2468. if (gpio.dmask) {
  2469. data = rd_reg32(info, IODR);
  2470. data |= gpio.dmask & gpio.dir;
  2471. data &= ~(gpio.dmask & ~gpio.dir);
  2472. wr_reg32(info, IODR, data);
  2473. }
  2474. if (gpio.smask) {
  2475. data = rd_reg32(info, IOVR);
  2476. data |= gpio.smask & gpio.state;
  2477. data &= ~(gpio.smask & ~gpio.state);
  2478. wr_reg32(info, IOVR, data);
  2479. }
  2480. spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
  2481. return 0;
  2482. }
  2483. /*
  2484. * get general purpose IO pin state and direction
  2485. */
  2486. static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
  2487. {
  2488. struct gpio_desc gpio;
  2489. if (!info->gpio_present)
  2490. return -EINVAL;
  2491. gpio.state = rd_reg32(info, IOVR);
  2492. gpio.smask = 0xffffffff;
  2493. gpio.dir = rd_reg32(info, IODR);
  2494. gpio.dmask = 0xffffffff;
  2495. if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
  2496. return -EFAULT;
  2497. DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
  2498. info->device_name, gpio.state, gpio.dir));
  2499. return 0;
  2500. }
  2501. /*
  2502. * conditional wait facility
  2503. */
  2504. static void init_cond_wait(struct cond_wait *w, unsigned int data)
  2505. {
  2506. init_waitqueue_head(&w->q);
  2507. init_waitqueue_entry(&w->wait, current);
  2508. w->data = data;
  2509. }
  2510. static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
  2511. {
  2512. set_current_state(TASK_INTERRUPTIBLE);
  2513. add_wait_queue(&w->q, &w->wait);
  2514. w->next = *head;
  2515. *head = w;
  2516. }
  2517. static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
  2518. {
  2519. struct cond_wait *w, *prev;
  2520. remove_wait_queue(&cw->q, &cw->wait);
  2521. set_current_state(TASK_RUNNING);
  2522. for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
  2523. if (w == cw) {
  2524. if (prev != NULL)
  2525. prev->next = w->next;
  2526. else
  2527. *head = w->next;
  2528. break;
  2529. }
  2530. }
  2531. }
  2532. static void flush_cond_wait(struct cond_wait **head)
  2533. {
  2534. while (*head != NULL) {
  2535. wake_up_interruptible(&(*head)->q);
  2536. *head = (*head)->next;
  2537. }
  2538. }
  2539. /*
  2540. * wait for general purpose I/O pin(s) to enter specified state
  2541. *
  2542. * user_gpio fields:
  2543. * state - bit indicates target pin state
  2544. * smask - set bit indicates watched pin
  2545. *
  2546. * The wait ends when at least one watched pin enters the specified
  2547. * state. When 0 (no error) is returned, user_gpio->state is set to the
  2548. * state of all GPIO pins when the wait ends.
  2549. *
  2550. * Note: Each pin may be a dedicated input, dedicated output, or
  2551. * configurable input/output. The number and configuration of pins
  2552. * varies with the specific adapter model. Only input pins (dedicated
  2553. * or configured) can be monitored with this function.
  2554. */
  2555. static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
  2556. {
  2557. unsigned long flags;
  2558. int rc = 0;
  2559. struct gpio_desc gpio;
  2560. struct cond_wait wait;
  2561. u32 state;
  2562. if (!info->gpio_present)
  2563. return -EINVAL;
  2564. if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
  2565. return -EFAULT;
  2566. DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
  2567. info->device_name, gpio.state, gpio.smask));
  2568. /* ignore output pins identified by set IODR bit */
  2569. if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
  2570. return -EINVAL;
  2571. init_cond_wait(&wait, gpio.smask);
  2572. spin_lock_irqsave(&info->port_array[0]->lock, flags);
  2573. /* enable interrupts for watched pins */
  2574. wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
  2575. /* get current pin states */
  2576. state = rd_reg32(info, IOVR);
  2577. if (gpio.smask & ~(state ^ gpio.state)) {
  2578. /* already in target state */
  2579. gpio.state = state;
  2580. } else {
  2581. /* wait for target state */
  2582. add_cond_wait(&info->gpio_wait_q, &wait);
  2583. spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
  2584. schedule();
  2585. if (signal_pending(current))
  2586. rc = -ERESTARTSYS;
  2587. else
  2588. gpio.state = wait.data;
  2589. spin_lock_irqsave(&info->port_array[0]->lock, flags);
  2590. remove_cond_wait(&info->gpio_wait_q, &wait);
  2591. }
  2592. /* disable all GPIO interrupts if no waiting processes */
  2593. if (info->gpio_wait_q == NULL)
  2594. wr_reg32(info, IOER, 0);
  2595. spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
  2596. if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
  2597. rc = -EFAULT;
  2598. return rc;
  2599. }
  2600. static int modem_input_wait(struct slgt_info *info,int arg)
  2601. {
  2602. unsigned long flags;
  2603. int rc;
  2604. struct mgsl_icount cprev, cnow;
  2605. DECLARE_WAITQUEUE(wait, current);
  2606. /* save current irq counts */
  2607. spin_lock_irqsave(&info->lock,flags);
  2608. cprev = info->icount;
  2609. add_wait_queue(&info->status_event_wait_q, &wait);
  2610. set_current_state(TASK_INTERRUPTIBLE);
  2611. spin_unlock_irqrestore(&info->lock,flags);
  2612. for(;;) {
  2613. schedule();
  2614. if (signal_pending(current)) {
  2615. rc = -ERESTARTSYS;
  2616. break;
  2617. }
  2618. /* get new irq counts */
  2619. spin_lock_irqsave(&info->lock,flags);
  2620. cnow = info->icount;
  2621. set_current_state(TASK_INTERRUPTIBLE);
  2622. spin_unlock_irqrestore(&info->lock,flags);
  2623. /* if no change, wait aborted for some reason */
  2624. if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
  2625. cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
  2626. rc = -EIO;
  2627. break;
  2628. }
  2629. /* check for change in caller specified modem input */
  2630. if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
  2631. (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
  2632. (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
  2633. (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
  2634. rc = 0;
  2635. break;
  2636. }
  2637. cprev = cnow;
  2638. }
  2639. remove_wait_queue(&info->status_event_wait_q, &wait);
  2640. set_current_state(TASK_RUNNING);
  2641. return rc;
  2642. }
  2643. /*
  2644. * return state of serial control and status signals
  2645. */
  2646. static int tiocmget(struct tty_struct *tty)
  2647. {
  2648. struct slgt_info *info = tty->driver_data;
  2649. unsigned int result;
  2650. unsigned long flags;
  2651. spin_lock_irqsave(&info->lock,flags);
  2652. get_gtsignals(info);
  2653. spin_unlock_irqrestore(&info->lock,flags);
  2654. result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
  2655. ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
  2656. ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
  2657. ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) +
  2658. ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
  2659. ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
  2660. DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
  2661. return result;
  2662. }
  2663. /*
  2664. * set modem control signals (DTR/RTS)
  2665. *
  2666. * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
  2667. * TIOCMSET = set/clear signal values
  2668. * value bit mask for command
  2669. */
  2670. static int tiocmset(struct tty_struct *tty,
  2671. unsigned int set, unsigned int clear)
  2672. {
  2673. struct slgt_info *info = tty->driver_data;
  2674. unsigned long flags;
  2675. DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
  2676. if (set & TIOCM_RTS)
  2677. info->signals |= SerialSignal_RTS;
  2678. if (set & TIOCM_DTR)
  2679. info->signals |= SerialSignal_DTR;
  2680. if (clear & TIOCM_RTS)
  2681. info->signals &= ~SerialSignal_RTS;
  2682. if (clear & TIOCM_DTR)
  2683. info->signals &= ~SerialSignal_DTR;
  2684. spin_lock_irqsave(&info->lock,flags);
  2685. set_gtsignals(info);
  2686. spin_unlock_irqrestore(&info->lock,flags);
  2687. return 0;
  2688. }
  2689. static int carrier_raised(struct tty_port *port)
  2690. {
  2691. unsigned long flags;
  2692. struct slgt_info *info = container_of(port, struct slgt_info, port);
  2693. spin_lock_irqsave(&info->lock,flags);
  2694. get_gtsignals(info);
  2695. spin_unlock_irqrestore(&info->lock,flags);
  2696. return (info->signals & SerialSignal_DCD) ? 1 : 0;
  2697. }
  2698. static void dtr_rts(struct tty_port *port, int on)
  2699. {
  2700. unsigned long flags;
  2701. struct slgt_info *info = container_of(port, struct slgt_info, port);
  2702. spin_lock_irqsave(&info->lock,flags);
  2703. if (on)
  2704. info->signals |= SerialSignal_RTS | SerialSignal_DTR;
  2705. else
  2706. info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
  2707. set_gtsignals(info);
  2708. spin_unlock_irqrestore(&info->lock,flags);
  2709. }
  2710. /*
  2711. * block current process until the device is ready to open
  2712. */
  2713. static int block_til_ready(struct tty_struct *tty, struct file *filp,
  2714. struct slgt_info *info)
  2715. {
  2716. DECLARE_WAITQUEUE(wait, current);
  2717. int retval;
  2718. bool do_clocal = false;
  2719. unsigned long flags;
  2720. int cd;
  2721. struct tty_port *port = &info->port;
  2722. DBGINFO(("%s block_til_ready\n", tty->driver->name));
  2723. if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) {
  2724. /* nonblock mode is set or port is not enabled */
  2725. tty_port_set_active(port, 1);
  2726. return 0;
  2727. }
  2728. if (C_CLOCAL(tty))
  2729. do_clocal = true;
  2730. /* Wait for carrier detect and the line to become
  2731. * free (i.e., not in use by the callout). While we are in
  2732. * this loop, port->count is dropped by one, so that
  2733. * close() knows when to free things. We restore it upon
  2734. * exit, either normal or abnormal.
  2735. */
  2736. retval = 0;
  2737. add_wait_queue(&port->open_wait, &wait);
  2738. spin_lock_irqsave(&info->lock, flags);
  2739. port->count--;
  2740. spin_unlock_irqrestore(&info->lock, flags);
  2741. port->blocked_open++;
  2742. while (1) {
  2743. if (C_BAUD(tty) && tty_port_initialized(port))
  2744. tty_port_raise_dtr_rts(port);
  2745. set_current_state(TASK_INTERRUPTIBLE);
  2746. if (tty_hung_up_p(filp) || !tty_port_initialized(port)) {
  2747. retval = (port->flags & ASYNC_HUP_NOTIFY) ?
  2748. -EAGAIN : -ERESTARTSYS;
  2749. break;
  2750. }
  2751. cd = tty_port_carrier_raised(port);
  2752. if (do_clocal || cd)
  2753. break;
  2754. if (signal_pending(current)) {
  2755. retval = -ERESTARTSYS;
  2756. break;
  2757. }
  2758. DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
  2759. tty_unlock(tty);
  2760. schedule();
  2761. tty_lock(tty);
  2762. }
  2763. set_current_state(TASK_RUNNING);
  2764. remove_wait_queue(&port->open_wait, &wait);
  2765. if (!tty_hung_up_p(filp))
  2766. port->count++;
  2767. port->blocked_open--;
  2768. if (!retval)
  2769. tty_port_set_active(port, 1);
  2770. DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
  2771. return retval;
  2772. }
  2773. /*
  2774. * allocate buffers used for calling line discipline receive_buf
  2775. * directly in synchronous mode
  2776. * note: add 5 bytes to max frame size to allow appending
  2777. * 32-bit CRC and status byte when configured to do so
  2778. */
  2779. static int alloc_tmp_rbuf(struct slgt_info *info)
  2780. {
  2781. info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
  2782. if (info->tmp_rbuf == NULL)
  2783. return -ENOMEM;
  2784. /* unused flag buffer to satisfy receive_buf calling interface */
  2785. info->flag_buf = kzalloc(info->max_frame_size + 5, GFP_KERNEL);
  2786. if (!info->flag_buf) {
  2787. kfree(info->tmp_rbuf);
  2788. info->tmp_rbuf = NULL;
  2789. return -ENOMEM;
  2790. }
  2791. return 0;
  2792. }
  2793. static void free_tmp_rbuf(struct slgt_info *info)
  2794. {
  2795. kfree(info->tmp_rbuf);
  2796. info->tmp_rbuf = NULL;
  2797. kfree(info->flag_buf);
  2798. info->flag_buf = NULL;
  2799. }
  2800. /*
  2801. * allocate DMA descriptor lists.
  2802. */
  2803. static int alloc_desc(struct slgt_info *info)
  2804. {
  2805. unsigned int i;
  2806. unsigned int pbufs;
  2807. /* allocate memory to hold descriptor lists */
  2808. info->bufs = dma_alloc_coherent(&info->pdev->dev, DESC_LIST_SIZE,
  2809. &info->bufs_dma_addr, GFP_KERNEL);
  2810. if (info->bufs == NULL)
  2811. return -ENOMEM;
  2812. info->rbufs = (struct slgt_desc*)info->bufs;
  2813. info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
  2814. pbufs = (unsigned int)info->bufs_dma_addr;
  2815. /*
  2816. * Build circular lists of descriptors
  2817. */
  2818. for (i=0; i < info->rbuf_count; i++) {
  2819. /* physical address of this descriptor */
  2820. info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
  2821. /* physical address of next descriptor */
  2822. if (i == info->rbuf_count - 1)
  2823. info->rbufs[i].next = cpu_to_le32(pbufs);
  2824. else
  2825. info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
  2826. set_desc_count(info->rbufs[i], DMABUFSIZE);
  2827. }
  2828. for (i=0; i < info->tbuf_count; i++) {
  2829. /* physical address of this descriptor */
  2830. info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
  2831. /* physical address of next descriptor */
  2832. if (i == info->tbuf_count - 1)
  2833. info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
  2834. else
  2835. info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
  2836. }
  2837. return 0;
  2838. }
  2839. static void free_desc(struct slgt_info *info)
  2840. {
  2841. if (info->bufs != NULL) {
  2842. dma_free_coherent(&info->pdev->dev, DESC_LIST_SIZE,
  2843. info->bufs, info->bufs_dma_addr);
  2844. info->bufs = NULL;
  2845. info->rbufs = NULL;
  2846. info->tbufs = NULL;
  2847. }
  2848. }
  2849. static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
  2850. {
  2851. int i;
  2852. for (i=0; i < count; i++) {
  2853. bufs[i].buf = dma_alloc_coherent(&info->pdev->dev, DMABUFSIZE,
  2854. &bufs[i].buf_dma_addr, GFP_KERNEL);
  2855. if (!bufs[i].buf)
  2856. return -ENOMEM;
  2857. bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
  2858. }
  2859. return 0;
  2860. }
  2861. static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
  2862. {
  2863. int i;
  2864. for (i=0; i < count; i++) {
  2865. if (bufs[i].buf == NULL)
  2866. continue;
  2867. dma_free_coherent(&info->pdev->dev, DMABUFSIZE, bufs[i].buf,
  2868. bufs[i].buf_dma_addr);
  2869. bufs[i].buf = NULL;
  2870. }
  2871. }
  2872. static int alloc_dma_bufs(struct slgt_info *info)
  2873. {
  2874. info->rbuf_count = 32;
  2875. info->tbuf_count = 32;
  2876. if (alloc_desc(info) < 0 ||
  2877. alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
  2878. alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
  2879. alloc_tmp_rbuf(info) < 0) {
  2880. DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
  2881. return -ENOMEM;
  2882. }
  2883. reset_rbufs(info);
  2884. return 0;
  2885. }
  2886. static void free_dma_bufs(struct slgt_info *info)
  2887. {
  2888. if (info->bufs) {
  2889. free_bufs(info, info->rbufs, info->rbuf_count);
  2890. free_bufs(info, info->tbufs, info->tbuf_count);
  2891. free_desc(info);
  2892. }
  2893. free_tmp_rbuf(info);
  2894. }
  2895. static int claim_resources(struct slgt_info *info)
  2896. {
  2897. if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
  2898. DBGERR(("%s reg addr conflict, addr=%08X\n",
  2899. info->device_name, info->phys_reg_addr));
  2900. info->init_error = DiagStatus_AddressConflict;
  2901. goto errout;
  2902. }
  2903. else
  2904. info->reg_addr_requested = true;
  2905. info->reg_addr = ioremap(info->phys_reg_addr, SLGT_REG_SIZE);
  2906. if (!info->reg_addr) {
  2907. DBGERR(("%s can't map device registers, addr=%08X\n",
  2908. info->device_name, info->phys_reg_addr));
  2909. info->init_error = DiagStatus_CantAssignPciResources;
  2910. goto errout;
  2911. }
  2912. return 0;
  2913. errout:
  2914. release_resources(info);
  2915. return -ENODEV;
  2916. }
  2917. static void release_resources(struct slgt_info *info)
  2918. {
  2919. if (info->irq_requested) {
  2920. free_irq(info->irq_level, info);
  2921. info->irq_requested = false;
  2922. }
  2923. if (info->reg_addr_requested) {
  2924. release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
  2925. info->reg_addr_requested = false;
  2926. }
  2927. if (info->reg_addr) {
  2928. iounmap(info->reg_addr);
  2929. info->reg_addr = NULL;
  2930. }
  2931. }
  2932. /* Add the specified device instance data structure to the
  2933. * global linked list of devices and increment the device count.
  2934. */
  2935. static void add_device(struct slgt_info *info)
  2936. {
  2937. char *devstr;
  2938. info->next_device = NULL;
  2939. info->line = slgt_device_count;
  2940. sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
  2941. if (info->line < MAX_DEVICES) {
  2942. if (maxframe[info->line])
  2943. info->max_frame_size = maxframe[info->line];
  2944. }
  2945. slgt_device_count++;
  2946. if (!slgt_device_list)
  2947. slgt_device_list = info;
  2948. else {
  2949. struct slgt_info *current_dev = slgt_device_list;
  2950. while(current_dev->next_device)
  2951. current_dev = current_dev->next_device;
  2952. current_dev->next_device = info;
  2953. }
  2954. if (info->max_frame_size < 4096)
  2955. info->max_frame_size = 4096;
  2956. else if (info->max_frame_size > 65535)
  2957. info->max_frame_size = 65535;
  2958. switch(info->pdev->device) {
  2959. case SYNCLINK_GT_DEVICE_ID:
  2960. devstr = "GT";
  2961. break;
  2962. case SYNCLINK_GT2_DEVICE_ID:
  2963. devstr = "GT2";
  2964. break;
  2965. case SYNCLINK_GT4_DEVICE_ID:
  2966. devstr = "GT4";
  2967. break;
  2968. case SYNCLINK_AC_DEVICE_ID:
  2969. devstr = "AC";
  2970. info->params.mode = MGSL_MODE_ASYNC;
  2971. break;
  2972. default:
  2973. devstr = "(unknown model)";
  2974. }
  2975. printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
  2976. devstr, info->device_name, info->phys_reg_addr,
  2977. info->irq_level, info->max_frame_size);
  2978. #if SYNCLINK_GENERIC_HDLC
  2979. hdlcdev_init(info);
  2980. #endif
  2981. }
  2982. static const struct tty_port_operations slgt_port_ops = {
  2983. .carrier_raised = carrier_raised,
  2984. .dtr_rts = dtr_rts,
  2985. };
  2986. /*
  2987. * allocate device instance structure, return NULL on failure
  2988. */
  2989. static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
  2990. {
  2991. struct slgt_info *info;
  2992. info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
  2993. if (!info) {
  2994. DBGERR(("%s device alloc failed adapter=%d port=%d\n",
  2995. driver_name, adapter_num, port_num));
  2996. } else {
  2997. tty_port_init(&info->port);
  2998. info->port.ops = &slgt_port_ops;
  2999. info->magic = MGSL_MAGIC;
  3000. INIT_WORK(&info->task, bh_handler);
  3001. info->max_frame_size = 4096;
  3002. info->base_clock = 14745600;
  3003. info->rbuf_fill_level = DMABUFSIZE;
  3004. info->port.close_delay = 5*HZ/10;
  3005. info->port.closing_wait = 30*HZ;
  3006. init_waitqueue_head(&info->status_event_wait_q);
  3007. init_waitqueue_head(&info->event_wait_q);
  3008. spin_lock_init(&info->netlock);
  3009. memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
  3010. info->idle_mode = HDLC_TXIDLE_FLAGS;
  3011. info->adapter_num = adapter_num;
  3012. info->port_num = port_num;
  3013. timer_setup(&info->tx_timer, tx_timeout, 0);
  3014. timer_setup(&info->rx_timer, rx_timeout, 0);
  3015. /* Copy configuration info to device instance data */
  3016. info->pdev = pdev;
  3017. info->irq_level = pdev->irq;
  3018. info->phys_reg_addr = pci_resource_start(pdev,0);
  3019. info->bus_type = MGSL_BUS_TYPE_PCI;
  3020. info->irq_flags = IRQF_SHARED;
  3021. info->init_error = -1; /* assume error, set to 0 on successful init */
  3022. }
  3023. return info;
  3024. }
  3025. static void device_init(int adapter_num, struct pci_dev *pdev)
  3026. {
  3027. struct slgt_info *port_array[SLGT_MAX_PORTS];
  3028. int i;
  3029. int port_count = 1;
  3030. if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
  3031. port_count = 2;
  3032. else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
  3033. port_count = 4;
  3034. /* allocate device instances for all ports */
  3035. for (i=0; i < port_count; ++i) {
  3036. port_array[i] = alloc_dev(adapter_num, i, pdev);
  3037. if (port_array[i] == NULL) {
  3038. for (--i; i >= 0; --i) {
  3039. tty_port_destroy(&port_array[i]->port);
  3040. kfree(port_array[i]);
  3041. }
  3042. return;
  3043. }
  3044. }
  3045. /* give copy of port_array to all ports and add to device list */
  3046. for (i=0; i < port_count; ++i) {
  3047. memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
  3048. add_device(port_array[i]);
  3049. port_array[i]->port_count = port_count;
  3050. spin_lock_init(&port_array[i]->lock);
  3051. }
  3052. /* Allocate and claim adapter resources */
  3053. if (!claim_resources(port_array[0])) {
  3054. alloc_dma_bufs(port_array[0]);
  3055. /* copy resource information from first port to others */
  3056. for (i = 1; i < port_count; ++i) {
  3057. port_array[i]->irq_level = port_array[0]->irq_level;
  3058. port_array[i]->reg_addr = port_array[0]->reg_addr;
  3059. alloc_dma_bufs(port_array[i]);
  3060. }
  3061. if (request_irq(port_array[0]->irq_level,
  3062. slgt_interrupt,
  3063. port_array[0]->irq_flags,
  3064. port_array[0]->device_name,
  3065. port_array[0]) < 0) {
  3066. DBGERR(("%s request_irq failed IRQ=%d\n",
  3067. port_array[0]->device_name,
  3068. port_array[0]->irq_level));
  3069. } else {
  3070. port_array[0]->irq_requested = true;
  3071. adapter_test(port_array[0]);
  3072. for (i=1 ; i < port_count ; i++) {
  3073. port_array[i]->init_error = port_array[0]->init_error;
  3074. port_array[i]->gpio_present = port_array[0]->gpio_present;
  3075. }
  3076. }
  3077. }
  3078. for (i = 0; i < port_count; ++i) {
  3079. struct slgt_info *info = port_array[i];
  3080. tty_port_register_device(&info->port, serial_driver, info->line,
  3081. &info->pdev->dev);
  3082. }
  3083. }
  3084. static int init_one(struct pci_dev *dev,
  3085. const struct pci_device_id *ent)
  3086. {
  3087. if (pci_enable_device(dev)) {
  3088. printk("error enabling pci device %p\n", dev);
  3089. return -EIO;
  3090. }
  3091. pci_set_master(dev);
  3092. device_init(slgt_device_count, dev);
  3093. return 0;
  3094. }
  3095. static void remove_one(struct pci_dev *dev)
  3096. {
  3097. }
  3098. static const struct tty_operations ops = {
  3099. .open = open,
  3100. .close = close,
  3101. .write = write,
  3102. .put_char = put_char,
  3103. .flush_chars = flush_chars,
  3104. .write_room = write_room,
  3105. .chars_in_buffer = chars_in_buffer,
  3106. .flush_buffer = flush_buffer,
  3107. .ioctl = ioctl,
  3108. .compat_ioctl = slgt_compat_ioctl,
  3109. .throttle = throttle,
  3110. .unthrottle = unthrottle,
  3111. .send_xchar = send_xchar,
  3112. .break_ctl = set_break,
  3113. .wait_until_sent = wait_until_sent,
  3114. .set_termios = set_termios,
  3115. .stop = tx_hold,
  3116. .start = tx_release,
  3117. .hangup = hangup,
  3118. .tiocmget = tiocmget,
  3119. .tiocmset = tiocmset,
  3120. .get_icount = get_icount,
  3121. .proc_show = synclink_gt_proc_show,
  3122. };
  3123. static void slgt_cleanup(void)
  3124. {
  3125. int rc;
  3126. struct slgt_info *info;
  3127. struct slgt_info *tmp;
  3128. printk(KERN_INFO "unload %s\n", driver_name);
  3129. if (serial_driver) {
  3130. for (info=slgt_device_list ; info != NULL ; info=info->next_device)
  3131. tty_unregister_device(serial_driver, info->line);
  3132. rc = tty_unregister_driver(serial_driver);
  3133. if (rc)
  3134. DBGERR(("tty_unregister_driver error=%d\n", rc));
  3135. put_tty_driver(serial_driver);
  3136. }
  3137. /* reset devices */
  3138. info = slgt_device_list;
  3139. while(info) {
  3140. reset_port(info);
  3141. info = info->next_device;
  3142. }
  3143. /* release devices */
  3144. info = slgt_device_list;
  3145. while(info) {
  3146. #if SYNCLINK_GENERIC_HDLC
  3147. hdlcdev_exit(info);
  3148. #endif
  3149. free_dma_bufs(info);
  3150. free_tmp_rbuf(info);
  3151. if (info->port_num == 0)
  3152. release_resources(info);
  3153. tmp = info;
  3154. info = info->next_device;
  3155. tty_port_destroy(&tmp->port);
  3156. kfree(tmp);
  3157. }
  3158. if (pci_registered)
  3159. pci_unregister_driver(&pci_driver);
  3160. }
  3161. /*
  3162. * Driver initialization entry point.
  3163. */
  3164. static int __init slgt_init(void)
  3165. {
  3166. int rc;
  3167. printk(KERN_INFO "%s\n", driver_name);
  3168. serial_driver = alloc_tty_driver(MAX_DEVICES);
  3169. if (!serial_driver) {
  3170. printk("%s can't allocate tty driver\n", driver_name);
  3171. return -ENOMEM;
  3172. }
  3173. /* Initialize the tty_driver structure */
  3174. serial_driver->driver_name = slgt_driver_name;
  3175. serial_driver->name = tty_dev_prefix;
  3176. serial_driver->major = ttymajor;
  3177. serial_driver->minor_start = 64;
  3178. serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
  3179. serial_driver->subtype = SERIAL_TYPE_NORMAL;
  3180. serial_driver->init_termios = tty_std_termios;
  3181. serial_driver->init_termios.c_cflag =
  3182. B9600 | CS8 | CREAD | HUPCL | CLOCAL;
  3183. serial_driver->init_termios.c_ispeed = 9600;
  3184. serial_driver->init_termios.c_ospeed = 9600;
  3185. serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
  3186. tty_set_operations(serial_driver, &ops);
  3187. if ((rc = tty_register_driver(serial_driver)) < 0) {
  3188. DBGERR(("%s can't register serial driver\n", driver_name));
  3189. put_tty_driver(serial_driver);
  3190. serial_driver = NULL;
  3191. goto error;
  3192. }
  3193. printk(KERN_INFO "%s, tty major#%d\n",
  3194. driver_name, serial_driver->major);
  3195. slgt_device_count = 0;
  3196. if ((rc = pci_register_driver(&pci_driver)) < 0) {
  3197. printk("%s pci_register_driver error=%d\n", driver_name, rc);
  3198. goto error;
  3199. }
  3200. pci_registered = true;
  3201. if (!slgt_device_list)
  3202. printk("%s no devices found\n",driver_name);
  3203. return 0;
  3204. error:
  3205. slgt_cleanup();
  3206. return rc;
  3207. }
  3208. static void __exit slgt_exit(void)
  3209. {
  3210. slgt_cleanup();
  3211. }
  3212. module_init(slgt_init);
  3213. module_exit(slgt_exit);
  3214. /*
  3215. * register access routines
  3216. */
  3217. #define CALC_REGADDR() \
  3218. unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
  3219. if (addr >= 0x80) \
  3220. reg_addr += (info->port_num) * 32; \
  3221. else if (addr >= 0x40) \
  3222. reg_addr += (info->port_num) * 16;
  3223. static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
  3224. {
  3225. CALC_REGADDR();
  3226. return readb((void __iomem *)reg_addr);
  3227. }
  3228. static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
  3229. {
  3230. CALC_REGADDR();
  3231. writeb(value, (void __iomem *)reg_addr);
  3232. }
  3233. static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
  3234. {
  3235. CALC_REGADDR();
  3236. return readw((void __iomem *)reg_addr);
  3237. }
  3238. static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
  3239. {
  3240. CALC_REGADDR();
  3241. writew(value, (void __iomem *)reg_addr);
  3242. }
  3243. static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
  3244. {
  3245. CALC_REGADDR();
  3246. return readl((void __iomem *)reg_addr);
  3247. }
  3248. static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
  3249. {
  3250. CALC_REGADDR();
  3251. writel(value, (void __iomem *)reg_addr);
  3252. }
  3253. static void rdma_reset(struct slgt_info *info)
  3254. {
  3255. unsigned int i;
  3256. /* set reset bit */
  3257. wr_reg32(info, RDCSR, BIT1);
  3258. /* wait for enable bit cleared */
  3259. for(i=0 ; i < 1000 ; i++)
  3260. if (!(rd_reg32(info, RDCSR) & BIT0))
  3261. break;
  3262. }
  3263. static void tdma_reset(struct slgt_info *info)
  3264. {
  3265. unsigned int i;
  3266. /* set reset bit */
  3267. wr_reg32(info, TDCSR, BIT1);
  3268. /* wait for enable bit cleared */
  3269. for(i=0 ; i < 1000 ; i++)
  3270. if (!(rd_reg32(info, TDCSR) & BIT0))
  3271. break;
  3272. }
  3273. /*
  3274. * enable internal loopback
  3275. * TxCLK and RxCLK are generated from BRG
  3276. * and TxD is looped back to RxD internally.
  3277. */
  3278. static void enable_loopback(struct slgt_info *info)
  3279. {
  3280. /* SCR (serial control) BIT2=loopback enable */
  3281. wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
  3282. if (info->params.mode != MGSL_MODE_ASYNC) {
  3283. /* CCR (clock control)
  3284. * 07..05 tx clock source (010 = BRG)
  3285. * 04..02 rx clock source (010 = BRG)
  3286. * 01 auxclk enable (0 = disable)
  3287. * 00 BRG enable (1 = enable)
  3288. *
  3289. * 0100 1001
  3290. */
  3291. wr_reg8(info, CCR, 0x49);
  3292. /* set speed if available, otherwise use default */
  3293. if (info->params.clock_speed)
  3294. set_rate(info, info->params.clock_speed);
  3295. else
  3296. set_rate(info, 3686400);
  3297. }
  3298. }
  3299. /*
  3300. * set baud rate generator to specified rate
  3301. */
  3302. static void set_rate(struct slgt_info *info, u32 rate)
  3303. {
  3304. unsigned int div;
  3305. unsigned int osc = info->base_clock;
  3306. /* div = osc/rate - 1
  3307. *
  3308. * Round div up if osc/rate is not integer to
  3309. * force to next slowest rate.
  3310. */
  3311. if (rate) {
  3312. div = osc/rate;
  3313. if (!(osc % rate) && div)
  3314. div--;
  3315. wr_reg16(info, BDR, (unsigned short)div);
  3316. }
  3317. }
  3318. static void rx_stop(struct slgt_info *info)
  3319. {
  3320. unsigned short val;
  3321. /* disable and reset receiver */
  3322. val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
  3323. wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
  3324. wr_reg16(info, RCR, val); /* clear reset bit */
  3325. slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
  3326. /* clear pending rx interrupts */
  3327. wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
  3328. rdma_reset(info);
  3329. info->rx_enabled = false;
  3330. info->rx_restart = false;
  3331. }
  3332. static void rx_start(struct slgt_info *info)
  3333. {
  3334. unsigned short val;
  3335. slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
  3336. /* clear pending rx overrun IRQ */
  3337. wr_reg16(info, SSR, IRQ_RXOVER);
  3338. /* reset and disable receiver */
  3339. val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
  3340. wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
  3341. wr_reg16(info, RCR, val); /* clear reset bit */
  3342. rdma_reset(info);
  3343. reset_rbufs(info);
  3344. if (info->rx_pio) {
  3345. /* rx request when rx FIFO not empty */
  3346. wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
  3347. slgt_irq_on(info, IRQ_RXDATA);
  3348. if (info->params.mode == MGSL_MODE_ASYNC) {
  3349. /* enable saving of rx status */
  3350. wr_reg32(info, RDCSR, BIT6);
  3351. }
  3352. } else {
  3353. /* rx request when rx FIFO half full */
  3354. wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
  3355. /* set 1st descriptor address */
  3356. wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
  3357. if (info->params.mode != MGSL_MODE_ASYNC) {
  3358. /* enable rx DMA and DMA interrupt */
  3359. wr_reg32(info, RDCSR, (BIT2 + BIT0));
  3360. } else {
  3361. /* enable saving of rx status, rx DMA and DMA interrupt */
  3362. wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
  3363. }
  3364. }
  3365. slgt_irq_on(info, IRQ_RXOVER);
  3366. /* enable receiver */
  3367. wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
  3368. info->rx_restart = false;
  3369. info->rx_enabled = true;
  3370. }
  3371. static void tx_start(struct slgt_info *info)
  3372. {
  3373. if (!info->tx_enabled) {
  3374. wr_reg16(info, TCR,
  3375. (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
  3376. info->tx_enabled = true;
  3377. }
  3378. if (desc_count(info->tbufs[info->tbuf_start])) {
  3379. info->drop_rts_on_tx_done = false;
  3380. if (info->params.mode != MGSL_MODE_ASYNC) {
  3381. if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
  3382. get_gtsignals(info);
  3383. if (!(info->signals & SerialSignal_RTS)) {
  3384. info->signals |= SerialSignal_RTS;
  3385. set_gtsignals(info);
  3386. info->drop_rts_on_tx_done = true;
  3387. }
  3388. }
  3389. slgt_irq_off(info, IRQ_TXDATA);
  3390. slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
  3391. /* clear tx idle and underrun status bits */
  3392. wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
  3393. } else {
  3394. slgt_irq_off(info, IRQ_TXDATA);
  3395. slgt_irq_on(info, IRQ_TXIDLE);
  3396. /* clear tx idle status bit */
  3397. wr_reg16(info, SSR, IRQ_TXIDLE);
  3398. }
  3399. /* set 1st descriptor address and start DMA */
  3400. wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
  3401. wr_reg32(info, TDCSR, BIT2 + BIT0);
  3402. info->tx_active = true;
  3403. }
  3404. }
  3405. static void tx_stop(struct slgt_info *info)
  3406. {
  3407. unsigned short val;
  3408. del_timer(&info->tx_timer);
  3409. tdma_reset(info);
  3410. /* reset and disable transmitter */
  3411. val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
  3412. wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
  3413. slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
  3414. /* clear tx idle and underrun status bit */
  3415. wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
  3416. reset_tbufs(info);
  3417. info->tx_enabled = false;
  3418. info->tx_active = false;
  3419. }
  3420. static void reset_port(struct slgt_info *info)
  3421. {
  3422. if (!info->reg_addr)
  3423. return;
  3424. tx_stop(info);
  3425. rx_stop(info);
  3426. info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
  3427. set_gtsignals(info);
  3428. slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
  3429. }
  3430. static void reset_adapter(struct slgt_info *info)
  3431. {
  3432. int i;
  3433. for (i=0; i < info->port_count; ++i) {
  3434. if (info->port_array[i])
  3435. reset_port(info->port_array[i]);
  3436. }
  3437. }
  3438. static void async_mode(struct slgt_info *info)
  3439. {
  3440. unsigned short val;
  3441. slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
  3442. tx_stop(info);
  3443. rx_stop(info);
  3444. /* TCR (tx control)
  3445. *
  3446. * 15..13 mode, 010=async
  3447. * 12..10 encoding, 000=NRZ
  3448. * 09 parity enable
  3449. * 08 1=odd parity, 0=even parity
  3450. * 07 1=RTS driver control
  3451. * 06 1=break enable
  3452. * 05..04 character length
  3453. * 00=5 bits
  3454. * 01=6 bits
  3455. * 10=7 bits
  3456. * 11=8 bits
  3457. * 03 0=1 stop bit, 1=2 stop bits
  3458. * 02 reset
  3459. * 01 enable
  3460. * 00 auto-CTS enable
  3461. */
  3462. val = 0x4000;
  3463. if (info->if_mode & MGSL_INTERFACE_RTS_EN)
  3464. val |= BIT7;
  3465. if (info->params.parity != ASYNC_PARITY_NONE) {
  3466. val |= BIT9;
  3467. if (info->params.parity == ASYNC_PARITY_ODD)
  3468. val |= BIT8;
  3469. }
  3470. switch (info->params.data_bits)
  3471. {
  3472. case 6: val |= BIT4; break;
  3473. case 7: val |= BIT5; break;
  3474. case 8: val |= BIT5 + BIT4; break;
  3475. }
  3476. if (info->params.stop_bits != 1)
  3477. val |= BIT3;
  3478. if (info->params.flags & HDLC_FLAG_AUTO_CTS)
  3479. val |= BIT0;
  3480. wr_reg16(info, TCR, val);
  3481. /* RCR (rx control)
  3482. *
  3483. * 15..13 mode, 010=async
  3484. * 12..10 encoding, 000=NRZ
  3485. * 09 parity enable
  3486. * 08 1=odd parity, 0=even parity
  3487. * 07..06 reserved, must be 0
  3488. * 05..04 character length
  3489. * 00=5 bits
  3490. * 01=6 bits
  3491. * 10=7 bits
  3492. * 11=8 bits
  3493. * 03 reserved, must be zero
  3494. * 02 reset
  3495. * 01 enable
  3496. * 00 auto-DCD enable
  3497. */
  3498. val = 0x4000;
  3499. if (info->params.parity != ASYNC_PARITY_NONE) {
  3500. val |= BIT9;
  3501. if (info->params.parity == ASYNC_PARITY_ODD)
  3502. val |= BIT8;
  3503. }
  3504. switch (info->params.data_bits)
  3505. {
  3506. case 6: val |= BIT4; break;
  3507. case 7: val |= BIT5; break;
  3508. case 8: val |= BIT5 + BIT4; break;
  3509. }
  3510. if (info->params.flags & HDLC_FLAG_AUTO_DCD)
  3511. val |= BIT0;
  3512. wr_reg16(info, RCR, val);
  3513. /* CCR (clock control)
  3514. *
  3515. * 07..05 011 = tx clock source is BRG/16
  3516. * 04..02 010 = rx clock source is BRG
  3517. * 01 0 = auxclk disabled
  3518. * 00 1 = BRG enabled
  3519. *
  3520. * 0110 1001
  3521. */
  3522. wr_reg8(info, CCR, 0x69);
  3523. msc_set_vcr(info);
  3524. /* SCR (serial control)
  3525. *
  3526. * 15 1=tx req on FIFO half empty
  3527. * 14 1=rx req on FIFO half full
  3528. * 13 tx data IRQ enable
  3529. * 12 tx idle IRQ enable
  3530. * 11 rx break on IRQ enable
  3531. * 10 rx data IRQ enable
  3532. * 09 rx break off IRQ enable
  3533. * 08 overrun IRQ enable
  3534. * 07 DSR IRQ enable
  3535. * 06 CTS IRQ enable
  3536. * 05 DCD IRQ enable
  3537. * 04 RI IRQ enable
  3538. * 03 0=16x sampling, 1=8x sampling
  3539. * 02 1=txd->rxd internal loopback enable
  3540. * 01 reserved, must be zero
  3541. * 00 1=master IRQ enable
  3542. */
  3543. val = BIT15 + BIT14 + BIT0;
  3544. /* JCR[8] : 1 = x8 async mode feature available */
  3545. if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
  3546. ((info->base_clock < (info->params.data_rate * 16)) ||
  3547. (info->base_clock % (info->params.data_rate * 16)))) {
  3548. /* use 8x sampling */
  3549. val |= BIT3;
  3550. set_rate(info, info->params.data_rate * 8);
  3551. } else {
  3552. /* use 16x sampling */
  3553. set_rate(info, info->params.data_rate * 16);
  3554. }
  3555. wr_reg16(info, SCR, val);
  3556. slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
  3557. if (info->params.loopback)
  3558. enable_loopback(info);
  3559. }
  3560. static void sync_mode(struct slgt_info *info)
  3561. {
  3562. unsigned short val;
  3563. slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
  3564. tx_stop(info);
  3565. rx_stop(info);
  3566. /* TCR (tx control)
  3567. *
  3568. * 15..13 mode
  3569. * 000=HDLC/SDLC
  3570. * 001=raw bit synchronous
  3571. * 010=asynchronous/isochronous
  3572. * 011=monosync byte synchronous
  3573. * 100=bisync byte synchronous
  3574. * 101=xsync byte synchronous
  3575. * 12..10 encoding
  3576. * 09 CRC enable
  3577. * 08 CRC32
  3578. * 07 1=RTS driver control
  3579. * 06 preamble enable
  3580. * 05..04 preamble length
  3581. * 03 share open/close flag
  3582. * 02 reset
  3583. * 01 enable
  3584. * 00 auto-CTS enable
  3585. */
  3586. val = BIT2;
  3587. switch(info->params.mode) {
  3588. case MGSL_MODE_XSYNC:
  3589. val |= BIT15 + BIT13;
  3590. break;
  3591. case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
  3592. case MGSL_MODE_BISYNC: val |= BIT15; break;
  3593. case MGSL_MODE_RAW: val |= BIT13; break;
  3594. }
  3595. if (info->if_mode & MGSL_INTERFACE_RTS_EN)
  3596. val |= BIT7;
  3597. switch(info->params.encoding)
  3598. {
  3599. case HDLC_ENCODING_NRZB: val |= BIT10; break;
  3600. case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
  3601. case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
  3602. case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
  3603. case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
  3604. case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
  3605. case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
  3606. }
  3607. switch (info->params.crc_type & HDLC_CRC_MASK)
  3608. {
  3609. case HDLC_CRC_16_CCITT: val |= BIT9; break;
  3610. case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
  3611. }
  3612. if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
  3613. val |= BIT6;
  3614. switch (info->params.preamble_length)
  3615. {
  3616. case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
  3617. case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
  3618. case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
  3619. }
  3620. if (info->params.flags & HDLC_FLAG_AUTO_CTS)
  3621. val |= BIT0;
  3622. wr_reg16(info, TCR, val);
  3623. /* TPR (transmit preamble) */
  3624. switch (info->params.preamble)
  3625. {
  3626. case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
  3627. case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
  3628. case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
  3629. case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break;
  3630. case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break;
  3631. default: val = 0x7e; break;
  3632. }
  3633. wr_reg8(info, TPR, (unsigned char)val);
  3634. /* RCR (rx control)
  3635. *
  3636. * 15..13 mode
  3637. * 000=HDLC/SDLC
  3638. * 001=raw bit synchronous
  3639. * 010=asynchronous/isochronous
  3640. * 011=monosync byte synchronous
  3641. * 100=bisync byte synchronous
  3642. * 101=xsync byte synchronous
  3643. * 12..10 encoding
  3644. * 09 CRC enable
  3645. * 08 CRC32
  3646. * 07..03 reserved, must be 0
  3647. * 02 reset
  3648. * 01 enable
  3649. * 00 auto-DCD enable
  3650. */
  3651. val = 0;
  3652. switch(info->params.mode) {
  3653. case MGSL_MODE_XSYNC:
  3654. val |= BIT15 + BIT13;
  3655. break;
  3656. case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
  3657. case MGSL_MODE_BISYNC: val |= BIT15; break;
  3658. case MGSL_MODE_RAW: val |= BIT13; break;
  3659. }
  3660. switch(info->params.encoding)
  3661. {
  3662. case HDLC_ENCODING_NRZB: val |= BIT10; break;
  3663. case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
  3664. case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
  3665. case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
  3666. case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
  3667. case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
  3668. case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
  3669. }
  3670. switch (info->params.crc_type & HDLC_CRC_MASK)
  3671. {
  3672. case HDLC_CRC_16_CCITT: val |= BIT9; break;
  3673. case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
  3674. }
  3675. if (info->params.flags & HDLC_FLAG_AUTO_DCD)
  3676. val |= BIT0;
  3677. wr_reg16(info, RCR, val);
  3678. /* CCR (clock control)
  3679. *
  3680. * 07..05 tx clock source
  3681. * 04..02 rx clock source
  3682. * 01 auxclk enable
  3683. * 00 BRG enable
  3684. */
  3685. val = 0;
  3686. if (info->params.flags & HDLC_FLAG_TXC_BRG)
  3687. {
  3688. // when RxC source is DPLL, BRG generates 16X DPLL
  3689. // reference clock, so take TxC from BRG/16 to get
  3690. // transmit clock at actual data rate
  3691. if (info->params.flags & HDLC_FLAG_RXC_DPLL)
  3692. val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
  3693. else
  3694. val |= BIT6; /* 010, txclk = BRG */
  3695. }
  3696. else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
  3697. val |= BIT7; /* 100, txclk = DPLL Input */
  3698. else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
  3699. val |= BIT5; /* 001, txclk = RXC Input */
  3700. if (info->params.flags & HDLC_FLAG_RXC_BRG)
  3701. val |= BIT3; /* 010, rxclk = BRG */
  3702. else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
  3703. val |= BIT4; /* 100, rxclk = DPLL */
  3704. else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
  3705. val |= BIT2; /* 001, rxclk = TXC Input */
  3706. if (info->params.clock_speed)
  3707. val |= BIT1 + BIT0;
  3708. wr_reg8(info, CCR, (unsigned char)val);
  3709. if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
  3710. {
  3711. // program DPLL mode
  3712. switch(info->params.encoding)
  3713. {
  3714. case HDLC_ENCODING_BIPHASE_MARK:
  3715. case HDLC_ENCODING_BIPHASE_SPACE:
  3716. val = BIT7; break;
  3717. case HDLC_ENCODING_BIPHASE_LEVEL:
  3718. case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
  3719. val = BIT7 + BIT6; break;
  3720. default: val = BIT6; // NRZ encodings
  3721. }
  3722. wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
  3723. // DPLL requires a 16X reference clock from BRG
  3724. set_rate(info, info->params.clock_speed * 16);
  3725. }
  3726. else
  3727. set_rate(info, info->params.clock_speed);
  3728. tx_set_idle(info);
  3729. msc_set_vcr(info);
  3730. /* SCR (serial control)
  3731. *
  3732. * 15 1=tx req on FIFO half empty
  3733. * 14 1=rx req on FIFO half full
  3734. * 13 tx data IRQ enable
  3735. * 12 tx idle IRQ enable
  3736. * 11 underrun IRQ enable
  3737. * 10 rx data IRQ enable
  3738. * 09 rx idle IRQ enable
  3739. * 08 overrun IRQ enable
  3740. * 07 DSR IRQ enable
  3741. * 06 CTS IRQ enable
  3742. * 05 DCD IRQ enable
  3743. * 04 RI IRQ enable
  3744. * 03 reserved, must be zero
  3745. * 02 1=txd->rxd internal loopback enable
  3746. * 01 reserved, must be zero
  3747. * 00 1=master IRQ enable
  3748. */
  3749. wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
  3750. if (info->params.loopback)
  3751. enable_loopback(info);
  3752. }
  3753. /*
  3754. * set transmit idle mode
  3755. */
  3756. static void tx_set_idle(struct slgt_info *info)
  3757. {
  3758. unsigned char val;
  3759. unsigned short tcr;
  3760. /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
  3761. * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
  3762. */
  3763. tcr = rd_reg16(info, TCR);
  3764. if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
  3765. /* disable preamble, set idle size to 16 bits */
  3766. tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
  3767. /* MSB of 16 bit idle specified in tx preamble register (TPR) */
  3768. wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
  3769. } else if (!(tcr & BIT6)) {
  3770. /* preamble is disabled, set idle size to 8 bits */
  3771. tcr &= ~(BIT5 + BIT4);
  3772. }
  3773. wr_reg16(info, TCR, tcr);
  3774. if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
  3775. /* LSB of custom tx idle specified in tx idle register */
  3776. val = (unsigned char)(info->idle_mode & 0xff);
  3777. } else {
  3778. /* standard 8 bit idle patterns */
  3779. switch(info->idle_mode)
  3780. {
  3781. case HDLC_TXIDLE_FLAGS: val = 0x7e; break;
  3782. case HDLC_TXIDLE_ALT_ZEROS_ONES:
  3783. case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
  3784. case HDLC_TXIDLE_ZEROS:
  3785. case HDLC_TXIDLE_SPACE: val = 0x00; break;
  3786. default: val = 0xff;
  3787. }
  3788. }
  3789. wr_reg8(info, TIR, val);
  3790. }
  3791. /*
  3792. * get state of V24 status (input) signals
  3793. */
  3794. static void get_gtsignals(struct slgt_info *info)
  3795. {
  3796. unsigned short status = rd_reg16(info, SSR);
  3797. /* clear all serial signals except RTS and DTR */
  3798. info->signals &= SerialSignal_RTS | SerialSignal_DTR;
  3799. if (status & BIT3)
  3800. info->signals |= SerialSignal_DSR;
  3801. if (status & BIT2)
  3802. info->signals |= SerialSignal_CTS;
  3803. if (status & BIT1)
  3804. info->signals |= SerialSignal_DCD;
  3805. if (status & BIT0)
  3806. info->signals |= SerialSignal_RI;
  3807. }
  3808. /*
  3809. * set V.24 Control Register based on current configuration
  3810. */
  3811. static void msc_set_vcr(struct slgt_info *info)
  3812. {
  3813. unsigned char val = 0;
  3814. /* VCR (V.24 control)
  3815. *
  3816. * 07..04 serial IF select
  3817. * 03 DTR
  3818. * 02 RTS
  3819. * 01 LL
  3820. * 00 RL
  3821. */
  3822. switch(info->if_mode & MGSL_INTERFACE_MASK)
  3823. {
  3824. case MGSL_INTERFACE_RS232:
  3825. val |= BIT5; /* 0010 */
  3826. break;
  3827. case MGSL_INTERFACE_V35:
  3828. val |= BIT7 + BIT6 + BIT5; /* 1110 */
  3829. break;
  3830. case MGSL_INTERFACE_RS422:
  3831. val |= BIT6; /* 0100 */
  3832. break;
  3833. }
  3834. if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
  3835. val |= BIT4;
  3836. if (info->signals & SerialSignal_DTR)
  3837. val |= BIT3;
  3838. if (info->signals & SerialSignal_RTS)
  3839. val |= BIT2;
  3840. if (info->if_mode & MGSL_INTERFACE_LL)
  3841. val |= BIT1;
  3842. if (info->if_mode & MGSL_INTERFACE_RL)
  3843. val |= BIT0;
  3844. wr_reg8(info, VCR, val);
  3845. }
  3846. /*
  3847. * set state of V24 control (output) signals
  3848. */
  3849. static void set_gtsignals(struct slgt_info *info)
  3850. {
  3851. unsigned char val = rd_reg8(info, VCR);
  3852. if (info->signals & SerialSignal_DTR)
  3853. val |= BIT3;
  3854. else
  3855. val &= ~BIT3;
  3856. if (info->signals & SerialSignal_RTS)
  3857. val |= BIT2;
  3858. else
  3859. val &= ~BIT2;
  3860. wr_reg8(info, VCR, val);
  3861. }
  3862. /*
  3863. * free range of receive DMA buffers (i to last)
  3864. */
  3865. static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
  3866. {
  3867. int done = 0;
  3868. while(!done) {
  3869. /* reset current buffer for reuse */
  3870. info->rbufs[i].status = 0;
  3871. set_desc_count(info->rbufs[i], info->rbuf_fill_level);
  3872. if (i == last)
  3873. done = 1;
  3874. if (++i == info->rbuf_count)
  3875. i = 0;
  3876. }
  3877. info->rbuf_current = i;
  3878. }
  3879. /*
  3880. * mark all receive DMA buffers as free
  3881. */
  3882. static void reset_rbufs(struct slgt_info *info)
  3883. {
  3884. free_rbufs(info, 0, info->rbuf_count - 1);
  3885. info->rbuf_fill_index = 0;
  3886. info->rbuf_fill_count = 0;
  3887. }
  3888. /*
  3889. * pass receive HDLC frame to upper layer
  3890. *
  3891. * return true if frame available, otherwise false
  3892. */
  3893. static bool rx_get_frame(struct slgt_info *info)
  3894. {
  3895. unsigned int start, end;
  3896. unsigned short status;
  3897. unsigned int framesize = 0;
  3898. unsigned long flags;
  3899. struct tty_struct *tty = info->port.tty;
  3900. unsigned char addr_field = 0xff;
  3901. unsigned int crc_size = 0;
  3902. switch (info->params.crc_type & HDLC_CRC_MASK) {
  3903. case HDLC_CRC_16_CCITT: crc_size = 2; break;
  3904. case HDLC_CRC_32_CCITT: crc_size = 4; break;
  3905. }
  3906. check_again:
  3907. framesize = 0;
  3908. addr_field = 0xff;
  3909. start = end = info->rbuf_current;
  3910. for (;;) {
  3911. if (!desc_complete(info->rbufs[end]))
  3912. goto cleanup;
  3913. if (framesize == 0 && info->params.addr_filter != 0xff)
  3914. addr_field = info->rbufs[end].buf[0];
  3915. framesize += desc_count(info->rbufs[end]);
  3916. if (desc_eof(info->rbufs[end]))
  3917. break;
  3918. if (++end == info->rbuf_count)
  3919. end = 0;
  3920. if (end == info->rbuf_current) {
  3921. if (info->rx_enabled){
  3922. spin_lock_irqsave(&info->lock,flags);
  3923. rx_start(info);
  3924. spin_unlock_irqrestore(&info->lock,flags);
  3925. }
  3926. goto cleanup;
  3927. }
  3928. }
  3929. /* status
  3930. *
  3931. * 15 buffer complete
  3932. * 14..06 reserved
  3933. * 05..04 residue
  3934. * 02 eof (end of frame)
  3935. * 01 CRC error
  3936. * 00 abort
  3937. */
  3938. status = desc_status(info->rbufs[end]);
  3939. /* ignore CRC bit if not using CRC (bit is undefined) */
  3940. if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
  3941. status &= ~BIT1;
  3942. if (framesize == 0 ||
  3943. (addr_field != 0xff && addr_field != info->params.addr_filter)) {
  3944. free_rbufs(info, start, end);
  3945. goto check_again;
  3946. }
  3947. if (framesize < (2 + crc_size) || status & BIT0) {
  3948. info->icount.rxshort++;
  3949. framesize = 0;
  3950. } else if (status & BIT1) {
  3951. info->icount.rxcrc++;
  3952. if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
  3953. framesize = 0;
  3954. }
  3955. #if SYNCLINK_GENERIC_HDLC
  3956. if (framesize == 0) {
  3957. info->netdev->stats.rx_errors++;
  3958. info->netdev->stats.rx_frame_errors++;
  3959. }
  3960. #endif
  3961. DBGBH(("%s rx frame status=%04X size=%d\n",
  3962. info->device_name, status, framesize));
  3963. DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
  3964. if (framesize) {
  3965. if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
  3966. framesize -= crc_size;
  3967. crc_size = 0;
  3968. }
  3969. if (framesize > info->max_frame_size + crc_size)
  3970. info->icount.rxlong++;
  3971. else {
  3972. /* copy dma buffer(s) to contiguous temp buffer */
  3973. int copy_count = framesize;
  3974. int i = start;
  3975. unsigned char *p = info->tmp_rbuf;
  3976. info->tmp_rbuf_count = framesize;
  3977. info->icount.rxok++;
  3978. while(copy_count) {
  3979. int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
  3980. memcpy(p, info->rbufs[i].buf, partial_count);
  3981. p += partial_count;
  3982. copy_count -= partial_count;
  3983. if (++i == info->rbuf_count)
  3984. i = 0;
  3985. }
  3986. if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
  3987. *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
  3988. framesize++;
  3989. }
  3990. #if SYNCLINK_GENERIC_HDLC
  3991. if (info->netcount)
  3992. hdlcdev_rx(info,info->tmp_rbuf, framesize);
  3993. else
  3994. #endif
  3995. ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
  3996. }
  3997. }
  3998. free_rbufs(info, start, end);
  3999. return true;
  4000. cleanup:
  4001. return false;
  4002. }
  4003. /*
  4004. * pass receive buffer (RAW synchronous mode) to tty layer
  4005. * return true if buffer available, otherwise false
  4006. */
  4007. static bool rx_get_buf(struct slgt_info *info)
  4008. {
  4009. unsigned int i = info->rbuf_current;
  4010. unsigned int count;
  4011. if (!desc_complete(info->rbufs[i]))
  4012. return false;
  4013. count = desc_count(info->rbufs[i]);
  4014. switch(info->params.mode) {
  4015. case MGSL_MODE_MONOSYNC:
  4016. case MGSL_MODE_BISYNC:
  4017. case MGSL_MODE_XSYNC:
  4018. /* ignore residue in byte synchronous modes */
  4019. if (desc_residue(info->rbufs[i]))
  4020. count--;
  4021. break;
  4022. }
  4023. DBGDATA(info, info->rbufs[i].buf, count, "rx");
  4024. DBGINFO(("rx_get_buf size=%d\n", count));
  4025. if (count)
  4026. ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
  4027. info->flag_buf, count);
  4028. free_rbufs(info, i, i);
  4029. return true;
  4030. }
  4031. static void reset_tbufs(struct slgt_info *info)
  4032. {
  4033. unsigned int i;
  4034. info->tbuf_current = 0;
  4035. for (i=0 ; i < info->tbuf_count ; i++) {
  4036. info->tbufs[i].status = 0;
  4037. info->tbufs[i].count = 0;
  4038. }
  4039. }
  4040. /*
  4041. * return number of free transmit DMA buffers
  4042. */
  4043. static unsigned int free_tbuf_count(struct slgt_info *info)
  4044. {
  4045. unsigned int count = 0;
  4046. unsigned int i = info->tbuf_current;
  4047. do
  4048. {
  4049. if (desc_count(info->tbufs[i]))
  4050. break; /* buffer in use */
  4051. ++count;
  4052. if (++i == info->tbuf_count)
  4053. i=0;
  4054. } while (i != info->tbuf_current);
  4055. /* if tx DMA active, last zero count buffer is in use */
  4056. if (count && (rd_reg32(info, TDCSR) & BIT0))
  4057. --count;
  4058. return count;
  4059. }
  4060. /*
  4061. * return number of bytes in unsent transmit DMA buffers
  4062. * and the serial controller tx FIFO
  4063. */
  4064. static unsigned int tbuf_bytes(struct slgt_info *info)
  4065. {
  4066. unsigned int total_count = 0;
  4067. unsigned int i = info->tbuf_current;
  4068. unsigned int reg_value;
  4069. unsigned int count;
  4070. unsigned int active_buf_count = 0;
  4071. /*
  4072. * Add descriptor counts for all tx DMA buffers.
  4073. * If count is zero (cleared by DMA controller after read),
  4074. * the buffer is complete or is actively being read from.
  4075. *
  4076. * Record buf_count of last buffer with zero count starting
  4077. * from current ring position. buf_count is mirror
  4078. * copy of count and is not cleared by serial controller.
  4079. * If DMA controller is active, that buffer is actively
  4080. * being read so add to total.
  4081. */
  4082. do {
  4083. count = desc_count(info->tbufs[i]);
  4084. if (count)
  4085. total_count += count;
  4086. else if (!total_count)
  4087. active_buf_count = info->tbufs[i].buf_count;
  4088. if (++i == info->tbuf_count)
  4089. i = 0;
  4090. } while (i != info->tbuf_current);
  4091. /* read tx DMA status register */
  4092. reg_value = rd_reg32(info, TDCSR);
  4093. /* if tx DMA active, last zero count buffer is in use */
  4094. if (reg_value & BIT0)
  4095. total_count += active_buf_count;
  4096. /* add tx FIFO count = reg_value[15..8] */
  4097. total_count += (reg_value >> 8) & 0xff;
  4098. /* if transmitter active add one byte for shift register */
  4099. if (info->tx_active)
  4100. total_count++;
  4101. return total_count;
  4102. }
  4103. /*
  4104. * load data into transmit DMA buffer ring and start transmitter if needed
  4105. * return true if data accepted, otherwise false (buffers full)
  4106. */
  4107. static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size)
  4108. {
  4109. unsigned short count;
  4110. unsigned int i;
  4111. struct slgt_desc *d;
  4112. /* check required buffer space */
  4113. if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info))
  4114. return false;
  4115. DBGDATA(info, buf, size, "tx");
  4116. /*
  4117. * copy data to one or more DMA buffers in circular ring
  4118. * tbuf_start = first buffer for this data
  4119. * tbuf_current = next free buffer
  4120. *
  4121. * Copy all data before making data visible to DMA controller by
  4122. * setting descriptor count of the first buffer.
  4123. * This prevents an active DMA controller from reading the first DMA
  4124. * buffers of a frame and stopping before the final buffers are filled.
  4125. */
  4126. info->tbuf_start = i = info->tbuf_current;
  4127. while (size) {
  4128. d = &info->tbufs[i];
  4129. count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
  4130. memcpy(d->buf, buf, count);
  4131. size -= count;
  4132. buf += count;
  4133. /*
  4134. * set EOF bit for last buffer of HDLC frame or
  4135. * for every buffer in raw mode
  4136. */
  4137. if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
  4138. info->params.mode == MGSL_MODE_RAW)
  4139. set_desc_eof(*d, 1);
  4140. else
  4141. set_desc_eof(*d, 0);
  4142. /* set descriptor count for all but first buffer */
  4143. if (i != info->tbuf_start)
  4144. set_desc_count(*d, count);
  4145. d->buf_count = count;
  4146. if (++i == info->tbuf_count)
  4147. i = 0;
  4148. }
  4149. info->tbuf_current = i;
  4150. /* set first buffer count to make new data visible to DMA controller */
  4151. d = &info->tbufs[info->tbuf_start];
  4152. set_desc_count(*d, d->buf_count);
  4153. /* start transmitter if needed and update transmit timeout */
  4154. if (!info->tx_active)
  4155. tx_start(info);
  4156. update_tx_timer(info);
  4157. return true;
  4158. }
  4159. static int register_test(struct slgt_info *info)
  4160. {
  4161. static unsigned short patterns[] =
  4162. {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
  4163. static unsigned int count = ARRAY_SIZE(patterns);
  4164. unsigned int i;
  4165. int rc = 0;
  4166. for (i=0 ; i < count ; i++) {
  4167. wr_reg16(info, TIR, patterns[i]);
  4168. wr_reg16(info, BDR, patterns[(i+1)%count]);
  4169. if ((rd_reg16(info, TIR) != patterns[i]) ||
  4170. (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
  4171. rc = -ENODEV;
  4172. break;
  4173. }
  4174. }
  4175. info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
  4176. info->init_error = rc ? 0 : DiagStatus_AddressFailure;
  4177. return rc;
  4178. }
  4179. static int irq_test(struct slgt_info *info)
  4180. {
  4181. unsigned long timeout;
  4182. unsigned long flags;
  4183. struct tty_struct *oldtty = info->port.tty;
  4184. u32 speed = info->params.data_rate;
  4185. info->params.data_rate = 921600;
  4186. info->port.tty = NULL;
  4187. spin_lock_irqsave(&info->lock, flags);
  4188. async_mode(info);
  4189. slgt_irq_on(info, IRQ_TXIDLE);
  4190. /* enable transmitter */
  4191. wr_reg16(info, TCR,
  4192. (unsigned short)(rd_reg16(info, TCR) | BIT1));
  4193. /* write one byte and wait for tx idle */
  4194. wr_reg16(info, TDR, 0);
  4195. /* assume failure */
  4196. info->init_error = DiagStatus_IrqFailure;
  4197. info->irq_occurred = false;
  4198. spin_unlock_irqrestore(&info->lock, flags);
  4199. timeout=100;
  4200. while(timeout-- && !info->irq_occurred)
  4201. msleep_interruptible(10);
  4202. spin_lock_irqsave(&info->lock,flags);
  4203. reset_port(info);
  4204. spin_unlock_irqrestore(&info->lock,flags);
  4205. info->params.data_rate = speed;
  4206. info->port.tty = oldtty;
  4207. info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
  4208. return info->irq_occurred ? 0 : -ENODEV;
  4209. }
  4210. static int loopback_test_rx(struct slgt_info *info)
  4211. {
  4212. unsigned char *src, *dest;
  4213. int count;
  4214. if (desc_complete(info->rbufs[0])) {
  4215. count = desc_count(info->rbufs[0]);
  4216. src = info->rbufs[0].buf;
  4217. dest = info->tmp_rbuf;
  4218. for( ; count ; count-=2, src+=2) {
  4219. /* src=data byte (src+1)=status byte */
  4220. if (!(*(src+1) & (BIT9 + BIT8))) {
  4221. *dest = *src;
  4222. dest++;
  4223. info->tmp_rbuf_count++;
  4224. }
  4225. }
  4226. DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
  4227. return 1;
  4228. }
  4229. return 0;
  4230. }
  4231. static int loopback_test(struct slgt_info *info)
  4232. {
  4233. #define TESTFRAMESIZE 20
  4234. unsigned long timeout;
  4235. u16 count = TESTFRAMESIZE;
  4236. unsigned char buf[TESTFRAMESIZE];
  4237. int rc = -ENODEV;
  4238. unsigned long flags;
  4239. struct tty_struct *oldtty = info->port.tty;
  4240. MGSL_PARAMS params;
  4241. memcpy(&params, &info->params, sizeof(params));
  4242. info->params.mode = MGSL_MODE_ASYNC;
  4243. info->params.data_rate = 921600;
  4244. info->params.loopback = 1;
  4245. info->port.tty = NULL;
  4246. /* build and send transmit frame */
  4247. for (count = 0; count < TESTFRAMESIZE; ++count)
  4248. buf[count] = (unsigned char)count;
  4249. info->tmp_rbuf_count = 0;
  4250. memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
  4251. /* program hardware for HDLC and enabled receiver */
  4252. spin_lock_irqsave(&info->lock,flags);
  4253. async_mode(info);
  4254. rx_start(info);
  4255. tx_load(info, buf, count);
  4256. spin_unlock_irqrestore(&info->lock, flags);
  4257. /* wait for receive complete */
  4258. for (timeout = 100; timeout; --timeout) {
  4259. msleep_interruptible(10);
  4260. if (loopback_test_rx(info)) {
  4261. rc = 0;
  4262. break;
  4263. }
  4264. }
  4265. /* verify received frame length and contents */
  4266. if (!rc && (info->tmp_rbuf_count != count ||
  4267. memcmp(buf, info->tmp_rbuf, count))) {
  4268. rc = -ENODEV;
  4269. }
  4270. spin_lock_irqsave(&info->lock,flags);
  4271. reset_adapter(info);
  4272. spin_unlock_irqrestore(&info->lock,flags);
  4273. memcpy(&info->params, &params, sizeof(info->params));
  4274. info->port.tty = oldtty;
  4275. info->init_error = rc ? DiagStatus_DmaFailure : 0;
  4276. return rc;
  4277. }
  4278. static int adapter_test(struct slgt_info *info)
  4279. {
  4280. DBGINFO(("testing %s\n", info->device_name));
  4281. if (register_test(info) < 0) {
  4282. printk("register test failure %s addr=%08X\n",
  4283. info->device_name, info->phys_reg_addr);
  4284. } else if (irq_test(info) < 0) {
  4285. printk("IRQ test failure %s IRQ=%d\n",
  4286. info->device_name, info->irq_level);
  4287. } else if (loopback_test(info) < 0) {
  4288. printk("loopback test failure %s\n", info->device_name);
  4289. }
  4290. return info->init_error;
  4291. }
  4292. /*
  4293. * transmit timeout handler
  4294. */
  4295. static void tx_timeout(struct timer_list *t)
  4296. {
  4297. struct slgt_info *info = from_timer(info, t, tx_timer);
  4298. unsigned long flags;
  4299. DBGINFO(("%s tx_timeout\n", info->device_name));
  4300. if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
  4301. info->icount.txtimeout++;
  4302. }
  4303. spin_lock_irqsave(&info->lock,flags);
  4304. tx_stop(info);
  4305. spin_unlock_irqrestore(&info->lock,flags);
  4306. #if SYNCLINK_GENERIC_HDLC
  4307. if (info->netcount)
  4308. hdlcdev_tx_done(info);
  4309. else
  4310. #endif
  4311. bh_transmit(info);
  4312. }
  4313. /*
  4314. * receive buffer polling timer
  4315. */
  4316. static void rx_timeout(struct timer_list *t)
  4317. {
  4318. struct slgt_info *info = from_timer(info, t, rx_timer);
  4319. unsigned long flags;
  4320. DBGINFO(("%s rx_timeout\n", info->device_name));
  4321. spin_lock_irqsave(&info->lock, flags);
  4322. info->pending_bh |= BH_RECEIVE;
  4323. spin_unlock_irqrestore(&info->lock, flags);
  4324. bh_handler(&info->task);
  4325. }