synclink.c 223 KB

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  1. // SPDX-License-Identifier: GPL-1.0+
  2. /*
  3. * $Id: synclink.c,v 4.38 2005/11/07 16:30:34 paulkf Exp $
  4. *
  5. * Device driver for Microgate SyncLink ISA and PCI
  6. * high speed multiprotocol serial adapters.
  7. *
  8. * written by Paul Fulghum for Microgate Corporation
  9. * paulkf@microgate.com
  10. *
  11. * Microgate and SyncLink are trademarks of Microgate Corporation
  12. *
  13. * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
  14. *
  15. * Original release 01/11/99
  16. *
  17. * This driver is primarily intended for use in synchronous
  18. * HDLC mode. Asynchronous mode is also provided.
  19. *
  20. * When operating in synchronous mode, each call to mgsl_write()
  21. * contains exactly one complete HDLC frame. Calling mgsl_put_char
  22. * will start assembling an HDLC frame that will not be sent until
  23. * mgsl_flush_chars or mgsl_write is called.
  24. *
  25. * Synchronous receive data is reported as complete frames. To accomplish
  26. * this, the TTY flip buffer is bypassed (too small to hold largest
  27. * frame and may fragment frames) and the line discipline
  28. * receive entry point is called directly.
  29. *
  30. * This driver has been tested with a slightly modified ppp.c driver
  31. * for synchronous PPP.
  32. *
  33. * 2000/02/16
  34. * Added interface for syncppp.c driver (an alternate synchronous PPP
  35. * implementation that also supports Cisco HDLC). Each device instance
  36. * registers as a tty device AND a network device (if dosyncppp option
  37. * is set for the device). The functionality is determined by which
  38. * device interface is opened.
  39. *
  40. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  41. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  42. * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  43. * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  44. * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  45. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  46. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  47. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  48. * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  49. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  50. * OF THE POSSIBILITY OF SUCH DAMAGE.
  51. */
  52. #if defined(__i386__)
  53. # define BREAKPOINT() asm(" int $3");
  54. #else
  55. # define BREAKPOINT() { }
  56. #endif
  57. #define MAX_ISA_DEVICES 10
  58. #define MAX_PCI_DEVICES 10
  59. #define MAX_TOTAL_DEVICES 20
  60. #include <linux/module.h>
  61. #include <linux/errno.h>
  62. #include <linux/signal.h>
  63. #include <linux/sched.h>
  64. #include <linux/timer.h>
  65. #include <linux/interrupt.h>
  66. #include <linux/pci.h>
  67. #include <linux/tty.h>
  68. #include <linux/tty_flip.h>
  69. #include <linux/serial.h>
  70. #include <linux/major.h>
  71. #include <linux/string.h>
  72. #include <linux/fcntl.h>
  73. #include <linux/ptrace.h>
  74. #include <linux/ioport.h>
  75. #include <linux/mm.h>
  76. #include <linux/seq_file.h>
  77. #include <linux/slab.h>
  78. #include <linux/delay.h>
  79. #include <linux/netdevice.h>
  80. #include <linux/vmalloc.h>
  81. #include <linux/init.h>
  82. #include <linux/ioctl.h>
  83. #include <linux/synclink.h>
  84. #include <asm/io.h>
  85. #include <asm/irq.h>
  86. #include <asm/dma.h>
  87. #include <linux/bitops.h>
  88. #include <asm/types.h>
  89. #include <linux/termios.h>
  90. #include <linux/workqueue.h>
  91. #include <linux/hdlc.h>
  92. #include <linux/dma-mapping.h>
  93. #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_MODULE))
  94. #define SYNCLINK_GENERIC_HDLC 1
  95. #else
  96. #define SYNCLINK_GENERIC_HDLC 0
  97. #endif
  98. #define GET_USER(error,value,addr) error = get_user(value,addr)
  99. #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
  100. #define PUT_USER(error,value,addr) error = put_user(value,addr)
  101. #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
  102. #include <linux/uaccess.h>
  103. #define RCLRVALUE 0xffff
  104. static MGSL_PARAMS default_params = {
  105. MGSL_MODE_HDLC, /* unsigned long mode */
  106. 0, /* unsigned char loopback; */
  107. HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
  108. HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
  109. 0, /* unsigned long clock_speed; */
  110. 0xff, /* unsigned char addr_filter; */
  111. HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
  112. HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
  113. HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
  114. 9600, /* unsigned long data_rate; */
  115. 8, /* unsigned char data_bits; */
  116. 1, /* unsigned char stop_bits; */
  117. ASYNC_PARITY_NONE /* unsigned char parity; */
  118. };
  119. #define SHARED_MEM_ADDRESS_SIZE 0x40000
  120. #define BUFFERLISTSIZE 4096
  121. #define DMABUFFERSIZE 4096
  122. #define MAXRXFRAMES 7
  123. typedef struct _DMABUFFERENTRY
  124. {
  125. u32 phys_addr; /* 32-bit flat physical address of data buffer */
  126. volatile u16 count; /* buffer size/data count */
  127. volatile u16 status; /* Control/status field */
  128. volatile u16 rcc; /* character count field */
  129. u16 reserved; /* padding required by 16C32 */
  130. u32 link; /* 32-bit flat link to next buffer entry */
  131. char *virt_addr; /* virtual address of data buffer */
  132. u32 phys_entry; /* physical address of this buffer entry */
  133. dma_addr_t dma_addr;
  134. } DMABUFFERENTRY, *DMAPBUFFERENTRY;
  135. /* The queue of BH actions to be performed */
  136. #define BH_RECEIVE 1
  137. #define BH_TRANSMIT 2
  138. #define BH_STATUS 4
  139. #define IO_PIN_SHUTDOWN_LIMIT 100
  140. struct _input_signal_events {
  141. int ri_up;
  142. int ri_down;
  143. int dsr_up;
  144. int dsr_down;
  145. int dcd_up;
  146. int dcd_down;
  147. int cts_up;
  148. int cts_down;
  149. };
  150. /* transmit holding buffer definitions*/
  151. #define MAX_TX_HOLDING_BUFFERS 5
  152. struct tx_holding_buffer {
  153. int buffer_size;
  154. unsigned char * buffer;
  155. };
  156. /*
  157. * Device instance data structure
  158. */
  159. struct mgsl_struct {
  160. int magic;
  161. struct tty_port port;
  162. int line;
  163. int hw_version;
  164. struct mgsl_icount icount;
  165. int timeout;
  166. int x_char; /* xon/xoff character */
  167. u16 read_status_mask;
  168. u16 ignore_status_mask;
  169. unsigned char *xmit_buf;
  170. int xmit_head;
  171. int xmit_tail;
  172. int xmit_cnt;
  173. wait_queue_head_t status_event_wait_q;
  174. wait_queue_head_t event_wait_q;
  175. struct timer_list tx_timer; /* HDLC transmit timeout timer */
  176. struct mgsl_struct *next_device; /* device list link */
  177. spinlock_t irq_spinlock; /* spinlock for synchronizing with ISR */
  178. struct work_struct task; /* task structure for scheduling bh */
  179. u32 EventMask; /* event trigger mask */
  180. u32 RecordedEvents; /* pending events */
  181. u32 max_frame_size; /* as set by device config */
  182. u32 pending_bh;
  183. bool bh_running; /* Protection from multiple */
  184. int isr_overflow;
  185. bool bh_requested;
  186. int dcd_chkcount; /* check counts to prevent */
  187. int cts_chkcount; /* too many IRQs if a signal */
  188. int dsr_chkcount; /* is floating */
  189. int ri_chkcount;
  190. char *buffer_list; /* virtual address of Rx & Tx buffer lists */
  191. u32 buffer_list_phys;
  192. dma_addr_t buffer_list_dma_addr;
  193. unsigned int rx_buffer_count; /* count of total allocated Rx buffers */
  194. DMABUFFERENTRY *rx_buffer_list; /* list of receive buffer entries */
  195. unsigned int current_rx_buffer;
  196. int num_tx_dma_buffers; /* number of tx dma frames required */
  197. int tx_dma_buffers_used;
  198. unsigned int tx_buffer_count; /* count of total allocated Tx buffers */
  199. DMABUFFERENTRY *tx_buffer_list; /* list of transmit buffer entries */
  200. int start_tx_dma_buffer; /* tx dma buffer to start tx dma operation */
  201. int current_tx_buffer; /* next tx dma buffer to be loaded */
  202. unsigned char *intermediate_rxbuffer;
  203. int num_tx_holding_buffers; /* number of tx holding buffer allocated */
  204. int get_tx_holding_index; /* next tx holding buffer for adapter to load */
  205. int put_tx_holding_index; /* next tx holding buffer to store user request */
  206. int tx_holding_count; /* number of tx holding buffers waiting */
  207. struct tx_holding_buffer tx_holding_buffers[MAX_TX_HOLDING_BUFFERS];
  208. bool rx_enabled;
  209. bool rx_overflow;
  210. bool rx_rcc_underrun;
  211. bool tx_enabled;
  212. bool tx_active;
  213. u32 idle_mode;
  214. u16 cmr_value;
  215. u16 tcsr_value;
  216. char device_name[25]; /* device instance name */
  217. unsigned char bus; /* expansion bus number (zero based) */
  218. unsigned char function; /* PCI device number */
  219. unsigned int io_base; /* base I/O address of adapter */
  220. unsigned int io_addr_size; /* size of the I/O address range */
  221. bool io_addr_requested; /* true if I/O address requested */
  222. unsigned int irq_level; /* interrupt level */
  223. unsigned long irq_flags;
  224. bool irq_requested; /* true if IRQ requested */
  225. unsigned int dma_level; /* DMA channel */
  226. bool dma_requested; /* true if dma channel requested */
  227. u16 mbre_bit;
  228. u16 loopback_bits;
  229. u16 usc_idle_mode;
  230. MGSL_PARAMS params; /* communications parameters */
  231. unsigned char serial_signals; /* current serial signal states */
  232. bool irq_occurred; /* for diagnostics use */
  233. unsigned int init_error; /* Initialization startup error (DIAGS) */
  234. int fDiagnosticsmode; /* Driver in Diagnostic mode? (DIAGS) */
  235. u32 last_mem_alloc;
  236. unsigned char* memory_base; /* shared memory address (PCI only) */
  237. u32 phys_memory_base;
  238. bool shared_mem_requested;
  239. unsigned char* lcr_base; /* local config registers (PCI only) */
  240. u32 phys_lcr_base;
  241. u32 lcr_offset;
  242. bool lcr_mem_requested;
  243. u32 misc_ctrl_value;
  244. char *flag_buf;
  245. bool drop_rts_on_tx_done;
  246. bool loopmode_insert_requested;
  247. bool loopmode_send_done_requested;
  248. struct _input_signal_events input_signal_events;
  249. /* generic HDLC device parts */
  250. int netcount;
  251. spinlock_t netlock;
  252. #if SYNCLINK_GENERIC_HDLC
  253. struct net_device *netdev;
  254. #endif
  255. };
  256. #define MGSL_MAGIC 0x5401
  257. /*
  258. * The size of the serial xmit buffer is 1 page, or 4096 bytes
  259. */
  260. #ifndef SERIAL_XMIT_SIZE
  261. #define SERIAL_XMIT_SIZE 4096
  262. #endif
  263. /*
  264. * These macros define the offsets used in calculating the
  265. * I/O address of the specified USC registers.
  266. */
  267. #define DCPIN 2 /* Bit 1 of I/O address */
  268. #define SDPIN 4 /* Bit 2 of I/O address */
  269. #define DCAR 0 /* DMA command/address register */
  270. #define CCAR SDPIN /* channel command/address register */
  271. #define DATAREG DCPIN + SDPIN /* serial data register */
  272. #define MSBONLY 0x41
  273. #define LSBONLY 0x40
  274. /*
  275. * These macros define the register address (ordinal number)
  276. * used for writing address/value pairs to the USC.
  277. */
  278. #define CMR 0x02 /* Channel mode Register */
  279. #define CCSR 0x04 /* Channel Command/status Register */
  280. #define CCR 0x06 /* Channel Control Register */
  281. #define PSR 0x08 /* Port status Register */
  282. #define PCR 0x0a /* Port Control Register */
  283. #define TMDR 0x0c /* Test mode Data Register */
  284. #define TMCR 0x0e /* Test mode Control Register */
  285. #define CMCR 0x10 /* Clock mode Control Register */
  286. #define HCR 0x12 /* Hardware Configuration Register */
  287. #define IVR 0x14 /* Interrupt Vector Register */
  288. #define IOCR 0x16 /* Input/Output Control Register */
  289. #define ICR 0x18 /* Interrupt Control Register */
  290. #define DCCR 0x1a /* Daisy Chain Control Register */
  291. #define MISR 0x1c /* Misc Interrupt status Register */
  292. #define SICR 0x1e /* status Interrupt Control Register */
  293. #define RDR 0x20 /* Receive Data Register */
  294. #define RMR 0x22 /* Receive mode Register */
  295. #define RCSR 0x24 /* Receive Command/status Register */
  296. #define RICR 0x26 /* Receive Interrupt Control Register */
  297. #define RSR 0x28 /* Receive Sync Register */
  298. #define RCLR 0x2a /* Receive count Limit Register */
  299. #define RCCR 0x2c /* Receive Character count Register */
  300. #define TC0R 0x2e /* Time Constant 0 Register */
  301. #define TDR 0x30 /* Transmit Data Register */
  302. #define TMR 0x32 /* Transmit mode Register */
  303. #define TCSR 0x34 /* Transmit Command/status Register */
  304. #define TICR 0x36 /* Transmit Interrupt Control Register */
  305. #define TSR 0x38 /* Transmit Sync Register */
  306. #define TCLR 0x3a /* Transmit count Limit Register */
  307. #define TCCR 0x3c /* Transmit Character count Register */
  308. #define TC1R 0x3e /* Time Constant 1 Register */
  309. /*
  310. * MACRO DEFINITIONS FOR DMA REGISTERS
  311. */
  312. #define DCR 0x06 /* DMA Control Register (shared) */
  313. #define DACR 0x08 /* DMA Array count Register (shared) */
  314. #define BDCR 0x12 /* Burst/Dwell Control Register (shared) */
  315. #define DIVR 0x14 /* DMA Interrupt Vector Register (shared) */
  316. #define DICR 0x18 /* DMA Interrupt Control Register (shared) */
  317. #define CDIR 0x1a /* Clear DMA Interrupt Register (shared) */
  318. #define SDIR 0x1c /* Set DMA Interrupt Register (shared) */
  319. #define TDMR 0x02 /* Transmit DMA mode Register */
  320. #define TDIAR 0x1e /* Transmit DMA Interrupt Arm Register */
  321. #define TBCR 0x2a /* Transmit Byte count Register */
  322. #define TARL 0x2c /* Transmit Address Register (low) */
  323. #define TARU 0x2e /* Transmit Address Register (high) */
  324. #define NTBCR 0x3a /* Next Transmit Byte count Register */
  325. #define NTARL 0x3c /* Next Transmit Address Register (low) */
  326. #define NTARU 0x3e /* Next Transmit Address Register (high) */
  327. #define RDMR 0x82 /* Receive DMA mode Register (non-shared) */
  328. #define RDIAR 0x9e /* Receive DMA Interrupt Arm Register */
  329. #define RBCR 0xaa /* Receive Byte count Register */
  330. #define RARL 0xac /* Receive Address Register (low) */
  331. #define RARU 0xae /* Receive Address Register (high) */
  332. #define NRBCR 0xba /* Next Receive Byte count Register */
  333. #define NRARL 0xbc /* Next Receive Address Register (low) */
  334. #define NRARU 0xbe /* Next Receive Address Register (high) */
  335. /*
  336. * MACRO DEFINITIONS FOR MODEM STATUS BITS
  337. */
  338. #define MODEMSTATUS_DTR 0x80
  339. #define MODEMSTATUS_DSR 0x40
  340. #define MODEMSTATUS_RTS 0x20
  341. #define MODEMSTATUS_CTS 0x10
  342. #define MODEMSTATUS_RI 0x04
  343. #define MODEMSTATUS_DCD 0x01
  344. /*
  345. * Channel Command/Address Register (CCAR) Command Codes
  346. */
  347. #define RTCmd_Null 0x0000
  348. #define RTCmd_ResetHighestIus 0x1000
  349. #define RTCmd_TriggerChannelLoadDma 0x2000
  350. #define RTCmd_TriggerRxDma 0x2800
  351. #define RTCmd_TriggerTxDma 0x3000
  352. #define RTCmd_TriggerRxAndTxDma 0x3800
  353. #define RTCmd_PurgeRxFifo 0x4800
  354. #define RTCmd_PurgeTxFifo 0x5000
  355. #define RTCmd_PurgeRxAndTxFifo 0x5800
  356. #define RTCmd_LoadRcc 0x6800
  357. #define RTCmd_LoadTcc 0x7000
  358. #define RTCmd_LoadRccAndTcc 0x7800
  359. #define RTCmd_LoadTC0 0x8800
  360. #define RTCmd_LoadTC1 0x9000
  361. #define RTCmd_LoadTC0AndTC1 0x9800
  362. #define RTCmd_SerialDataLSBFirst 0xa000
  363. #define RTCmd_SerialDataMSBFirst 0xa800
  364. #define RTCmd_SelectBigEndian 0xb000
  365. #define RTCmd_SelectLittleEndian 0xb800
  366. /*
  367. * DMA Command/Address Register (DCAR) Command Codes
  368. */
  369. #define DmaCmd_Null 0x0000
  370. #define DmaCmd_ResetTxChannel 0x1000
  371. #define DmaCmd_ResetRxChannel 0x1200
  372. #define DmaCmd_StartTxChannel 0x2000
  373. #define DmaCmd_StartRxChannel 0x2200
  374. #define DmaCmd_ContinueTxChannel 0x3000
  375. #define DmaCmd_ContinueRxChannel 0x3200
  376. #define DmaCmd_PauseTxChannel 0x4000
  377. #define DmaCmd_PauseRxChannel 0x4200
  378. #define DmaCmd_AbortTxChannel 0x5000
  379. #define DmaCmd_AbortRxChannel 0x5200
  380. #define DmaCmd_InitTxChannel 0x7000
  381. #define DmaCmd_InitRxChannel 0x7200
  382. #define DmaCmd_ResetHighestDmaIus 0x8000
  383. #define DmaCmd_ResetAllChannels 0x9000
  384. #define DmaCmd_StartAllChannels 0xa000
  385. #define DmaCmd_ContinueAllChannels 0xb000
  386. #define DmaCmd_PauseAllChannels 0xc000
  387. #define DmaCmd_AbortAllChannels 0xd000
  388. #define DmaCmd_InitAllChannels 0xf000
  389. #define TCmd_Null 0x0000
  390. #define TCmd_ClearTxCRC 0x2000
  391. #define TCmd_SelectTicrTtsaData 0x4000
  392. #define TCmd_SelectTicrTxFifostatus 0x5000
  393. #define TCmd_SelectTicrIntLevel 0x6000
  394. #define TCmd_SelectTicrdma_level 0x7000
  395. #define TCmd_SendFrame 0x8000
  396. #define TCmd_SendAbort 0x9000
  397. #define TCmd_EnableDleInsertion 0xc000
  398. #define TCmd_DisableDleInsertion 0xd000
  399. #define TCmd_ClearEofEom 0xe000
  400. #define TCmd_SetEofEom 0xf000
  401. #define RCmd_Null 0x0000
  402. #define RCmd_ClearRxCRC 0x2000
  403. #define RCmd_EnterHuntmode 0x3000
  404. #define RCmd_SelectRicrRtsaData 0x4000
  405. #define RCmd_SelectRicrRxFifostatus 0x5000
  406. #define RCmd_SelectRicrIntLevel 0x6000
  407. #define RCmd_SelectRicrdma_level 0x7000
  408. /*
  409. * Bits for enabling and disabling IRQs in Interrupt Control Register (ICR)
  410. */
  411. #define RECEIVE_STATUS BIT5
  412. #define RECEIVE_DATA BIT4
  413. #define TRANSMIT_STATUS BIT3
  414. #define TRANSMIT_DATA BIT2
  415. #define IO_PIN BIT1
  416. #define MISC BIT0
  417. /*
  418. * Receive status Bits in Receive Command/status Register RCSR
  419. */
  420. #define RXSTATUS_SHORT_FRAME BIT8
  421. #define RXSTATUS_CODE_VIOLATION BIT8
  422. #define RXSTATUS_EXITED_HUNT BIT7
  423. #define RXSTATUS_IDLE_RECEIVED BIT6
  424. #define RXSTATUS_BREAK_RECEIVED BIT5
  425. #define RXSTATUS_ABORT_RECEIVED BIT5
  426. #define RXSTATUS_RXBOUND BIT4
  427. #define RXSTATUS_CRC_ERROR BIT3
  428. #define RXSTATUS_FRAMING_ERROR BIT3
  429. #define RXSTATUS_ABORT BIT2
  430. #define RXSTATUS_PARITY_ERROR BIT2
  431. #define RXSTATUS_OVERRUN BIT1
  432. #define RXSTATUS_DATA_AVAILABLE BIT0
  433. #define RXSTATUS_ALL 0x01f6
  434. #define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
  435. /*
  436. * Values for setting transmit idle mode in
  437. * Transmit Control/status Register (TCSR)
  438. */
  439. #define IDLEMODE_FLAGS 0x0000
  440. #define IDLEMODE_ALT_ONE_ZERO 0x0100
  441. #define IDLEMODE_ZERO 0x0200
  442. #define IDLEMODE_ONE 0x0300
  443. #define IDLEMODE_ALT_MARK_SPACE 0x0500
  444. #define IDLEMODE_SPACE 0x0600
  445. #define IDLEMODE_MARK 0x0700
  446. #define IDLEMODE_MASK 0x0700
  447. /*
  448. * IUSC revision identifiers
  449. */
  450. #define IUSC_SL1660 0x4d44
  451. #define IUSC_PRE_SL1660 0x4553
  452. /*
  453. * Transmit status Bits in Transmit Command/status Register (TCSR)
  454. */
  455. #define TCSR_PRESERVE 0x0F00
  456. #define TCSR_UNDERWAIT BIT11
  457. #define TXSTATUS_PREAMBLE_SENT BIT7
  458. #define TXSTATUS_IDLE_SENT BIT6
  459. #define TXSTATUS_ABORT_SENT BIT5
  460. #define TXSTATUS_EOF_SENT BIT4
  461. #define TXSTATUS_EOM_SENT BIT4
  462. #define TXSTATUS_CRC_SENT BIT3
  463. #define TXSTATUS_ALL_SENT BIT2
  464. #define TXSTATUS_UNDERRUN BIT1
  465. #define TXSTATUS_FIFO_EMPTY BIT0
  466. #define TXSTATUS_ALL 0x00fa
  467. #define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) )
  468. #define MISCSTATUS_RXC_LATCHED BIT15
  469. #define MISCSTATUS_RXC BIT14
  470. #define MISCSTATUS_TXC_LATCHED BIT13
  471. #define MISCSTATUS_TXC BIT12
  472. #define MISCSTATUS_RI_LATCHED BIT11
  473. #define MISCSTATUS_RI BIT10
  474. #define MISCSTATUS_DSR_LATCHED BIT9
  475. #define MISCSTATUS_DSR BIT8
  476. #define MISCSTATUS_DCD_LATCHED BIT7
  477. #define MISCSTATUS_DCD BIT6
  478. #define MISCSTATUS_CTS_LATCHED BIT5
  479. #define MISCSTATUS_CTS BIT4
  480. #define MISCSTATUS_RCC_UNDERRUN BIT3
  481. #define MISCSTATUS_DPLL_NO_SYNC BIT2
  482. #define MISCSTATUS_BRG1_ZERO BIT1
  483. #define MISCSTATUS_BRG0_ZERO BIT0
  484. #define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))
  485. #define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))
  486. #define SICR_RXC_ACTIVE BIT15
  487. #define SICR_RXC_INACTIVE BIT14
  488. #define SICR_RXC (BIT15|BIT14)
  489. #define SICR_TXC_ACTIVE BIT13
  490. #define SICR_TXC_INACTIVE BIT12
  491. #define SICR_TXC (BIT13|BIT12)
  492. #define SICR_RI_ACTIVE BIT11
  493. #define SICR_RI_INACTIVE BIT10
  494. #define SICR_RI (BIT11|BIT10)
  495. #define SICR_DSR_ACTIVE BIT9
  496. #define SICR_DSR_INACTIVE BIT8
  497. #define SICR_DSR (BIT9|BIT8)
  498. #define SICR_DCD_ACTIVE BIT7
  499. #define SICR_DCD_INACTIVE BIT6
  500. #define SICR_DCD (BIT7|BIT6)
  501. #define SICR_CTS_ACTIVE BIT5
  502. #define SICR_CTS_INACTIVE BIT4
  503. #define SICR_CTS (BIT5|BIT4)
  504. #define SICR_RCC_UNDERFLOW BIT3
  505. #define SICR_DPLL_NO_SYNC BIT2
  506. #define SICR_BRG1_ZERO BIT1
  507. #define SICR_BRG0_ZERO BIT0
  508. void usc_DisableMasterIrqBit( struct mgsl_struct *info );
  509. void usc_EnableMasterIrqBit( struct mgsl_struct *info );
  510. void usc_EnableInterrupts( struct mgsl_struct *info, u16 IrqMask );
  511. void usc_DisableInterrupts( struct mgsl_struct *info, u16 IrqMask );
  512. void usc_ClearIrqPendingBits( struct mgsl_struct *info, u16 IrqMask );
  513. #define usc_EnableInterrupts( a, b ) \
  514. usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
  515. #define usc_DisableInterrupts( a, b ) \
  516. usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
  517. #define usc_EnableMasterIrqBit(a) \
  518. usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
  519. #define usc_DisableMasterIrqBit(a) \
  520. usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
  521. #define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) )
  522. /*
  523. * Transmit status Bits in Transmit Control status Register (TCSR)
  524. * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0)
  525. */
  526. #define TXSTATUS_PREAMBLE_SENT BIT7
  527. #define TXSTATUS_IDLE_SENT BIT6
  528. #define TXSTATUS_ABORT_SENT BIT5
  529. #define TXSTATUS_EOF BIT4
  530. #define TXSTATUS_CRC_SENT BIT3
  531. #define TXSTATUS_ALL_SENT BIT2
  532. #define TXSTATUS_UNDERRUN BIT1
  533. #define TXSTATUS_FIFO_EMPTY BIT0
  534. #define DICR_MASTER BIT15
  535. #define DICR_TRANSMIT BIT0
  536. #define DICR_RECEIVE BIT1
  537. #define usc_EnableDmaInterrupts(a,b) \
  538. usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )
  539. #define usc_DisableDmaInterrupts(a,b) \
  540. usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )
  541. #define usc_EnableStatusIrqs(a,b) \
  542. usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
  543. #define usc_DisablestatusIrqs(a,b) \
  544. usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
  545. /* Transmit status Bits in Transmit Control status Register (TCSR) */
  546. /* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */
  547. #define DISABLE_UNCONDITIONAL 0
  548. #define DISABLE_END_OF_FRAME 1
  549. #define ENABLE_UNCONDITIONAL 2
  550. #define ENABLE_AUTO_CTS 3
  551. #define ENABLE_AUTO_DCD 3
  552. #define usc_EnableTransmitter(a,b) \
  553. usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
  554. #define usc_EnableReceiver(a,b) \
  555. usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
  556. static u16 usc_InDmaReg( struct mgsl_struct *info, u16 Port );
  557. static void usc_OutDmaReg( struct mgsl_struct *info, u16 Port, u16 Value );
  558. static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd );
  559. static u16 usc_InReg( struct mgsl_struct *info, u16 Port );
  560. static void usc_OutReg( struct mgsl_struct *info, u16 Port, u16 Value );
  561. static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd );
  562. void usc_RCmd( struct mgsl_struct *info, u16 Cmd );
  563. void usc_TCmd( struct mgsl_struct *info, u16 Cmd );
  564. #define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))
  565. #define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
  566. #define usc_SetTransmitSyncChars(a,s0,s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)|(u16)s1))
  567. static void usc_process_rxoverrun_sync( struct mgsl_struct *info );
  568. static void usc_start_receiver( struct mgsl_struct *info );
  569. static void usc_stop_receiver( struct mgsl_struct *info );
  570. static void usc_start_transmitter( struct mgsl_struct *info );
  571. static void usc_stop_transmitter( struct mgsl_struct *info );
  572. static void usc_set_txidle( struct mgsl_struct *info );
  573. static void usc_load_txfifo( struct mgsl_struct *info );
  574. static void usc_enable_aux_clock( struct mgsl_struct *info, u32 DataRate );
  575. static void usc_enable_loopback( struct mgsl_struct *info, int enable );
  576. static void usc_get_serial_signals( struct mgsl_struct *info );
  577. static void usc_set_serial_signals( struct mgsl_struct *info );
  578. static void usc_reset( struct mgsl_struct *info );
  579. static void usc_set_sync_mode( struct mgsl_struct *info );
  580. static void usc_set_sdlc_mode( struct mgsl_struct *info );
  581. static void usc_set_async_mode( struct mgsl_struct *info );
  582. static void usc_enable_async_clock( struct mgsl_struct *info, u32 DataRate );
  583. static void usc_loopback_frame( struct mgsl_struct *info );
  584. static void mgsl_tx_timeout(struct timer_list *t);
  585. static void usc_loopmode_cancel_transmit( struct mgsl_struct * info );
  586. static void usc_loopmode_insert_request( struct mgsl_struct * info );
  587. static int usc_loopmode_active( struct mgsl_struct * info);
  588. static void usc_loopmode_send_done( struct mgsl_struct * info );
  589. static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg);
  590. #if SYNCLINK_GENERIC_HDLC
  591. #define dev_to_port(D) (dev_to_hdlc(D)->priv)
  592. static void hdlcdev_tx_done(struct mgsl_struct *info);
  593. static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size);
  594. static int hdlcdev_init(struct mgsl_struct *info);
  595. static void hdlcdev_exit(struct mgsl_struct *info);
  596. #endif
  597. /*
  598. * Defines a BUS descriptor value for the PCI adapter
  599. * local bus address ranges.
  600. */
  601. #define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \
  602. (0x00400020 + \
  603. ((WrHold) << 30) + \
  604. ((WrDly) << 28) + \
  605. ((RdDly) << 26) + \
  606. ((Nwdd) << 20) + \
  607. ((Nwad) << 15) + \
  608. ((Nxda) << 13) + \
  609. ((Nrdd) << 11) + \
  610. ((Nrad) << 6) )
  611. static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit);
  612. /*
  613. * Adapter diagnostic routines
  614. */
  615. static bool mgsl_register_test( struct mgsl_struct *info );
  616. static bool mgsl_irq_test( struct mgsl_struct *info );
  617. static bool mgsl_dma_test( struct mgsl_struct *info );
  618. static bool mgsl_memory_test( struct mgsl_struct *info );
  619. static int mgsl_adapter_test( struct mgsl_struct *info );
  620. /*
  621. * device and resource management routines
  622. */
  623. static int mgsl_claim_resources(struct mgsl_struct *info);
  624. static void mgsl_release_resources(struct mgsl_struct *info);
  625. static void mgsl_add_device(struct mgsl_struct *info);
  626. static struct mgsl_struct* mgsl_allocate_device(void);
  627. /*
  628. * DMA buffer manupulation functions.
  629. */
  630. static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex );
  631. static bool mgsl_get_rx_frame( struct mgsl_struct *info );
  632. static bool mgsl_get_raw_rx_frame( struct mgsl_struct *info );
  633. static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info );
  634. static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info );
  635. static int num_free_tx_dma_buffers(struct mgsl_struct *info);
  636. static void mgsl_load_tx_dma_buffer( struct mgsl_struct *info, const char *Buffer, unsigned int BufferSize);
  637. static void mgsl_load_pci_memory(char* TargetPtr, const char* SourcePtr, unsigned short count);
  638. /*
  639. * DMA and Shared Memory buffer allocation and formatting
  640. */
  641. static int mgsl_allocate_dma_buffers(struct mgsl_struct *info);
  642. static void mgsl_free_dma_buffers(struct mgsl_struct *info);
  643. static int mgsl_alloc_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
  644. static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
  645. static int mgsl_alloc_buffer_list_memory(struct mgsl_struct *info);
  646. static void mgsl_free_buffer_list_memory(struct mgsl_struct *info);
  647. static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info);
  648. static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info);
  649. static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info);
  650. static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info);
  651. static bool load_next_tx_holding_buffer(struct mgsl_struct *info);
  652. static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize);
  653. /*
  654. * Bottom half interrupt handlers
  655. */
  656. static void mgsl_bh_handler(struct work_struct *work);
  657. static void mgsl_bh_receive(struct mgsl_struct *info);
  658. static void mgsl_bh_transmit(struct mgsl_struct *info);
  659. static void mgsl_bh_status(struct mgsl_struct *info);
  660. /*
  661. * Interrupt handler routines and dispatch table.
  662. */
  663. static void mgsl_isr_null( struct mgsl_struct *info );
  664. static void mgsl_isr_transmit_data( struct mgsl_struct *info );
  665. static void mgsl_isr_receive_data( struct mgsl_struct *info );
  666. static void mgsl_isr_receive_status( struct mgsl_struct *info );
  667. static void mgsl_isr_transmit_status( struct mgsl_struct *info );
  668. static void mgsl_isr_io_pin( struct mgsl_struct *info );
  669. static void mgsl_isr_misc( struct mgsl_struct *info );
  670. static void mgsl_isr_receive_dma( struct mgsl_struct *info );
  671. static void mgsl_isr_transmit_dma( struct mgsl_struct *info );
  672. typedef void (*isr_dispatch_func)(struct mgsl_struct *);
  673. static isr_dispatch_func UscIsrTable[7] =
  674. {
  675. mgsl_isr_null,
  676. mgsl_isr_misc,
  677. mgsl_isr_io_pin,
  678. mgsl_isr_transmit_data,
  679. mgsl_isr_transmit_status,
  680. mgsl_isr_receive_data,
  681. mgsl_isr_receive_status
  682. };
  683. /*
  684. * ioctl call handlers
  685. */
  686. static int tiocmget(struct tty_struct *tty);
  687. static int tiocmset(struct tty_struct *tty,
  688. unsigned int set, unsigned int clear);
  689. static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount
  690. __user *user_icount);
  691. static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params);
  692. static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params);
  693. static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode);
  694. static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode);
  695. static int mgsl_txenable(struct mgsl_struct * info, int enable);
  696. static int mgsl_txabort(struct mgsl_struct * info);
  697. static int mgsl_rxenable(struct mgsl_struct * info, int enable);
  698. static int mgsl_wait_event(struct mgsl_struct * info, int __user *mask);
  699. static int mgsl_loopmode_send_done( struct mgsl_struct * info );
  700. /* set non-zero on successful registration with PCI subsystem */
  701. static bool pci_registered;
  702. /*
  703. * Global linked list of SyncLink devices
  704. */
  705. static struct mgsl_struct *mgsl_device_list;
  706. static int mgsl_device_count;
  707. /*
  708. * Set this param to non-zero to load eax with the
  709. * .text section address and breakpoint on module load.
  710. * This is useful for use with gdb and add-symbol-file command.
  711. */
  712. static bool break_on_load;
  713. /*
  714. * Driver major number, defaults to zero to get auto
  715. * assigned major number. May be forced as module parameter.
  716. */
  717. static int ttymajor;
  718. /*
  719. * Array of user specified options for ISA adapters.
  720. */
  721. static int io[MAX_ISA_DEVICES];
  722. static int irq[MAX_ISA_DEVICES];
  723. static int dma[MAX_ISA_DEVICES];
  724. static int debug_level;
  725. static int maxframe[MAX_TOTAL_DEVICES];
  726. static int txdmabufs[MAX_TOTAL_DEVICES];
  727. static int txholdbufs[MAX_TOTAL_DEVICES];
  728. module_param(break_on_load, bool, 0);
  729. module_param(ttymajor, int, 0);
  730. module_param_hw_array(io, int, ioport, NULL, 0);
  731. module_param_hw_array(irq, int, irq, NULL, 0);
  732. module_param_hw_array(dma, int, dma, NULL, 0);
  733. module_param(debug_level, int, 0);
  734. module_param_array(maxframe, int, NULL, 0);
  735. module_param_array(txdmabufs, int, NULL, 0);
  736. module_param_array(txholdbufs, int, NULL, 0);
  737. static char *driver_name = "SyncLink serial driver";
  738. static char *driver_version = "$Revision: 4.38 $";
  739. static int synclink_init_one (struct pci_dev *dev,
  740. const struct pci_device_id *ent);
  741. static void synclink_remove_one (struct pci_dev *dev);
  742. static const struct pci_device_id synclink_pci_tbl[] = {
  743. { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_USC, PCI_ANY_ID, PCI_ANY_ID, },
  744. { PCI_VENDOR_ID_MICROGATE, 0x0210, PCI_ANY_ID, PCI_ANY_ID, },
  745. { 0, }, /* terminate list */
  746. };
  747. MODULE_DEVICE_TABLE(pci, synclink_pci_tbl);
  748. MODULE_LICENSE("GPL");
  749. static struct pci_driver synclink_pci_driver = {
  750. .name = "synclink",
  751. .id_table = synclink_pci_tbl,
  752. .probe = synclink_init_one,
  753. .remove = synclink_remove_one,
  754. };
  755. static struct tty_driver *serial_driver;
  756. /* number of characters left in xmit buffer before we ask for more */
  757. #define WAKEUP_CHARS 256
  758. static void mgsl_change_params(struct mgsl_struct *info);
  759. static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout);
  760. /*
  761. * 1st function defined in .text section. Calling this function in
  762. * init_module() followed by a breakpoint allows a remote debugger
  763. * (gdb) to get the .text address for the add-symbol-file command.
  764. * This allows remote debugging of dynamically loadable modules.
  765. */
  766. static void* mgsl_get_text_ptr(void)
  767. {
  768. return mgsl_get_text_ptr;
  769. }
  770. static inline int mgsl_paranoia_check(struct mgsl_struct *info,
  771. char *name, const char *routine)
  772. {
  773. #ifdef MGSL_PARANOIA_CHECK
  774. static const char *badmagic =
  775. "Warning: bad magic number for mgsl struct (%s) in %s\n";
  776. static const char *badinfo =
  777. "Warning: null mgsl_struct for (%s) in %s\n";
  778. if (!info) {
  779. printk(badinfo, name, routine);
  780. return 1;
  781. }
  782. if (info->magic != MGSL_MAGIC) {
  783. printk(badmagic, name, routine);
  784. return 1;
  785. }
  786. #else
  787. if (!info)
  788. return 1;
  789. #endif
  790. return 0;
  791. }
  792. /*
  793. * line discipline callback wrappers
  794. *
  795. * The wrappers maintain line discipline references
  796. * while calling into the line discipline.
  797. *
  798. * ldisc_receive_buf - pass receive data to line discipline
  799. */
  800. static void ldisc_receive_buf(struct tty_struct *tty,
  801. const __u8 *data, char *flags, int count)
  802. {
  803. struct tty_ldisc *ld;
  804. if (!tty)
  805. return;
  806. ld = tty_ldisc_ref(tty);
  807. if (ld) {
  808. if (ld->ops->receive_buf)
  809. ld->ops->receive_buf(tty, data, flags, count);
  810. tty_ldisc_deref(ld);
  811. }
  812. }
  813. /* mgsl_stop() throttle (stop) transmitter
  814. *
  815. * Arguments: tty pointer to tty info structure
  816. * Return Value: None
  817. */
  818. static void mgsl_stop(struct tty_struct *tty)
  819. {
  820. struct mgsl_struct *info = tty->driver_data;
  821. unsigned long flags;
  822. if (mgsl_paranoia_check(info, tty->name, "mgsl_stop"))
  823. return;
  824. if ( debug_level >= DEBUG_LEVEL_INFO )
  825. printk("mgsl_stop(%s)\n",info->device_name);
  826. spin_lock_irqsave(&info->irq_spinlock,flags);
  827. if (info->tx_enabled)
  828. usc_stop_transmitter(info);
  829. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  830. } /* end of mgsl_stop() */
  831. /* mgsl_start() release (start) transmitter
  832. *
  833. * Arguments: tty pointer to tty info structure
  834. * Return Value: None
  835. */
  836. static void mgsl_start(struct tty_struct *tty)
  837. {
  838. struct mgsl_struct *info = tty->driver_data;
  839. unsigned long flags;
  840. if (mgsl_paranoia_check(info, tty->name, "mgsl_start"))
  841. return;
  842. if ( debug_level >= DEBUG_LEVEL_INFO )
  843. printk("mgsl_start(%s)\n",info->device_name);
  844. spin_lock_irqsave(&info->irq_spinlock,flags);
  845. if (!info->tx_enabled)
  846. usc_start_transmitter(info);
  847. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  848. } /* end of mgsl_start() */
  849. /*
  850. * Bottom half work queue access functions
  851. */
  852. /* mgsl_bh_action() Return next bottom half action to perform.
  853. * Return Value: BH action code or 0 if nothing to do.
  854. */
  855. static int mgsl_bh_action(struct mgsl_struct *info)
  856. {
  857. unsigned long flags;
  858. int rc = 0;
  859. spin_lock_irqsave(&info->irq_spinlock,flags);
  860. if (info->pending_bh & BH_RECEIVE) {
  861. info->pending_bh &= ~BH_RECEIVE;
  862. rc = BH_RECEIVE;
  863. } else if (info->pending_bh & BH_TRANSMIT) {
  864. info->pending_bh &= ~BH_TRANSMIT;
  865. rc = BH_TRANSMIT;
  866. } else if (info->pending_bh & BH_STATUS) {
  867. info->pending_bh &= ~BH_STATUS;
  868. rc = BH_STATUS;
  869. }
  870. if (!rc) {
  871. /* Mark BH routine as complete */
  872. info->bh_running = false;
  873. info->bh_requested = false;
  874. }
  875. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  876. return rc;
  877. }
  878. /*
  879. * Perform bottom half processing of work items queued by ISR.
  880. */
  881. static void mgsl_bh_handler(struct work_struct *work)
  882. {
  883. struct mgsl_struct *info =
  884. container_of(work, struct mgsl_struct, task);
  885. int action;
  886. if ( debug_level >= DEBUG_LEVEL_BH )
  887. printk( "%s(%d):mgsl_bh_handler(%s) entry\n",
  888. __FILE__,__LINE__,info->device_name);
  889. info->bh_running = true;
  890. while((action = mgsl_bh_action(info)) != 0) {
  891. /* Process work item */
  892. if ( debug_level >= DEBUG_LEVEL_BH )
  893. printk( "%s(%d):mgsl_bh_handler() work item action=%d\n",
  894. __FILE__,__LINE__,action);
  895. switch (action) {
  896. case BH_RECEIVE:
  897. mgsl_bh_receive(info);
  898. break;
  899. case BH_TRANSMIT:
  900. mgsl_bh_transmit(info);
  901. break;
  902. case BH_STATUS:
  903. mgsl_bh_status(info);
  904. break;
  905. default:
  906. /* unknown work item ID */
  907. printk("Unknown work item ID=%08X!\n", action);
  908. break;
  909. }
  910. }
  911. if ( debug_level >= DEBUG_LEVEL_BH )
  912. printk( "%s(%d):mgsl_bh_handler(%s) exit\n",
  913. __FILE__,__LINE__,info->device_name);
  914. }
  915. static void mgsl_bh_receive(struct mgsl_struct *info)
  916. {
  917. bool (*get_rx_frame)(struct mgsl_struct *info) =
  918. (info->params.mode == MGSL_MODE_HDLC ? mgsl_get_rx_frame : mgsl_get_raw_rx_frame);
  919. if ( debug_level >= DEBUG_LEVEL_BH )
  920. printk( "%s(%d):mgsl_bh_receive(%s)\n",
  921. __FILE__,__LINE__,info->device_name);
  922. do
  923. {
  924. if (info->rx_rcc_underrun) {
  925. unsigned long flags;
  926. spin_lock_irqsave(&info->irq_spinlock,flags);
  927. usc_start_receiver(info);
  928. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  929. return;
  930. }
  931. } while(get_rx_frame(info));
  932. }
  933. static void mgsl_bh_transmit(struct mgsl_struct *info)
  934. {
  935. struct tty_struct *tty = info->port.tty;
  936. unsigned long flags;
  937. if ( debug_level >= DEBUG_LEVEL_BH )
  938. printk( "%s(%d):mgsl_bh_transmit() entry on %s\n",
  939. __FILE__,__LINE__,info->device_name);
  940. if (tty)
  941. tty_wakeup(tty);
  942. /* if transmitter idle and loopmode_send_done_requested
  943. * then start echoing RxD to TxD
  944. */
  945. spin_lock_irqsave(&info->irq_spinlock,flags);
  946. if ( !info->tx_active && info->loopmode_send_done_requested )
  947. usc_loopmode_send_done( info );
  948. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  949. }
  950. static void mgsl_bh_status(struct mgsl_struct *info)
  951. {
  952. if ( debug_level >= DEBUG_LEVEL_BH )
  953. printk( "%s(%d):mgsl_bh_status() entry on %s\n",
  954. __FILE__,__LINE__,info->device_name);
  955. info->ri_chkcount = 0;
  956. info->dsr_chkcount = 0;
  957. info->dcd_chkcount = 0;
  958. info->cts_chkcount = 0;
  959. }
  960. /* mgsl_isr_receive_status()
  961. *
  962. * Service a receive status interrupt. The type of status
  963. * interrupt is indicated by the state of the RCSR.
  964. * This is only used for HDLC mode.
  965. *
  966. * Arguments: info pointer to device instance data
  967. * Return Value: None
  968. */
  969. static void mgsl_isr_receive_status( struct mgsl_struct *info )
  970. {
  971. u16 status = usc_InReg( info, RCSR );
  972. if ( debug_level >= DEBUG_LEVEL_ISR )
  973. printk("%s(%d):mgsl_isr_receive_status status=%04X\n",
  974. __FILE__,__LINE__,status);
  975. if ( (status & RXSTATUS_ABORT_RECEIVED) &&
  976. info->loopmode_insert_requested &&
  977. usc_loopmode_active(info) )
  978. {
  979. ++info->icount.rxabort;
  980. info->loopmode_insert_requested = false;
  981. /* clear CMR:13 to start echoing RxD to TxD */
  982. info->cmr_value &= ~BIT13;
  983. usc_OutReg(info, CMR, info->cmr_value);
  984. /* disable received abort irq (no longer required) */
  985. usc_OutReg(info, RICR,
  986. (usc_InReg(info, RICR) & ~RXSTATUS_ABORT_RECEIVED));
  987. }
  988. if (status & (RXSTATUS_EXITED_HUNT | RXSTATUS_IDLE_RECEIVED)) {
  989. if (status & RXSTATUS_EXITED_HUNT)
  990. info->icount.exithunt++;
  991. if (status & RXSTATUS_IDLE_RECEIVED)
  992. info->icount.rxidle++;
  993. wake_up_interruptible(&info->event_wait_q);
  994. }
  995. if (status & RXSTATUS_OVERRUN){
  996. info->icount.rxover++;
  997. usc_process_rxoverrun_sync( info );
  998. }
  999. usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
  1000. usc_UnlatchRxstatusBits( info, status );
  1001. } /* end of mgsl_isr_receive_status() */
  1002. /* mgsl_isr_transmit_status()
  1003. *
  1004. * Service a transmit status interrupt
  1005. * HDLC mode :end of transmit frame
  1006. * Async mode:all data is sent
  1007. * transmit status is indicated by bits in the TCSR.
  1008. *
  1009. * Arguments: info pointer to device instance data
  1010. * Return Value: None
  1011. */
  1012. static void mgsl_isr_transmit_status( struct mgsl_struct *info )
  1013. {
  1014. u16 status = usc_InReg( info, TCSR );
  1015. if ( debug_level >= DEBUG_LEVEL_ISR )
  1016. printk("%s(%d):mgsl_isr_transmit_status status=%04X\n",
  1017. __FILE__,__LINE__,status);
  1018. usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
  1019. usc_UnlatchTxstatusBits( info, status );
  1020. if ( status & (TXSTATUS_UNDERRUN | TXSTATUS_ABORT_SENT) )
  1021. {
  1022. /* finished sending HDLC abort. This may leave */
  1023. /* the TxFifo with data from the aborted frame */
  1024. /* so purge the TxFifo. Also shutdown the DMA */
  1025. /* channel in case there is data remaining in */
  1026. /* the DMA buffer */
  1027. usc_DmaCmd( info, DmaCmd_ResetTxChannel );
  1028. usc_RTCmd( info, RTCmd_PurgeTxFifo );
  1029. }
  1030. if ( status & TXSTATUS_EOF_SENT )
  1031. info->icount.txok++;
  1032. else if ( status & TXSTATUS_UNDERRUN )
  1033. info->icount.txunder++;
  1034. else if ( status & TXSTATUS_ABORT_SENT )
  1035. info->icount.txabort++;
  1036. else
  1037. info->icount.txunder++;
  1038. info->tx_active = false;
  1039. info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
  1040. del_timer(&info->tx_timer);
  1041. if ( info->drop_rts_on_tx_done ) {
  1042. usc_get_serial_signals( info );
  1043. if ( info->serial_signals & SerialSignal_RTS ) {
  1044. info->serial_signals &= ~SerialSignal_RTS;
  1045. usc_set_serial_signals( info );
  1046. }
  1047. info->drop_rts_on_tx_done = false;
  1048. }
  1049. #if SYNCLINK_GENERIC_HDLC
  1050. if (info->netcount)
  1051. hdlcdev_tx_done(info);
  1052. else
  1053. #endif
  1054. {
  1055. if (info->port.tty->stopped || info->port.tty->hw_stopped) {
  1056. usc_stop_transmitter(info);
  1057. return;
  1058. }
  1059. info->pending_bh |= BH_TRANSMIT;
  1060. }
  1061. } /* end of mgsl_isr_transmit_status() */
  1062. /* mgsl_isr_io_pin()
  1063. *
  1064. * Service an Input/Output pin interrupt. The type of
  1065. * interrupt is indicated by bits in the MISR
  1066. *
  1067. * Arguments: info pointer to device instance data
  1068. * Return Value: None
  1069. */
  1070. static void mgsl_isr_io_pin( struct mgsl_struct *info )
  1071. {
  1072. struct mgsl_icount *icount;
  1073. u16 status = usc_InReg( info, MISR );
  1074. if ( debug_level >= DEBUG_LEVEL_ISR )
  1075. printk("%s(%d):mgsl_isr_io_pin status=%04X\n",
  1076. __FILE__,__LINE__,status);
  1077. usc_ClearIrqPendingBits( info, IO_PIN );
  1078. usc_UnlatchIostatusBits( info, status );
  1079. if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
  1080. MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
  1081. icount = &info->icount;
  1082. /* update input line counters */
  1083. if (status & MISCSTATUS_RI_LATCHED) {
  1084. if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  1085. usc_DisablestatusIrqs(info,SICR_RI);
  1086. icount->rng++;
  1087. if ( status & MISCSTATUS_RI )
  1088. info->input_signal_events.ri_up++;
  1089. else
  1090. info->input_signal_events.ri_down++;
  1091. }
  1092. if (status & MISCSTATUS_DSR_LATCHED) {
  1093. if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  1094. usc_DisablestatusIrqs(info,SICR_DSR);
  1095. icount->dsr++;
  1096. if ( status & MISCSTATUS_DSR )
  1097. info->input_signal_events.dsr_up++;
  1098. else
  1099. info->input_signal_events.dsr_down++;
  1100. }
  1101. if (status & MISCSTATUS_DCD_LATCHED) {
  1102. if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  1103. usc_DisablestatusIrqs(info,SICR_DCD);
  1104. icount->dcd++;
  1105. if (status & MISCSTATUS_DCD) {
  1106. info->input_signal_events.dcd_up++;
  1107. } else
  1108. info->input_signal_events.dcd_down++;
  1109. #if SYNCLINK_GENERIC_HDLC
  1110. if (info->netcount) {
  1111. if (status & MISCSTATUS_DCD)
  1112. netif_carrier_on(info->netdev);
  1113. else
  1114. netif_carrier_off(info->netdev);
  1115. }
  1116. #endif
  1117. }
  1118. if (status & MISCSTATUS_CTS_LATCHED)
  1119. {
  1120. if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  1121. usc_DisablestatusIrqs(info,SICR_CTS);
  1122. icount->cts++;
  1123. if ( status & MISCSTATUS_CTS )
  1124. info->input_signal_events.cts_up++;
  1125. else
  1126. info->input_signal_events.cts_down++;
  1127. }
  1128. wake_up_interruptible(&info->status_event_wait_q);
  1129. wake_up_interruptible(&info->event_wait_q);
  1130. if (tty_port_check_carrier(&info->port) &&
  1131. (status & MISCSTATUS_DCD_LATCHED) ) {
  1132. if ( debug_level >= DEBUG_LEVEL_ISR )
  1133. printk("%s CD now %s...", info->device_name,
  1134. (status & MISCSTATUS_DCD) ? "on" : "off");
  1135. if (status & MISCSTATUS_DCD)
  1136. wake_up_interruptible(&info->port.open_wait);
  1137. else {
  1138. if ( debug_level >= DEBUG_LEVEL_ISR )
  1139. printk("doing serial hangup...");
  1140. if (info->port.tty)
  1141. tty_hangup(info->port.tty);
  1142. }
  1143. }
  1144. if (tty_port_cts_enabled(&info->port) &&
  1145. (status & MISCSTATUS_CTS_LATCHED) ) {
  1146. if (info->port.tty->hw_stopped) {
  1147. if (status & MISCSTATUS_CTS) {
  1148. if ( debug_level >= DEBUG_LEVEL_ISR )
  1149. printk("CTS tx start...");
  1150. info->port.tty->hw_stopped = 0;
  1151. usc_start_transmitter(info);
  1152. info->pending_bh |= BH_TRANSMIT;
  1153. return;
  1154. }
  1155. } else {
  1156. if (!(status & MISCSTATUS_CTS)) {
  1157. if ( debug_level >= DEBUG_LEVEL_ISR )
  1158. printk("CTS tx stop...");
  1159. if (info->port.tty)
  1160. info->port.tty->hw_stopped = 1;
  1161. usc_stop_transmitter(info);
  1162. }
  1163. }
  1164. }
  1165. }
  1166. info->pending_bh |= BH_STATUS;
  1167. /* for diagnostics set IRQ flag */
  1168. if ( status & MISCSTATUS_TXC_LATCHED ){
  1169. usc_OutReg( info, SICR,
  1170. (unsigned short)(usc_InReg(info,SICR) & ~(SICR_TXC_ACTIVE+SICR_TXC_INACTIVE)) );
  1171. usc_UnlatchIostatusBits( info, MISCSTATUS_TXC_LATCHED );
  1172. info->irq_occurred = true;
  1173. }
  1174. } /* end of mgsl_isr_io_pin() */
  1175. /* mgsl_isr_transmit_data()
  1176. *
  1177. * Service a transmit data interrupt (async mode only).
  1178. *
  1179. * Arguments: info pointer to device instance data
  1180. * Return Value: None
  1181. */
  1182. static void mgsl_isr_transmit_data( struct mgsl_struct *info )
  1183. {
  1184. if ( debug_level >= DEBUG_LEVEL_ISR )
  1185. printk("%s(%d):mgsl_isr_transmit_data xmit_cnt=%d\n",
  1186. __FILE__,__LINE__,info->xmit_cnt);
  1187. usc_ClearIrqPendingBits( info, TRANSMIT_DATA );
  1188. if (info->port.tty->stopped || info->port.tty->hw_stopped) {
  1189. usc_stop_transmitter(info);
  1190. return;
  1191. }
  1192. if ( info->xmit_cnt )
  1193. usc_load_txfifo( info );
  1194. else
  1195. info->tx_active = false;
  1196. if (info->xmit_cnt < WAKEUP_CHARS)
  1197. info->pending_bh |= BH_TRANSMIT;
  1198. } /* end of mgsl_isr_transmit_data() */
  1199. /* mgsl_isr_receive_data()
  1200. *
  1201. * Service a receive data interrupt. This occurs
  1202. * when operating in asynchronous interrupt transfer mode.
  1203. * The receive data FIFO is flushed to the receive data buffers.
  1204. *
  1205. * Arguments: info pointer to device instance data
  1206. * Return Value: None
  1207. */
  1208. static void mgsl_isr_receive_data( struct mgsl_struct *info )
  1209. {
  1210. int Fifocount;
  1211. u16 status;
  1212. int work = 0;
  1213. unsigned char DataByte;
  1214. struct mgsl_icount *icount = &info->icount;
  1215. if ( debug_level >= DEBUG_LEVEL_ISR )
  1216. printk("%s(%d):mgsl_isr_receive_data\n",
  1217. __FILE__,__LINE__);
  1218. usc_ClearIrqPendingBits( info, RECEIVE_DATA );
  1219. /* select FIFO status for RICR readback */
  1220. usc_RCmd( info, RCmd_SelectRicrRxFifostatus );
  1221. /* clear the Wordstatus bit so that status readback */
  1222. /* only reflects the status of this byte */
  1223. usc_OutReg( info, RICR+LSBONLY, (u16)(usc_InReg(info, RICR+LSBONLY) & ~BIT3 ));
  1224. /* flush the receive FIFO */
  1225. while( (Fifocount = (usc_InReg(info,RICR) >> 8)) ) {
  1226. int flag;
  1227. /* read one byte from RxFIFO */
  1228. outw( (inw(info->io_base + CCAR) & 0x0780) | (RDR+LSBONLY),
  1229. info->io_base + CCAR );
  1230. DataByte = inb( info->io_base + CCAR );
  1231. /* get the status of the received byte */
  1232. status = usc_InReg(info, RCSR);
  1233. if ( status & (RXSTATUS_FRAMING_ERROR | RXSTATUS_PARITY_ERROR |
  1234. RXSTATUS_OVERRUN | RXSTATUS_BREAK_RECEIVED) )
  1235. usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
  1236. icount->rx++;
  1237. flag = 0;
  1238. if ( status & (RXSTATUS_FRAMING_ERROR | RXSTATUS_PARITY_ERROR |
  1239. RXSTATUS_OVERRUN | RXSTATUS_BREAK_RECEIVED) ) {
  1240. printk("rxerr=%04X\n",status);
  1241. /* update error statistics */
  1242. if ( status & RXSTATUS_BREAK_RECEIVED ) {
  1243. status &= ~(RXSTATUS_FRAMING_ERROR | RXSTATUS_PARITY_ERROR);
  1244. icount->brk++;
  1245. } else if (status & RXSTATUS_PARITY_ERROR)
  1246. icount->parity++;
  1247. else if (status & RXSTATUS_FRAMING_ERROR)
  1248. icount->frame++;
  1249. else if (status & RXSTATUS_OVERRUN) {
  1250. /* must issue purge fifo cmd before */
  1251. /* 16C32 accepts more receive chars */
  1252. usc_RTCmd(info,RTCmd_PurgeRxFifo);
  1253. icount->overrun++;
  1254. }
  1255. /* discard char if tty control flags say so */
  1256. if (status & info->ignore_status_mask)
  1257. continue;
  1258. status &= info->read_status_mask;
  1259. if (status & RXSTATUS_BREAK_RECEIVED) {
  1260. flag = TTY_BREAK;
  1261. if (info->port.flags & ASYNC_SAK)
  1262. do_SAK(info->port.tty);
  1263. } else if (status & RXSTATUS_PARITY_ERROR)
  1264. flag = TTY_PARITY;
  1265. else if (status & RXSTATUS_FRAMING_ERROR)
  1266. flag = TTY_FRAME;
  1267. } /* end of if (error) */
  1268. tty_insert_flip_char(&info->port, DataByte, flag);
  1269. if (status & RXSTATUS_OVERRUN) {
  1270. /* Overrun is special, since it's
  1271. * reported immediately, and doesn't
  1272. * affect the current character
  1273. */
  1274. work += tty_insert_flip_char(&info->port, 0, TTY_OVERRUN);
  1275. }
  1276. }
  1277. if ( debug_level >= DEBUG_LEVEL_ISR ) {
  1278. printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
  1279. __FILE__,__LINE__,icount->rx,icount->brk,
  1280. icount->parity,icount->frame,icount->overrun);
  1281. }
  1282. if(work)
  1283. tty_flip_buffer_push(&info->port);
  1284. }
  1285. /* mgsl_isr_misc()
  1286. *
  1287. * Service a miscellaneous interrupt source.
  1288. *
  1289. * Arguments: info pointer to device extension (instance data)
  1290. * Return Value: None
  1291. */
  1292. static void mgsl_isr_misc( struct mgsl_struct *info )
  1293. {
  1294. u16 status = usc_InReg( info, MISR );
  1295. if ( debug_level >= DEBUG_LEVEL_ISR )
  1296. printk("%s(%d):mgsl_isr_misc status=%04X\n",
  1297. __FILE__,__LINE__,status);
  1298. if ((status & MISCSTATUS_RCC_UNDERRUN) &&
  1299. (info->params.mode == MGSL_MODE_HDLC)) {
  1300. /* turn off receiver and rx DMA */
  1301. usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
  1302. usc_DmaCmd(info, DmaCmd_ResetRxChannel);
  1303. usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
  1304. usc_ClearIrqPendingBits(info, RECEIVE_DATA | RECEIVE_STATUS);
  1305. usc_DisableInterrupts(info, RECEIVE_DATA | RECEIVE_STATUS);
  1306. /* schedule BH handler to restart receiver */
  1307. info->pending_bh |= BH_RECEIVE;
  1308. info->rx_rcc_underrun = true;
  1309. }
  1310. usc_ClearIrqPendingBits( info, MISC );
  1311. usc_UnlatchMiscstatusBits( info, status );
  1312. } /* end of mgsl_isr_misc() */
  1313. /* mgsl_isr_null()
  1314. *
  1315. * Services undefined interrupt vectors from the
  1316. * USC. (hence this function SHOULD never be called)
  1317. *
  1318. * Arguments: info pointer to device extension (instance data)
  1319. * Return Value: None
  1320. */
  1321. static void mgsl_isr_null( struct mgsl_struct *info )
  1322. {
  1323. } /* end of mgsl_isr_null() */
  1324. /* mgsl_isr_receive_dma()
  1325. *
  1326. * Service a receive DMA channel interrupt.
  1327. * For this driver there are two sources of receive DMA interrupts
  1328. * as identified in the Receive DMA mode Register (RDMR):
  1329. *
  1330. * BIT3 EOA/EOL End of List, all receive buffers in receive
  1331. * buffer list have been filled (no more free buffers
  1332. * available). The DMA controller has shut down.
  1333. *
  1334. * BIT2 EOB End of Buffer. This interrupt occurs when a receive
  1335. * DMA buffer is terminated in response to completion
  1336. * of a good frame or a frame with errors. The status
  1337. * of the frame is stored in the buffer entry in the
  1338. * list of receive buffer entries.
  1339. *
  1340. * Arguments: info pointer to device instance data
  1341. * Return Value: None
  1342. */
  1343. static void mgsl_isr_receive_dma( struct mgsl_struct *info )
  1344. {
  1345. u16 status;
  1346. /* clear interrupt pending and IUS bit for Rx DMA IRQ */
  1347. usc_OutDmaReg( info, CDIR, BIT9 | BIT1 );
  1348. /* Read the receive DMA status to identify interrupt type. */
  1349. /* This also clears the status bits. */
  1350. status = usc_InDmaReg( info, RDMR );
  1351. if ( debug_level >= DEBUG_LEVEL_ISR )
  1352. printk("%s(%d):mgsl_isr_receive_dma(%s) status=%04X\n",
  1353. __FILE__,__LINE__,info->device_name,status);
  1354. info->pending_bh |= BH_RECEIVE;
  1355. if ( status & BIT3 ) {
  1356. info->rx_overflow = true;
  1357. info->icount.buf_overrun++;
  1358. }
  1359. } /* end of mgsl_isr_receive_dma() */
  1360. /* mgsl_isr_transmit_dma()
  1361. *
  1362. * This function services a transmit DMA channel interrupt.
  1363. *
  1364. * For this driver there is one source of transmit DMA interrupts
  1365. * as identified in the Transmit DMA Mode Register (TDMR):
  1366. *
  1367. * BIT2 EOB End of Buffer. This interrupt occurs when a
  1368. * transmit DMA buffer has been emptied.
  1369. *
  1370. * The driver maintains enough transmit DMA buffers to hold at least
  1371. * one max frame size transmit frame. When operating in a buffered
  1372. * transmit mode, there may be enough transmit DMA buffers to hold at
  1373. * least two or more max frame size frames. On an EOB condition,
  1374. * determine if there are any queued transmit buffers and copy into
  1375. * transmit DMA buffers if we have room.
  1376. *
  1377. * Arguments: info pointer to device instance data
  1378. * Return Value: None
  1379. */
  1380. static void mgsl_isr_transmit_dma( struct mgsl_struct *info )
  1381. {
  1382. u16 status;
  1383. /* clear interrupt pending and IUS bit for Tx DMA IRQ */
  1384. usc_OutDmaReg(info, CDIR, BIT8 | BIT0 );
  1385. /* Read the transmit DMA status to identify interrupt type. */
  1386. /* This also clears the status bits. */
  1387. status = usc_InDmaReg( info, TDMR );
  1388. if ( debug_level >= DEBUG_LEVEL_ISR )
  1389. printk("%s(%d):mgsl_isr_transmit_dma(%s) status=%04X\n",
  1390. __FILE__,__LINE__,info->device_name,status);
  1391. if ( status & BIT2 ) {
  1392. --info->tx_dma_buffers_used;
  1393. /* if there are transmit frames queued,
  1394. * try to load the next one
  1395. */
  1396. if ( load_next_tx_holding_buffer(info) ) {
  1397. /* if call returns non-zero value, we have
  1398. * at least one free tx holding buffer
  1399. */
  1400. info->pending_bh |= BH_TRANSMIT;
  1401. }
  1402. }
  1403. } /* end of mgsl_isr_transmit_dma() */
  1404. /* mgsl_interrupt()
  1405. *
  1406. * Interrupt service routine entry point.
  1407. *
  1408. * Arguments:
  1409. *
  1410. * irq interrupt number that caused interrupt
  1411. * dev_id device ID supplied during interrupt registration
  1412. *
  1413. * Return Value: None
  1414. */
  1415. static irqreturn_t mgsl_interrupt(int dummy, void *dev_id)
  1416. {
  1417. struct mgsl_struct *info = dev_id;
  1418. u16 UscVector;
  1419. u16 DmaVector;
  1420. if ( debug_level >= DEBUG_LEVEL_ISR )
  1421. printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)entry.\n",
  1422. __FILE__, __LINE__, info->irq_level);
  1423. spin_lock(&info->irq_spinlock);
  1424. for(;;) {
  1425. /* Read the interrupt vectors from hardware. */
  1426. UscVector = usc_InReg(info, IVR) >> 9;
  1427. DmaVector = usc_InDmaReg(info, DIVR);
  1428. if ( debug_level >= DEBUG_LEVEL_ISR )
  1429. printk("%s(%d):%s UscVector=%08X DmaVector=%08X\n",
  1430. __FILE__,__LINE__,info->device_name,UscVector,DmaVector);
  1431. if ( !UscVector && !DmaVector )
  1432. break;
  1433. /* Dispatch interrupt vector */
  1434. if ( UscVector )
  1435. (*UscIsrTable[UscVector])(info);
  1436. else if ( (DmaVector&(BIT10|BIT9)) == BIT10)
  1437. mgsl_isr_transmit_dma(info);
  1438. else
  1439. mgsl_isr_receive_dma(info);
  1440. if ( info->isr_overflow ) {
  1441. printk(KERN_ERR "%s(%d):%s isr overflow irq=%d\n",
  1442. __FILE__, __LINE__, info->device_name, info->irq_level);
  1443. usc_DisableMasterIrqBit(info);
  1444. usc_DisableDmaInterrupts(info,DICR_MASTER);
  1445. break;
  1446. }
  1447. }
  1448. /* Request bottom half processing if there's something
  1449. * for it to do and the bh is not already running
  1450. */
  1451. if ( info->pending_bh && !info->bh_running && !info->bh_requested ) {
  1452. if ( debug_level >= DEBUG_LEVEL_ISR )
  1453. printk("%s(%d):%s queueing bh task.\n",
  1454. __FILE__,__LINE__,info->device_name);
  1455. schedule_work(&info->task);
  1456. info->bh_requested = true;
  1457. }
  1458. spin_unlock(&info->irq_spinlock);
  1459. if ( debug_level >= DEBUG_LEVEL_ISR )
  1460. printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)exit.\n",
  1461. __FILE__, __LINE__, info->irq_level);
  1462. return IRQ_HANDLED;
  1463. } /* end of mgsl_interrupt() */
  1464. /* startup()
  1465. *
  1466. * Initialize and start device.
  1467. *
  1468. * Arguments: info pointer to device instance data
  1469. * Return Value: 0 if success, otherwise error code
  1470. */
  1471. static int startup(struct mgsl_struct * info)
  1472. {
  1473. int retval = 0;
  1474. if ( debug_level >= DEBUG_LEVEL_INFO )
  1475. printk("%s(%d):mgsl_startup(%s)\n",__FILE__,__LINE__,info->device_name);
  1476. if (tty_port_initialized(&info->port))
  1477. return 0;
  1478. if (!info->xmit_buf) {
  1479. /* allocate a page of memory for a transmit buffer */
  1480. info->xmit_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
  1481. if (!info->xmit_buf) {
  1482. printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
  1483. __FILE__,__LINE__,info->device_name);
  1484. return -ENOMEM;
  1485. }
  1486. }
  1487. info->pending_bh = 0;
  1488. memset(&info->icount, 0, sizeof(info->icount));
  1489. timer_setup(&info->tx_timer, mgsl_tx_timeout, 0);
  1490. /* Allocate and claim adapter resources */
  1491. retval = mgsl_claim_resources(info);
  1492. /* perform existence check and diagnostics */
  1493. if ( !retval )
  1494. retval = mgsl_adapter_test(info);
  1495. if ( retval ) {
  1496. if (capable(CAP_SYS_ADMIN) && info->port.tty)
  1497. set_bit(TTY_IO_ERROR, &info->port.tty->flags);
  1498. mgsl_release_resources(info);
  1499. return retval;
  1500. }
  1501. /* program hardware for current parameters */
  1502. mgsl_change_params(info);
  1503. if (info->port.tty)
  1504. clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
  1505. tty_port_set_initialized(&info->port, 1);
  1506. return 0;
  1507. } /* end of startup() */
  1508. /* shutdown()
  1509. *
  1510. * Called by mgsl_close() and mgsl_hangup() to shutdown hardware
  1511. *
  1512. * Arguments: info pointer to device instance data
  1513. * Return Value: None
  1514. */
  1515. static void shutdown(struct mgsl_struct * info)
  1516. {
  1517. unsigned long flags;
  1518. if (!tty_port_initialized(&info->port))
  1519. return;
  1520. if (debug_level >= DEBUG_LEVEL_INFO)
  1521. printk("%s(%d):mgsl_shutdown(%s)\n",
  1522. __FILE__,__LINE__, info->device_name );
  1523. /* clear status wait queue because status changes */
  1524. /* can't happen after shutting down the hardware */
  1525. wake_up_interruptible(&info->status_event_wait_q);
  1526. wake_up_interruptible(&info->event_wait_q);
  1527. del_timer_sync(&info->tx_timer);
  1528. if (info->xmit_buf) {
  1529. free_page((unsigned long) info->xmit_buf);
  1530. info->xmit_buf = NULL;
  1531. }
  1532. spin_lock_irqsave(&info->irq_spinlock,flags);
  1533. usc_DisableMasterIrqBit(info);
  1534. usc_stop_receiver(info);
  1535. usc_stop_transmitter(info);
  1536. usc_DisableInterrupts(info,RECEIVE_DATA | RECEIVE_STATUS |
  1537. TRANSMIT_DATA | TRANSMIT_STATUS | IO_PIN | MISC );
  1538. usc_DisableDmaInterrupts(info,DICR_MASTER + DICR_TRANSMIT + DICR_RECEIVE);
  1539. /* Disable DMAEN (Port 7, Bit 14) */
  1540. /* This disconnects the DMA request signal from the ISA bus */
  1541. /* on the ISA adapter. This has no effect for the PCI adapter */
  1542. usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) | BIT14));
  1543. /* Disable INTEN (Port 6, Bit12) */
  1544. /* This disconnects the IRQ request signal to the ISA bus */
  1545. /* on the ISA adapter. This has no effect for the PCI adapter */
  1546. usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) | BIT12));
  1547. if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
  1548. info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
  1549. usc_set_serial_signals(info);
  1550. }
  1551. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  1552. mgsl_release_resources(info);
  1553. if (info->port.tty)
  1554. set_bit(TTY_IO_ERROR, &info->port.tty->flags);
  1555. tty_port_set_initialized(&info->port, 0);
  1556. } /* end of shutdown() */
  1557. static void mgsl_program_hw(struct mgsl_struct *info)
  1558. {
  1559. unsigned long flags;
  1560. spin_lock_irqsave(&info->irq_spinlock,flags);
  1561. usc_stop_receiver(info);
  1562. usc_stop_transmitter(info);
  1563. info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
  1564. if (info->params.mode == MGSL_MODE_HDLC ||
  1565. info->params.mode == MGSL_MODE_RAW ||
  1566. info->netcount)
  1567. usc_set_sync_mode(info);
  1568. else
  1569. usc_set_async_mode(info);
  1570. usc_set_serial_signals(info);
  1571. info->dcd_chkcount = 0;
  1572. info->cts_chkcount = 0;
  1573. info->ri_chkcount = 0;
  1574. info->dsr_chkcount = 0;
  1575. usc_EnableStatusIrqs(info,SICR_CTS+SICR_DSR+SICR_DCD+SICR_RI);
  1576. usc_EnableInterrupts(info, IO_PIN);
  1577. usc_get_serial_signals(info);
  1578. if (info->netcount || info->port.tty->termios.c_cflag & CREAD)
  1579. usc_start_receiver(info);
  1580. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  1581. }
  1582. /* Reconfigure adapter based on new parameters
  1583. */
  1584. static void mgsl_change_params(struct mgsl_struct *info)
  1585. {
  1586. unsigned cflag;
  1587. int bits_per_char;
  1588. if (!info->port.tty)
  1589. return;
  1590. if (debug_level >= DEBUG_LEVEL_INFO)
  1591. printk("%s(%d):mgsl_change_params(%s)\n",
  1592. __FILE__,__LINE__, info->device_name );
  1593. cflag = info->port.tty->termios.c_cflag;
  1594. /* if B0 rate (hangup) specified then negate RTS and DTR */
  1595. /* otherwise assert RTS and DTR */
  1596. if (cflag & CBAUD)
  1597. info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
  1598. else
  1599. info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
  1600. /* byte size and parity */
  1601. switch (cflag & CSIZE) {
  1602. case CS5: info->params.data_bits = 5; break;
  1603. case CS6: info->params.data_bits = 6; break;
  1604. case CS7: info->params.data_bits = 7; break;
  1605. case CS8: info->params.data_bits = 8; break;
  1606. /* Never happens, but GCC is too dumb to figure it out */
  1607. default: info->params.data_bits = 7; break;
  1608. }
  1609. if (cflag & CSTOPB)
  1610. info->params.stop_bits = 2;
  1611. else
  1612. info->params.stop_bits = 1;
  1613. info->params.parity = ASYNC_PARITY_NONE;
  1614. if (cflag & PARENB) {
  1615. if (cflag & PARODD)
  1616. info->params.parity = ASYNC_PARITY_ODD;
  1617. else
  1618. info->params.parity = ASYNC_PARITY_EVEN;
  1619. #ifdef CMSPAR
  1620. if (cflag & CMSPAR)
  1621. info->params.parity = ASYNC_PARITY_SPACE;
  1622. #endif
  1623. }
  1624. /* calculate number of jiffies to transmit a full
  1625. * FIFO (32 bytes) at specified data rate
  1626. */
  1627. bits_per_char = info->params.data_bits +
  1628. info->params.stop_bits + 1;
  1629. /* if port data rate is set to 460800 or less then
  1630. * allow tty settings to override, otherwise keep the
  1631. * current data rate.
  1632. */
  1633. if (info->params.data_rate <= 460800)
  1634. info->params.data_rate = tty_get_baud_rate(info->port.tty);
  1635. if ( info->params.data_rate ) {
  1636. info->timeout = (32*HZ*bits_per_char) /
  1637. info->params.data_rate;
  1638. }
  1639. info->timeout += HZ/50; /* Add .02 seconds of slop */
  1640. tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
  1641. tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
  1642. /* process tty input control flags */
  1643. info->read_status_mask = RXSTATUS_OVERRUN;
  1644. if (I_INPCK(info->port.tty))
  1645. info->read_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
  1646. if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
  1647. info->read_status_mask |= RXSTATUS_BREAK_RECEIVED;
  1648. if (I_IGNPAR(info->port.tty))
  1649. info->ignore_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
  1650. if (I_IGNBRK(info->port.tty)) {
  1651. info->ignore_status_mask |= RXSTATUS_BREAK_RECEIVED;
  1652. /* If ignoring parity and break indicators, ignore
  1653. * overruns too. (For real raw support).
  1654. */
  1655. if (I_IGNPAR(info->port.tty))
  1656. info->ignore_status_mask |= RXSTATUS_OVERRUN;
  1657. }
  1658. mgsl_program_hw(info);
  1659. } /* end of mgsl_change_params() */
  1660. /* mgsl_put_char()
  1661. *
  1662. * Add a character to the transmit buffer.
  1663. *
  1664. * Arguments: tty pointer to tty information structure
  1665. * ch character to add to transmit buffer
  1666. *
  1667. * Return Value: None
  1668. */
  1669. static int mgsl_put_char(struct tty_struct *tty, unsigned char ch)
  1670. {
  1671. struct mgsl_struct *info = tty->driver_data;
  1672. unsigned long flags;
  1673. int ret = 0;
  1674. if (debug_level >= DEBUG_LEVEL_INFO) {
  1675. printk(KERN_DEBUG "%s(%d):mgsl_put_char(%d) on %s\n",
  1676. __FILE__, __LINE__, ch, info->device_name);
  1677. }
  1678. if (mgsl_paranoia_check(info, tty->name, "mgsl_put_char"))
  1679. return 0;
  1680. if (!info->xmit_buf)
  1681. return 0;
  1682. spin_lock_irqsave(&info->irq_spinlock, flags);
  1683. if ((info->params.mode == MGSL_MODE_ASYNC ) || !info->tx_active) {
  1684. if (info->xmit_cnt < SERIAL_XMIT_SIZE - 1) {
  1685. info->xmit_buf[info->xmit_head++] = ch;
  1686. info->xmit_head &= SERIAL_XMIT_SIZE-1;
  1687. info->xmit_cnt++;
  1688. ret = 1;
  1689. }
  1690. }
  1691. spin_unlock_irqrestore(&info->irq_spinlock, flags);
  1692. return ret;
  1693. } /* end of mgsl_put_char() */
  1694. /* mgsl_flush_chars()
  1695. *
  1696. * Enable transmitter so remaining characters in the
  1697. * transmit buffer are sent.
  1698. *
  1699. * Arguments: tty pointer to tty information structure
  1700. * Return Value: None
  1701. */
  1702. static void mgsl_flush_chars(struct tty_struct *tty)
  1703. {
  1704. struct mgsl_struct *info = tty->driver_data;
  1705. unsigned long flags;
  1706. if ( debug_level >= DEBUG_LEVEL_INFO )
  1707. printk( "%s(%d):mgsl_flush_chars() entry on %s xmit_cnt=%d\n",
  1708. __FILE__,__LINE__,info->device_name,info->xmit_cnt);
  1709. if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_chars"))
  1710. return;
  1711. if (info->xmit_cnt <= 0 || tty->stopped || tty->hw_stopped ||
  1712. !info->xmit_buf)
  1713. return;
  1714. if ( debug_level >= DEBUG_LEVEL_INFO )
  1715. printk( "%s(%d):mgsl_flush_chars() entry on %s starting transmitter\n",
  1716. __FILE__,__LINE__,info->device_name );
  1717. spin_lock_irqsave(&info->irq_spinlock,flags);
  1718. if (!info->tx_active) {
  1719. if ( (info->params.mode == MGSL_MODE_HDLC ||
  1720. info->params.mode == MGSL_MODE_RAW) && info->xmit_cnt ) {
  1721. /* operating in synchronous (frame oriented) mode */
  1722. /* copy data from circular xmit_buf to */
  1723. /* transmit DMA buffer. */
  1724. mgsl_load_tx_dma_buffer(info,
  1725. info->xmit_buf,info->xmit_cnt);
  1726. }
  1727. usc_start_transmitter(info);
  1728. }
  1729. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  1730. } /* end of mgsl_flush_chars() */
  1731. /* mgsl_write()
  1732. *
  1733. * Send a block of data
  1734. *
  1735. * Arguments:
  1736. *
  1737. * tty pointer to tty information structure
  1738. * buf pointer to buffer containing send data
  1739. * count size of send data in bytes
  1740. *
  1741. * Return Value: number of characters written
  1742. */
  1743. static int mgsl_write(struct tty_struct * tty,
  1744. const unsigned char *buf, int count)
  1745. {
  1746. int c, ret = 0;
  1747. struct mgsl_struct *info = tty->driver_data;
  1748. unsigned long flags;
  1749. if ( debug_level >= DEBUG_LEVEL_INFO )
  1750. printk( "%s(%d):mgsl_write(%s) count=%d\n",
  1751. __FILE__,__LINE__,info->device_name,count);
  1752. if (mgsl_paranoia_check(info, tty->name, "mgsl_write"))
  1753. goto cleanup;
  1754. if (!info->xmit_buf)
  1755. goto cleanup;
  1756. if ( info->params.mode == MGSL_MODE_HDLC ||
  1757. info->params.mode == MGSL_MODE_RAW ) {
  1758. /* operating in synchronous (frame oriented) mode */
  1759. if (info->tx_active) {
  1760. if ( info->params.mode == MGSL_MODE_HDLC ) {
  1761. ret = 0;
  1762. goto cleanup;
  1763. }
  1764. /* transmitter is actively sending data -
  1765. * if we have multiple transmit dma and
  1766. * holding buffers, attempt to queue this
  1767. * frame for transmission at a later time.
  1768. */
  1769. if (info->tx_holding_count >= info->num_tx_holding_buffers ) {
  1770. /* no tx holding buffers available */
  1771. ret = 0;
  1772. goto cleanup;
  1773. }
  1774. /* queue transmit frame request */
  1775. ret = count;
  1776. save_tx_buffer_request(info,buf,count);
  1777. /* if we have sufficient tx dma buffers,
  1778. * load the next buffered tx request
  1779. */
  1780. spin_lock_irqsave(&info->irq_spinlock,flags);
  1781. load_next_tx_holding_buffer(info);
  1782. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  1783. goto cleanup;
  1784. }
  1785. /* if operating in HDLC LoopMode and the adapter */
  1786. /* has yet to be inserted into the loop, we can't */
  1787. /* transmit */
  1788. if ( (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) &&
  1789. !usc_loopmode_active(info) )
  1790. {
  1791. ret = 0;
  1792. goto cleanup;
  1793. }
  1794. if ( info->xmit_cnt ) {
  1795. /* Send accumulated from send_char() calls */
  1796. /* as frame and wait before accepting more data. */
  1797. ret = 0;
  1798. /* copy data from circular xmit_buf to */
  1799. /* transmit DMA buffer. */
  1800. mgsl_load_tx_dma_buffer(info,
  1801. info->xmit_buf,info->xmit_cnt);
  1802. if ( debug_level >= DEBUG_LEVEL_INFO )
  1803. printk( "%s(%d):mgsl_write(%s) sync xmit_cnt flushing\n",
  1804. __FILE__,__LINE__,info->device_name);
  1805. } else {
  1806. if ( debug_level >= DEBUG_LEVEL_INFO )
  1807. printk( "%s(%d):mgsl_write(%s) sync transmit accepted\n",
  1808. __FILE__,__LINE__,info->device_name);
  1809. ret = count;
  1810. info->xmit_cnt = count;
  1811. mgsl_load_tx_dma_buffer(info,buf,count);
  1812. }
  1813. } else {
  1814. while (1) {
  1815. spin_lock_irqsave(&info->irq_spinlock,flags);
  1816. c = min_t(int, count,
  1817. min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
  1818. SERIAL_XMIT_SIZE - info->xmit_head));
  1819. if (c <= 0) {
  1820. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  1821. break;
  1822. }
  1823. memcpy(info->xmit_buf + info->xmit_head, buf, c);
  1824. info->xmit_head = ((info->xmit_head + c) &
  1825. (SERIAL_XMIT_SIZE-1));
  1826. info->xmit_cnt += c;
  1827. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  1828. buf += c;
  1829. count -= c;
  1830. ret += c;
  1831. }
  1832. }
  1833. if (info->xmit_cnt && !tty->stopped && !tty->hw_stopped) {
  1834. spin_lock_irqsave(&info->irq_spinlock,flags);
  1835. if (!info->tx_active)
  1836. usc_start_transmitter(info);
  1837. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  1838. }
  1839. cleanup:
  1840. if ( debug_level >= DEBUG_LEVEL_INFO )
  1841. printk( "%s(%d):mgsl_write(%s) returning=%d\n",
  1842. __FILE__,__LINE__,info->device_name,ret);
  1843. return ret;
  1844. } /* end of mgsl_write() */
  1845. /* mgsl_write_room()
  1846. *
  1847. * Return the count of free bytes in transmit buffer
  1848. *
  1849. * Arguments: tty pointer to tty info structure
  1850. * Return Value: None
  1851. */
  1852. static int mgsl_write_room(struct tty_struct *tty)
  1853. {
  1854. struct mgsl_struct *info = tty->driver_data;
  1855. int ret;
  1856. if (mgsl_paranoia_check(info, tty->name, "mgsl_write_room"))
  1857. return 0;
  1858. ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
  1859. if (ret < 0)
  1860. ret = 0;
  1861. if (debug_level >= DEBUG_LEVEL_INFO)
  1862. printk("%s(%d):mgsl_write_room(%s)=%d\n",
  1863. __FILE__,__LINE__, info->device_name,ret );
  1864. if ( info->params.mode == MGSL_MODE_HDLC ||
  1865. info->params.mode == MGSL_MODE_RAW ) {
  1866. /* operating in synchronous (frame oriented) mode */
  1867. if ( info->tx_active )
  1868. return 0;
  1869. else
  1870. return HDLC_MAX_FRAME_SIZE;
  1871. }
  1872. return ret;
  1873. } /* end of mgsl_write_room() */
  1874. /* mgsl_chars_in_buffer()
  1875. *
  1876. * Return the count of bytes in transmit buffer
  1877. *
  1878. * Arguments: tty pointer to tty info structure
  1879. * Return Value: None
  1880. */
  1881. static int mgsl_chars_in_buffer(struct tty_struct *tty)
  1882. {
  1883. struct mgsl_struct *info = tty->driver_data;
  1884. if (debug_level >= DEBUG_LEVEL_INFO)
  1885. printk("%s(%d):mgsl_chars_in_buffer(%s)\n",
  1886. __FILE__,__LINE__, info->device_name );
  1887. if (mgsl_paranoia_check(info, tty->name, "mgsl_chars_in_buffer"))
  1888. return 0;
  1889. if (debug_level >= DEBUG_LEVEL_INFO)
  1890. printk("%s(%d):mgsl_chars_in_buffer(%s)=%d\n",
  1891. __FILE__,__LINE__, info->device_name,info->xmit_cnt );
  1892. if ( info->params.mode == MGSL_MODE_HDLC ||
  1893. info->params.mode == MGSL_MODE_RAW ) {
  1894. /* operating in synchronous (frame oriented) mode */
  1895. if ( info->tx_active )
  1896. return info->max_frame_size;
  1897. else
  1898. return 0;
  1899. }
  1900. return info->xmit_cnt;
  1901. } /* end of mgsl_chars_in_buffer() */
  1902. /* mgsl_flush_buffer()
  1903. *
  1904. * Discard all data in the send buffer
  1905. *
  1906. * Arguments: tty pointer to tty info structure
  1907. * Return Value: None
  1908. */
  1909. static void mgsl_flush_buffer(struct tty_struct *tty)
  1910. {
  1911. struct mgsl_struct *info = tty->driver_data;
  1912. unsigned long flags;
  1913. if (debug_level >= DEBUG_LEVEL_INFO)
  1914. printk("%s(%d):mgsl_flush_buffer(%s) entry\n",
  1915. __FILE__,__LINE__, info->device_name );
  1916. if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_buffer"))
  1917. return;
  1918. spin_lock_irqsave(&info->irq_spinlock,flags);
  1919. info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
  1920. del_timer(&info->tx_timer);
  1921. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  1922. tty_wakeup(tty);
  1923. }
  1924. /* mgsl_send_xchar()
  1925. *
  1926. * Send a high-priority XON/XOFF character
  1927. *
  1928. * Arguments: tty pointer to tty info structure
  1929. * ch character to send
  1930. * Return Value: None
  1931. */
  1932. static void mgsl_send_xchar(struct tty_struct *tty, char ch)
  1933. {
  1934. struct mgsl_struct *info = tty->driver_data;
  1935. unsigned long flags;
  1936. if (debug_level >= DEBUG_LEVEL_INFO)
  1937. printk("%s(%d):mgsl_send_xchar(%s,%d)\n",
  1938. __FILE__,__LINE__, info->device_name, ch );
  1939. if (mgsl_paranoia_check(info, tty->name, "mgsl_send_xchar"))
  1940. return;
  1941. info->x_char = ch;
  1942. if (ch) {
  1943. /* Make sure transmit interrupts are on */
  1944. spin_lock_irqsave(&info->irq_spinlock,flags);
  1945. if (!info->tx_enabled)
  1946. usc_start_transmitter(info);
  1947. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  1948. }
  1949. } /* end of mgsl_send_xchar() */
  1950. /* mgsl_throttle()
  1951. *
  1952. * Signal remote device to throttle send data (our receive data)
  1953. *
  1954. * Arguments: tty pointer to tty info structure
  1955. * Return Value: None
  1956. */
  1957. static void mgsl_throttle(struct tty_struct * tty)
  1958. {
  1959. struct mgsl_struct *info = tty->driver_data;
  1960. unsigned long flags;
  1961. if (debug_level >= DEBUG_LEVEL_INFO)
  1962. printk("%s(%d):mgsl_throttle(%s) entry\n",
  1963. __FILE__,__LINE__, info->device_name );
  1964. if (mgsl_paranoia_check(info, tty->name, "mgsl_throttle"))
  1965. return;
  1966. if (I_IXOFF(tty))
  1967. mgsl_send_xchar(tty, STOP_CHAR(tty));
  1968. if (C_CRTSCTS(tty)) {
  1969. spin_lock_irqsave(&info->irq_spinlock,flags);
  1970. info->serial_signals &= ~SerialSignal_RTS;
  1971. usc_set_serial_signals(info);
  1972. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  1973. }
  1974. } /* end of mgsl_throttle() */
  1975. /* mgsl_unthrottle()
  1976. *
  1977. * Signal remote device to stop throttling send data (our receive data)
  1978. *
  1979. * Arguments: tty pointer to tty info structure
  1980. * Return Value: None
  1981. */
  1982. static void mgsl_unthrottle(struct tty_struct * tty)
  1983. {
  1984. struct mgsl_struct *info = tty->driver_data;
  1985. unsigned long flags;
  1986. if (debug_level >= DEBUG_LEVEL_INFO)
  1987. printk("%s(%d):mgsl_unthrottle(%s) entry\n",
  1988. __FILE__,__LINE__, info->device_name );
  1989. if (mgsl_paranoia_check(info, tty->name, "mgsl_unthrottle"))
  1990. return;
  1991. if (I_IXOFF(tty)) {
  1992. if (info->x_char)
  1993. info->x_char = 0;
  1994. else
  1995. mgsl_send_xchar(tty, START_CHAR(tty));
  1996. }
  1997. if (C_CRTSCTS(tty)) {
  1998. spin_lock_irqsave(&info->irq_spinlock,flags);
  1999. info->serial_signals |= SerialSignal_RTS;
  2000. usc_set_serial_signals(info);
  2001. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  2002. }
  2003. } /* end of mgsl_unthrottle() */
  2004. /* mgsl_get_stats()
  2005. *
  2006. * get the current serial parameters information
  2007. *
  2008. * Arguments: info pointer to device instance data
  2009. * user_icount pointer to buffer to hold returned stats
  2010. *
  2011. * Return Value: 0 if success, otherwise error code
  2012. */
  2013. static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount __user *user_icount)
  2014. {
  2015. int err;
  2016. if (debug_level >= DEBUG_LEVEL_INFO)
  2017. printk("%s(%d):mgsl_get_params(%s)\n",
  2018. __FILE__,__LINE__, info->device_name);
  2019. if (!user_icount) {
  2020. memset(&info->icount, 0, sizeof(info->icount));
  2021. } else {
  2022. mutex_lock(&info->port.mutex);
  2023. COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
  2024. mutex_unlock(&info->port.mutex);
  2025. if (err)
  2026. return -EFAULT;
  2027. }
  2028. return 0;
  2029. } /* end of mgsl_get_stats() */
  2030. /* mgsl_get_params()
  2031. *
  2032. * get the current serial parameters information
  2033. *
  2034. * Arguments: info pointer to device instance data
  2035. * user_params pointer to buffer to hold returned params
  2036. *
  2037. * Return Value: 0 if success, otherwise error code
  2038. */
  2039. static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params)
  2040. {
  2041. int err;
  2042. if (debug_level >= DEBUG_LEVEL_INFO)
  2043. printk("%s(%d):mgsl_get_params(%s)\n",
  2044. __FILE__,__LINE__, info->device_name);
  2045. mutex_lock(&info->port.mutex);
  2046. COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
  2047. mutex_unlock(&info->port.mutex);
  2048. if (err) {
  2049. if ( debug_level >= DEBUG_LEVEL_INFO )
  2050. printk( "%s(%d):mgsl_get_params(%s) user buffer copy failed\n",
  2051. __FILE__,__LINE__,info->device_name);
  2052. return -EFAULT;
  2053. }
  2054. return 0;
  2055. } /* end of mgsl_get_params() */
  2056. /* mgsl_set_params()
  2057. *
  2058. * set the serial parameters
  2059. *
  2060. * Arguments:
  2061. *
  2062. * info pointer to device instance data
  2063. * new_params user buffer containing new serial params
  2064. *
  2065. * Return Value: 0 if success, otherwise error code
  2066. */
  2067. static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params)
  2068. {
  2069. unsigned long flags;
  2070. MGSL_PARAMS tmp_params;
  2071. int err;
  2072. if (debug_level >= DEBUG_LEVEL_INFO)
  2073. printk("%s(%d):mgsl_set_params %s\n", __FILE__,__LINE__,
  2074. info->device_name );
  2075. COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
  2076. if (err) {
  2077. if ( debug_level >= DEBUG_LEVEL_INFO )
  2078. printk( "%s(%d):mgsl_set_params(%s) user buffer copy failed\n",
  2079. __FILE__,__LINE__,info->device_name);
  2080. return -EFAULT;
  2081. }
  2082. mutex_lock(&info->port.mutex);
  2083. spin_lock_irqsave(&info->irq_spinlock,flags);
  2084. memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
  2085. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  2086. mgsl_change_params(info);
  2087. mutex_unlock(&info->port.mutex);
  2088. return 0;
  2089. } /* end of mgsl_set_params() */
  2090. /* mgsl_get_txidle()
  2091. *
  2092. * get the current transmit idle mode
  2093. *
  2094. * Arguments: info pointer to device instance data
  2095. * idle_mode pointer to buffer to hold returned idle mode
  2096. *
  2097. * Return Value: 0 if success, otherwise error code
  2098. */
  2099. static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode)
  2100. {
  2101. int err;
  2102. if (debug_level >= DEBUG_LEVEL_INFO)
  2103. printk("%s(%d):mgsl_get_txidle(%s)=%d\n",
  2104. __FILE__,__LINE__, info->device_name, info->idle_mode);
  2105. COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
  2106. if (err) {
  2107. if ( debug_level >= DEBUG_LEVEL_INFO )
  2108. printk( "%s(%d):mgsl_get_txidle(%s) user buffer copy failed\n",
  2109. __FILE__,__LINE__,info->device_name);
  2110. return -EFAULT;
  2111. }
  2112. return 0;
  2113. } /* end of mgsl_get_txidle() */
  2114. /* mgsl_set_txidle() service ioctl to set transmit idle mode
  2115. *
  2116. * Arguments: info pointer to device instance data
  2117. * idle_mode new idle mode
  2118. *
  2119. * Return Value: 0 if success, otherwise error code
  2120. */
  2121. static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode)
  2122. {
  2123. unsigned long flags;
  2124. if (debug_level >= DEBUG_LEVEL_INFO)
  2125. printk("%s(%d):mgsl_set_txidle(%s,%d)\n", __FILE__,__LINE__,
  2126. info->device_name, idle_mode );
  2127. spin_lock_irqsave(&info->irq_spinlock,flags);
  2128. info->idle_mode = idle_mode;
  2129. usc_set_txidle( info );
  2130. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  2131. return 0;
  2132. } /* end of mgsl_set_txidle() */
  2133. /* mgsl_txenable()
  2134. *
  2135. * enable or disable the transmitter
  2136. *
  2137. * Arguments:
  2138. *
  2139. * info pointer to device instance data
  2140. * enable 1 = enable, 0 = disable
  2141. *
  2142. * Return Value: 0 if success, otherwise error code
  2143. */
  2144. static int mgsl_txenable(struct mgsl_struct * info, int enable)
  2145. {
  2146. unsigned long flags;
  2147. if (debug_level >= DEBUG_LEVEL_INFO)
  2148. printk("%s(%d):mgsl_txenable(%s,%d)\n", __FILE__,__LINE__,
  2149. info->device_name, enable);
  2150. spin_lock_irqsave(&info->irq_spinlock,flags);
  2151. if ( enable ) {
  2152. if ( !info->tx_enabled ) {
  2153. usc_start_transmitter(info);
  2154. /*--------------------------------------------------
  2155. * if HDLC/SDLC Loop mode, attempt to insert the
  2156. * station in the 'loop' by setting CMR:13. Upon
  2157. * receipt of the next GoAhead (RxAbort) sequence,
  2158. * the OnLoop indicator (CCSR:7) should go active
  2159. * to indicate that we are on the loop
  2160. *--------------------------------------------------*/
  2161. if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
  2162. usc_loopmode_insert_request( info );
  2163. }
  2164. } else {
  2165. if ( info->tx_enabled )
  2166. usc_stop_transmitter(info);
  2167. }
  2168. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  2169. return 0;
  2170. } /* end of mgsl_txenable() */
  2171. /* mgsl_txabort() abort send HDLC frame
  2172. *
  2173. * Arguments: info pointer to device instance data
  2174. * Return Value: 0 if success, otherwise error code
  2175. */
  2176. static int mgsl_txabort(struct mgsl_struct * info)
  2177. {
  2178. unsigned long flags;
  2179. if (debug_level >= DEBUG_LEVEL_INFO)
  2180. printk("%s(%d):mgsl_txabort(%s)\n", __FILE__,__LINE__,
  2181. info->device_name);
  2182. spin_lock_irqsave(&info->irq_spinlock,flags);
  2183. if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC )
  2184. {
  2185. if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
  2186. usc_loopmode_cancel_transmit( info );
  2187. else
  2188. usc_TCmd(info,TCmd_SendAbort);
  2189. }
  2190. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  2191. return 0;
  2192. } /* end of mgsl_txabort() */
  2193. /* mgsl_rxenable() enable or disable the receiver
  2194. *
  2195. * Arguments: info pointer to device instance data
  2196. * enable 1 = enable, 0 = disable
  2197. * Return Value: 0 if success, otherwise error code
  2198. */
  2199. static int mgsl_rxenable(struct mgsl_struct * info, int enable)
  2200. {
  2201. unsigned long flags;
  2202. if (debug_level >= DEBUG_LEVEL_INFO)
  2203. printk("%s(%d):mgsl_rxenable(%s,%d)\n", __FILE__,__LINE__,
  2204. info->device_name, enable);
  2205. spin_lock_irqsave(&info->irq_spinlock,flags);
  2206. if ( enable ) {
  2207. if ( !info->rx_enabled )
  2208. usc_start_receiver(info);
  2209. } else {
  2210. if ( info->rx_enabled )
  2211. usc_stop_receiver(info);
  2212. }
  2213. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  2214. return 0;
  2215. } /* end of mgsl_rxenable() */
  2216. /* mgsl_wait_event() wait for specified event to occur
  2217. *
  2218. * Arguments: info pointer to device instance data
  2219. * mask pointer to bitmask of events to wait for
  2220. * Return Value: 0 if successful and bit mask updated with
  2221. * of events triggerred,
  2222. * otherwise error code
  2223. */
  2224. static int mgsl_wait_event(struct mgsl_struct * info, int __user * mask_ptr)
  2225. {
  2226. unsigned long flags;
  2227. int s;
  2228. int rc=0;
  2229. struct mgsl_icount cprev, cnow;
  2230. int events;
  2231. int mask;
  2232. struct _input_signal_events oldsigs, newsigs;
  2233. DECLARE_WAITQUEUE(wait, current);
  2234. COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
  2235. if (rc) {
  2236. return -EFAULT;
  2237. }
  2238. if (debug_level >= DEBUG_LEVEL_INFO)
  2239. printk("%s(%d):mgsl_wait_event(%s,%d)\n", __FILE__,__LINE__,
  2240. info->device_name, mask);
  2241. spin_lock_irqsave(&info->irq_spinlock,flags);
  2242. /* return immediately if state matches requested events */
  2243. usc_get_serial_signals(info);
  2244. s = info->serial_signals;
  2245. events = mask &
  2246. ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
  2247. ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
  2248. ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
  2249. ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
  2250. if (events) {
  2251. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  2252. goto exit;
  2253. }
  2254. /* save current irq counts */
  2255. cprev = info->icount;
  2256. oldsigs = info->input_signal_events;
  2257. /* enable hunt and idle irqs if needed */
  2258. if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
  2259. u16 oldreg = usc_InReg(info,RICR);
  2260. u16 newreg = oldreg +
  2261. (mask & MgslEvent_ExitHuntMode ? RXSTATUS_EXITED_HUNT:0) +
  2262. (mask & MgslEvent_IdleReceived ? RXSTATUS_IDLE_RECEIVED:0);
  2263. if (oldreg != newreg)
  2264. usc_OutReg(info, RICR, newreg);
  2265. }
  2266. set_current_state(TASK_INTERRUPTIBLE);
  2267. add_wait_queue(&info->event_wait_q, &wait);
  2268. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  2269. for(;;) {
  2270. schedule();
  2271. if (signal_pending(current)) {
  2272. rc = -ERESTARTSYS;
  2273. break;
  2274. }
  2275. /* get current irq counts */
  2276. spin_lock_irqsave(&info->irq_spinlock,flags);
  2277. cnow = info->icount;
  2278. newsigs = info->input_signal_events;
  2279. set_current_state(TASK_INTERRUPTIBLE);
  2280. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  2281. /* if no change, wait aborted for some reason */
  2282. if (newsigs.dsr_up == oldsigs.dsr_up &&
  2283. newsigs.dsr_down == oldsigs.dsr_down &&
  2284. newsigs.dcd_up == oldsigs.dcd_up &&
  2285. newsigs.dcd_down == oldsigs.dcd_down &&
  2286. newsigs.cts_up == oldsigs.cts_up &&
  2287. newsigs.cts_down == oldsigs.cts_down &&
  2288. newsigs.ri_up == oldsigs.ri_up &&
  2289. newsigs.ri_down == oldsigs.ri_down &&
  2290. cnow.exithunt == cprev.exithunt &&
  2291. cnow.rxidle == cprev.rxidle) {
  2292. rc = -EIO;
  2293. break;
  2294. }
  2295. events = mask &
  2296. ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
  2297. (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
  2298. (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
  2299. (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
  2300. (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
  2301. (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
  2302. (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
  2303. (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
  2304. (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
  2305. (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
  2306. if (events)
  2307. break;
  2308. cprev = cnow;
  2309. oldsigs = newsigs;
  2310. }
  2311. remove_wait_queue(&info->event_wait_q, &wait);
  2312. set_current_state(TASK_RUNNING);
  2313. if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
  2314. spin_lock_irqsave(&info->irq_spinlock,flags);
  2315. if (!waitqueue_active(&info->event_wait_q)) {
  2316. /* disable enable exit hunt mode/idle rcvd IRQs */
  2317. usc_OutReg(info, RICR, usc_InReg(info,RICR) &
  2318. ~(RXSTATUS_EXITED_HUNT | RXSTATUS_IDLE_RECEIVED));
  2319. }
  2320. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  2321. }
  2322. exit:
  2323. if ( rc == 0 )
  2324. PUT_USER(rc, events, mask_ptr);
  2325. return rc;
  2326. } /* end of mgsl_wait_event() */
  2327. static int modem_input_wait(struct mgsl_struct *info,int arg)
  2328. {
  2329. unsigned long flags;
  2330. int rc;
  2331. struct mgsl_icount cprev, cnow;
  2332. DECLARE_WAITQUEUE(wait, current);
  2333. /* save current irq counts */
  2334. spin_lock_irqsave(&info->irq_spinlock,flags);
  2335. cprev = info->icount;
  2336. add_wait_queue(&info->status_event_wait_q, &wait);
  2337. set_current_state(TASK_INTERRUPTIBLE);
  2338. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  2339. for(;;) {
  2340. schedule();
  2341. if (signal_pending(current)) {
  2342. rc = -ERESTARTSYS;
  2343. break;
  2344. }
  2345. /* get new irq counts */
  2346. spin_lock_irqsave(&info->irq_spinlock,flags);
  2347. cnow = info->icount;
  2348. set_current_state(TASK_INTERRUPTIBLE);
  2349. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  2350. /* if no change, wait aborted for some reason */
  2351. if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
  2352. cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
  2353. rc = -EIO;
  2354. break;
  2355. }
  2356. /* check for change in caller specified modem input */
  2357. if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
  2358. (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
  2359. (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
  2360. (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
  2361. rc = 0;
  2362. break;
  2363. }
  2364. cprev = cnow;
  2365. }
  2366. remove_wait_queue(&info->status_event_wait_q, &wait);
  2367. set_current_state(TASK_RUNNING);
  2368. return rc;
  2369. }
  2370. /* return the state of the serial control and status signals
  2371. */
  2372. static int tiocmget(struct tty_struct *tty)
  2373. {
  2374. struct mgsl_struct *info = tty->driver_data;
  2375. unsigned int result;
  2376. unsigned long flags;
  2377. spin_lock_irqsave(&info->irq_spinlock,flags);
  2378. usc_get_serial_signals(info);
  2379. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  2380. result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
  2381. ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
  2382. ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
  2383. ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
  2384. ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
  2385. ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
  2386. if (debug_level >= DEBUG_LEVEL_INFO)
  2387. printk("%s(%d):%s tiocmget() value=%08X\n",
  2388. __FILE__,__LINE__, info->device_name, result );
  2389. return result;
  2390. }
  2391. /* set modem control signals (DTR/RTS)
  2392. */
  2393. static int tiocmset(struct tty_struct *tty,
  2394. unsigned int set, unsigned int clear)
  2395. {
  2396. struct mgsl_struct *info = tty->driver_data;
  2397. unsigned long flags;
  2398. if (debug_level >= DEBUG_LEVEL_INFO)
  2399. printk("%s(%d):%s tiocmset(%x,%x)\n",
  2400. __FILE__,__LINE__,info->device_name, set, clear);
  2401. if (set & TIOCM_RTS)
  2402. info->serial_signals |= SerialSignal_RTS;
  2403. if (set & TIOCM_DTR)
  2404. info->serial_signals |= SerialSignal_DTR;
  2405. if (clear & TIOCM_RTS)
  2406. info->serial_signals &= ~SerialSignal_RTS;
  2407. if (clear & TIOCM_DTR)
  2408. info->serial_signals &= ~SerialSignal_DTR;
  2409. spin_lock_irqsave(&info->irq_spinlock,flags);
  2410. usc_set_serial_signals(info);
  2411. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  2412. return 0;
  2413. }
  2414. /* mgsl_break() Set or clear transmit break condition
  2415. *
  2416. * Arguments: tty pointer to tty instance data
  2417. * break_state -1=set break condition, 0=clear
  2418. * Return Value: error code
  2419. */
  2420. static int mgsl_break(struct tty_struct *tty, int break_state)
  2421. {
  2422. struct mgsl_struct * info = tty->driver_data;
  2423. unsigned long flags;
  2424. if (debug_level >= DEBUG_LEVEL_INFO)
  2425. printk("%s(%d):mgsl_break(%s,%d)\n",
  2426. __FILE__,__LINE__, info->device_name, break_state);
  2427. if (mgsl_paranoia_check(info, tty->name, "mgsl_break"))
  2428. return -EINVAL;
  2429. spin_lock_irqsave(&info->irq_spinlock,flags);
  2430. if (break_state == -1)
  2431. usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) | BIT7));
  2432. else
  2433. usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) & ~BIT7));
  2434. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  2435. return 0;
  2436. } /* end of mgsl_break() */
  2437. /*
  2438. * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
  2439. * Return: write counters to the user passed counter struct
  2440. * NB: both 1->0 and 0->1 transitions are counted except for
  2441. * RI where only 0->1 is counted.
  2442. */
  2443. static int msgl_get_icount(struct tty_struct *tty,
  2444. struct serial_icounter_struct *icount)
  2445. {
  2446. struct mgsl_struct * info = tty->driver_data;
  2447. struct mgsl_icount cnow; /* kernel counter temps */
  2448. unsigned long flags;
  2449. spin_lock_irqsave(&info->irq_spinlock,flags);
  2450. cnow = info->icount;
  2451. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  2452. icount->cts = cnow.cts;
  2453. icount->dsr = cnow.dsr;
  2454. icount->rng = cnow.rng;
  2455. icount->dcd = cnow.dcd;
  2456. icount->rx = cnow.rx;
  2457. icount->tx = cnow.tx;
  2458. icount->frame = cnow.frame;
  2459. icount->overrun = cnow.overrun;
  2460. icount->parity = cnow.parity;
  2461. icount->brk = cnow.brk;
  2462. icount->buf_overrun = cnow.buf_overrun;
  2463. return 0;
  2464. }
  2465. /* mgsl_ioctl() Service an IOCTL request
  2466. *
  2467. * Arguments:
  2468. *
  2469. * tty pointer to tty instance data
  2470. * cmd IOCTL command code
  2471. * arg command argument/context
  2472. *
  2473. * Return Value: 0 if success, otherwise error code
  2474. */
  2475. static int mgsl_ioctl(struct tty_struct *tty,
  2476. unsigned int cmd, unsigned long arg)
  2477. {
  2478. struct mgsl_struct * info = tty->driver_data;
  2479. if (debug_level >= DEBUG_LEVEL_INFO)
  2480. printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
  2481. info->device_name, cmd );
  2482. if (mgsl_paranoia_check(info, tty->name, "mgsl_ioctl"))
  2483. return -ENODEV;
  2484. if (cmd != TIOCMIWAIT) {
  2485. if (tty_io_error(tty))
  2486. return -EIO;
  2487. }
  2488. return mgsl_ioctl_common(info, cmd, arg);
  2489. }
  2490. static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg)
  2491. {
  2492. void __user *argp = (void __user *)arg;
  2493. switch (cmd) {
  2494. case MGSL_IOCGPARAMS:
  2495. return mgsl_get_params(info, argp);
  2496. case MGSL_IOCSPARAMS:
  2497. return mgsl_set_params(info, argp);
  2498. case MGSL_IOCGTXIDLE:
  2499. return mgsl_get_txidle(info, argp);
  2500. case MGSL_IOCSTXIDLE:
  2501. return mgsl_set_txidle(info,(int)arg);
  2502. case MGSL_IOCTXENABLE:
  2503. return mgsl_txenable(info,(int)arg);
  2504. case MGSL_IOCRXENABLE:
  2505. return mgsl_rxenable(info,(int)arg);
  2506. case MGSL_IOCTXABORT:
  2507. return mgsl_txabort(info);
  2508. case MGSL_IOCGSTATS:
  2509. return mgsl_get_stats(info, argp);
  2510. case MGSL_IOCWAITEVENT:
  2511. return mgsl_wait_event(info, argp);
  2512. case MGSL_IOCLOOPTXDONE:
  2513. return mgsl_loopmode_send_done(info);
  2514. /* Wait for modem input (DCD,RI,DSR,CTS) change
  2515. * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
  2516. */
  2517. case TIOCMIWAIT:
  2518. return modem_input_wait(info,(int)arg);
  2519. default:
  2520. return -ENOIOCTLCMD;
  2521. }
  2522. return 0;
  2523. }
  2524. /* mgsl_set_termios()
  2525. *
  2526. * Set new termios settings
  2527. *
  2528. * Arguments:
  2529. *
  2530. * tty pointer to tty structure
  2531. * termios pointer to buffer to hold returned old termios
  2532. *
  2533. * Return Value: None
  2534. */
  2535. static void mgsl_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
  2536. {
  2537. struct mgsl_struct *info = tty->driver_data;
  2538. unsigned long flags;
  2539. if (debug_level >= DEBUG_LEVEL_INFO)
  2540. printk("%s(%d):mgsl_set_termios %s\n", __FILE__,__LINE__,
  2541. tty->driver->name );
  2542. mgsl_change_params(info);
  2543. /* Handle transition to B0 status */
  2544. if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
  2545. info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
  2546. spin_lock_irqsave(&info->irq_spinlock,flags);
  2547. usc_set_serial_signals(info);
  2548. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  2549. }
  2550. /* Handle transition away from B0 status */
  2551. if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
  2552. info->serial_signals |= SerialSignal_DTR;
  2553. if (!C_CRTSCTS(tty) || !tty_throttled(tty))
  2554. info->serial_signals |= SerialSignal_RTS;
  2555. spin_lock_irqsave(&info->irq_spinlock,flags);
  2556. usc_set_serial_signals(info);
  2557. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  2558. }
  2559. /* Handle turning off CRTSCTS */
  2560. if (old_termios->c_cflag & CRTSCTS && !C_CRTSCTS(tty)) {
  2561. tty->hw_stopped = 0;
  2562. mgsl_start(tty);
  2563. }
  2564. } /* end of mgsl_set_termios() */
  2565. /* mgsl_close()
  2566. *
  2567. * Called when port is closed. Wait for remaining data to be
  2568. * sent. Disable port and free resources.
  2569. *
  2570. * Arguments:
  2571. *
  2572. * tty pointer to open tty structure
  2573. * filp pointer to open file object
  2574. *
  2575. * Return Value: None
  2576. */
  2577. static void mgsl_close(struct tty_struct *tty, struct file * filp)
  2578. {
  2579. struct mgsl_struct * info = tty->driver_data;
  2580. if (mgsl_paranoia_check(info, tty->name, "mgsl_close"))
  2581. return;
  2582. if (debug_level >= DEBUG_LEVEL_INFO)
  2583. printk("%s(%d):mgsl_close(%s) entry, count=%d\n",
  2584. __FILE__,__LINE__, info->device_name, info->port.count);
  2585. if (tty_port_close_start(&info->port, tty, filp) == 0)
  2586. goto cleanup;
  2587. mutex_lock(&info->port.mutex);
  2588. if (tty_port_initialized(&info->port))
  2589. mgsl_wait_until_sent(tty, info->timeout);
  2590. mgsl_flush_buffer(tty);
  2591. tty_ldisc_flush(tty);
  2592. shutdown(info);
  2593. mutex_unlock(&info->port.mutex);
  2594. tty_port_close_end(&info->port, tty);
  2595. info->port.tty = NULL;
  2596. cleanup:
  2597. if (debug_level >= DEBUG_LEVEL_INFO)
  2598. printk("%s(%d):mgsl_close(%s) exit, count=%d\n", __FILE__,__LINE__,
  2599. tty->driver->name, info->port.count);
  2600. } /* end of mgsl_close() */
  2601. /* mgsl_wait_until_sent()
  2602. *
  2603. * Wait until the transmitter is empty.
  2604. *
  2605. * Arguments:
  2606. *
  2607. * tty pointer to tty info structure
  2608. * timeout time to wait for send completion
  2609. *
  2610. * Return Value: None
  2611. */
  2612. static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout)
  2613. {
  2614. struct mgsl_struct * info = tty->driver_data;
  2615. unsigned long orig_jiffies, char_time;
  2616. if (!info )
  2617. return;
  2618. if (debug_level >= DEBUG_LEVEL_INFO)
  2619. printk("%s(%d):mgsl_wait_until_sent(%s) entry\n",
  2620. __FILE__,__LINE__, info->device_name );
  2621. if (mgsl_paranoia_check(info, tty->name, "mgsl_wait_until_sent"))
  2622. return;
  2623. if (!tty_port_initialized(&info->port))
  2624. goto exit;
  2625. orig_jiffies = jiffies;
  2626. /* Set check interval to 1/5 of estimated time to
  2627. * send a character, and make it at least 1. The check
  2628. * interval should also be less than the timeout.
  2629. * Note: use tight timings here to satisfy the NIST-PCTS.
  2630. */
  2631. if ( info->params.data_rate ) {
  2632. char_time = info->timeout/(32 * 5);
  2633. if (!char_time)
  2634. char_time++;
  2635. } else
  2636. char_time = 1;
  2637. if (timeout)
  2638. char_time = min_t(unsigned long, char_time, timeout);
  2639. if ( info->params.mode == MGSL_MODE_HDLC ||
  2640. info->params.mode == MGSL_MODE_RAW ) {
  2641. while (info->tx_active) {
  2642. msleep_interruptible(jiffies_to_msecs(char_time));
  2643. if (signal_pending(current))
  2644. break;
  2645. if (timeout && time_after(jiffies, orig_jiffies + timeout))
  2646. break;
  2647. }
  2648. } else {
  2649. while (!(usc_InReg(info,TCSR) & TXSTATUS_ALL_SENT) &&
  2650. info->tx_enabled) {
  2651. msleep_interruptible(jiffies_to_msecs(char_time));
  2652. if (signal_pending(current))
  2653. break;
  2654. if (timeout && time_after(jiffies, orig_jiffies + timeout))
  2655. break;
  2656. }
  2657. }
  2658. exit:
  2659. if (debug_level >= DEBUG_LEVEL_INFO)
  2660. printk("%s(%d):mgsl_wait_until_sent(%s) exit\n",
  2661. __FILE__,__LINE__, info->device_name );
  2662. } /* end of mgsl_wait_until_sent() */
  2663. /* mgsl_hangup()
  2664. *
  2665. * Called by tty_hangup() when a hangup is signaled.
  2666. * This is the same as to closing all open files for the port.
  2667. *
  2668. * Arguments: tty pointer to associated tty object
  2669. * Return Value: None
  2670. */
  2671. static void mgsl_hangup(struct tty_struct *tty)
  2672. {
  2673. struct mgsl_struct * info = tty->driver_data;
  2674. if (debug_level >= DEBUG_LEVEL_INFO)
  2675. printk("%s(%d):mgsl_hangup(%s)\n",
  2676. __FILE__,__LINE__, info->device_name );
  2677. if (mgsl_paranoia_check(info, tty->name, "mgsl_hangup"))
  2678. return;
  2679. mgsl_flush_buffer(tty);
  2680. shutdown(info);
  2681. info->port.count = 0;
  2682. tty_port_set_active(&info->port, 0);
  2683. info->port.tty = NULL;
  2684. wake_up_interruptible(&info->port.open_wait);
  2685. } /* end of mgsl_hangup() */
  2686. /*
  2687. * carrier_raised()
  2688. *
  2689. * Return true if carrier is raised
  2690. */
  2691. static int carrier_raised(struct tty_port *port)
  2692. {
  2693. unsigned long flags;
  2694. struct mgsl_struct *info = container_of(port, struct mgsl_struct, port);
  2695. spin_lock_irqsave(&info->irq_spinlock, flags);
  2696. usc_get_serial_signals(info);
  2697. spin_unlock_irqrestore(&info->irq_spinlock, flags);
  2698. return (info->serial_signals & SerialSignal_DCD) ? 1 : 0;
  2699. }
  2700. static void dtr_rts(struct tty_port *port, int on)
  2701. {
  2702. struct mgsl_struct *info = container_of(port, struct mgsl_struct, port);
  2703. unsigned long flags;
  2704. spin_lock_irqsave(&info->irq_spinlock,flags);
  2705. if (on)
  2706. info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
  2707. else
  2708. info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
  2709. usc_set_serial_signals(info);
  2710. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  2711. }
  2712. /* block_til_ready()
  2713. *
  2714. * Block the current process until the specified port
  2715. * is ready to be opened.
  2716. *
  2717. * Arguments:
  2718. *
  2719. * tty pointer to tty info structure
  2720. * filp pointer to open file object
  2721. * info pointer to device instance data
  2722. *
  2723. * Return Value: 0 if success, otherwise error code
  2724. */
  2725. static int block_til_ready(struct tty_struct *tty, struct file * filp,
  2726. struct mgsl_struct *info)
  2727. {
  2728. DECLARE_WAITQUEUE(wait, current);
  2729. int retval;
  2730. bool do_clocal = false;
  2731. unsigned long flags;
  2732. int dcd;
  2733. struct tty_port *port = &info->port;
  2734. if (debug_level >= DEBUG_LEVEL_INFO)
  2735. printk("%s(%d):block_til_ready on %s\n",
  2736. __FILE__,__LINE__, tty->driver->name );
  2737. if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) {
  2738. /* nonblock mode is set or port is not enabled */
  2739. tty_port_set_active(port, 1);
  2740. return 0;
  2741. }
  2742. if (C_CLOCAL(tty))
  2743. do_clocal = true;
  2744. /* Wait for carrier detect and the line to become
  2745. * free (i.e., not in use by the callout). While we are in
  2746. * this loop, port->count is dropped by one, so that
  2747. * mgsl_close() knows when to free things. We restore it upon
  2748. * exit, either normal or abnormal.
  2749. */
  2750. retval = 0;
  2751. add_wait_queue(&port->open_wait, &wait);
  2752. if (debug_level >= DEBUG_LEVEL_INFO)
  2753. printk("%s(%d):block_til_ready before block on %s count=%d\n",
  2754. __FILE__,__LINE__, tty->driver->name, port->count );
  2755. spin_lock_irqsave(&info->irq_spinlock, flags);
  2756. port->count--;
  2757. spin_unlock_irqrestore(&info->irq_spinlock, flags);
  2758. port->blocked_open++;
  2759. while (1) {
  2760. if (C_BAUD(tty) && tty_port_initialized(port))
  2761. tty_port_raise_dtr_rts(port);
  2762. set_current_state(TASK_INTERRUPTIBLE);
  2763. if (tty_hung_up_p(filp) || !tty_port_initialized(port)) {
  2764. retval = (port->flags & ASYNC_HUP_NOTIFY) ?
  2765. -EAGAIN : -ERESTARTSYS;
  2766. break;
  2767. }
  2768. dcd = tty_port_carrier_raised(&info->port);
  2769. if (do_clocal || dcd)
  2770. break;
  2771. if (signal_pending(current)) {
  2772. retval = -ERESTARTSYS;
  2773. break;
  2774. }
  2775. if (debug_level >= DEBUG_LEVEL_INFO)
  2776. printk("%s(%d):block_til_ready blocking on %s count=%d\n",
  2777. __FILE__,__LINE__, tty->driver->name, port->count );
  2778. tty_unlock(tty);
  2779. schedule();
  2780. tty_lock(tty);
  2781. }
  2782. set_current_state(TASK_RUNNING);
  2783. remove_wait_queue(&port->open_wait, &wait);
  2784. /* FIXME: Racy on hangup during close wait */
  2785. if (!tty_hung_up_p(filp))
  2786. port->count++;
  2787. port->blocked_open--;
  2788. if (debug_level >= DEBUG_LEVEL_INFO)
  2789. printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
  2790. __FILE__,__LINE__, tty->driver->name, port->count );
  2791. if (!retval)
  2792. tty_port_set_active(port, 1);
  2793. return retval;
  2794. } /* end of block_til_ready() */
  2795. static int mgsl_install(struct tty_driver *driver, struct tty_struct *tty)
  2796. {
  2797. struct mgsl_struct *info;
  2798. int line = tty->index;
  2799. /* verify range of specified line number */
  2800. if (line >= mgsl_device_count) {
  2801. printk("%s(%d):mgsl_open with invalid line #%d.\n",
  2802. __FILE__, __LINE__, line);
  2803. return -ENODEV;
  2804. }
  2805. /* find the info structure for the specified line */
  2806. info = mgsl_device_list;
  2807. while (info && info->line != line)
  2808. info = info->next_device;
  2809. if (mgsl_paranoia_check(info, tty->name, "mgsl_open"))
  2810. return -ENODEV;
  2811. tty->driver_data = info;
  2812. return tty_port_install(&info->port, driver, tty);
  2813. }
  2814. /* mgsl_open()
  2815. *
  2816. * Called when a port is opened. Init and enable port.
  2817. * Perform serial-specific initialization for the tty structure.
  2818. *
  2819. * Arguments: tty pointer to tty info structure
  2820. * filp associated file pointer
  2821. *
  2822. * Return Value: 0 if success, otherwise error code
  2823. */
  2824. static int mgsl_open(struct tty_struct *tty, struct file * filp)
  2825. {
  2826. struct mgsl_struct *info = tty->driver_data;
  2827. unsigned long flags;
  2828. int retval;
  2829. info->port.tty = tty;
  2830. if (debug_level >= DEBUG_LEVEL_INFO)
  2831. printk("%s(%d):mgsl_open(%s), old ref count = %d\n",
  2832. __FILE__,__LINE__,tty->driver->name, info->port.count);
  2833. info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
  2834. spin_lock_irqsave(&info->netlock, flags);
  2835. if (info->netcount) {
  2836. retval = -EBUSY;
  2837. spin_unlock_irqrestore(&info->netlock, flags);
  2838. goto cleanup;
  2839. }
  2840. info->port.count++;
  2841. spin_unlock_irqrestore(&info->netlock, flags);
  2842. if (info->port.count == 1) {
  2843. /* 1st open on this device, init hardware */
  2844. retval = startup(info);
  2845. if (retval < 0)
  2846. goto cleanup;
  2847. }
  2848. retval = block_til_ready(tty, filp, info);
  2849. if (retval) {
  2850. if (debug_level >= DEBUG_LEVEL_INFO)
  2851. printk("%s(%d):block_til_ready(%s) returned %d\n",
  2852. __FILE__,__LINE__, info->device_name, retval);
  2853. goto cleanup;
  2854. }
  2855. if (debug_level >= DEBUG_LEVEL_INFO)
  2856. printk("%s(%d):mgsl_open(%s) success\n",
  2857. __FILE__,__LINE__, info->device_name);
  2858. retval = 0;
  2859. cleanup:
  2860. if (retval) {
  2861. if (tty->count == 1)
  2862. info->port.tty = NULL; /* tty layer will release tty struct */
  2863. if(info->port.count)
  2864. info->port.count--;
  2865. }
  2866. return retval;
  2867. } /* end of mgsl_open() */
  2868. /*
  2869. * /proc fs routines....
  2870. */
  2871. static inline void line_info(struct seq_file *m, struct mgsl_struct *info)
  2872. {
  2873. char stat_buf[30];
  2874. unsigned long flags;
  2875. seq_printf(m, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
  2876. info->device_name, info->io_base, info->irq_level,
  2877. info->phys_memory_base, info->phys_lcr_base);
  2878. /* output current serial signal states */
  2879. spin_lock_irqsave(&info->irq_spinlock,flags);
  2880. usc_get_serial_signals(info);
  2881. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  2882. stat_buf[0] = 0;
  2883. stat_buf[1] = 0;
  2884. if (info->serial_signals & SerialSignal_RTS)
  2885. strcat(stat_buf, "|RTS");
  2886. if (info->serial_signals & SerialSignal_CTS)
  2887. strcat(stat_buf, "|CTS");
  2888. if (info->serial_signals & SerialSignal_DTR)
  2889. strcat(stat_buf, "|DTR");
  2890. if (info->serial_signals & SerialSignal_DSR)
  2891. strcat(stat_buf, "|DSR");
  2892. if (info->serial_signals & SerialSignal_DCD)
  2893. strcat(stat_buf, "|CD");
  2894. if (info->serial_signals & SerialSignal_RI)
  2895. strcat(stat_buf, "|RI");
  2896. if (info->params.mode == MGSL_MODE_HDLC ||
  2897. info->params.mode == MGSL_MODE_RAW ) {
  2898. seq_printf(m, " HDLC txok:%d rxok:%d",
  2899. info->icount.txok, info->icount.rxok);
  2900. if (info->icount.txunder)
  2901. seq_printf(m, " txunder:%d", info->icount.txunder);
  2902. if (info->icount.txabort)
  2903. seq_printf(m, " txabort:%d", info->icount.txabort);
  2904. if (info->icount.rxshort)
  2905. seq_printf(m, " rxshort:%d", info->icount.rxshort);
  2906. if (info->icount.rxlong)
  2907. seq_printf(m, " rxlong:%d", info->icount.rxlong);
  2908. if (info->icount.rxover)
  2909. seq_printf(m, " rxover:%d", info->icount.rxover);
  2910. if (info->icount.rxcrc)
  2911. seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
  2912. } else {
  2913. seq_printf(m, " ASYNC tx:%d rx:%d",
  2914. info->icount.tx, info->icount.rx);
  2915. if (info->icount.frame)
  2916. seq_printf(m, " fe:%d", info->icount.frame);
  2917. if (info->icount.parity)
  2918. seq_printf(m, " pe:%d", info->icount.parity);
  2919. if (info->icount.brk)
  2920. seq_printf(m, " brk:%d", info->icount.brk);
  2921. if (info->icount.overrun)
  2922. seq_printf(m, " oe:%d", info->icount.overrun);
  2923. }
  2924. /* Append serial signal status to end */
  2925. seq_printf(m, " %s\n", stat_buf+1);
  2926. seq_printf(m, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
  2927. info->tx_active,info->bh_requested,info->bh_running,
  2928. info->pending_bh);
  2929. spin_lock_irqsave(&info->irq_spinlock,flags);
  2930. {
  2931. u16 Tcsr = usc_InReg( info, TCSR );
  2932. u16 Tdmr = usc_InDmaReg( info, TDMR );
  2933. u16 Ticr = usc_InReg( info, TICR );
  2934. u16 Rscr = usc_InReg( info, RCSR );
  2935. u16 Rdmr = usc_InDmaReg( info, RDMR );
  2936. u16 Ricr = usc_InReg( info, RICR );
  2937. u16 Icr = usc_InReg( info, ICR );
  2938. u16 Dccr = usc_InReg( info, DCCR );
  2939. u16 Tmr = usc_InReg( info, TMR );
  2940. u16 Tccr = usc_InReg( info, TCCR );
  2941. u16 Ccar = inw( info->io_base + CCAR );
  2942. seq_printf(m, "tcsr=%04X tdmr=%04X ticr=%04X rcsr=%04X rdmr=%04X\n"
  2943. "ricr=%04X icr =%04X dccr=%04X tmr=%04X tccr=%04X ccar=%04X\n",
  2944. Tcsr,Tdmr,Ticr,Rscr,Rdmr,Ricr,Icr,Dccr,Tmr,Tccr,Ccar );
  2945. }
  2946. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  2947. }
  2948. /* Called to print information about devices */
  2949. static int mgsl_proc_show(struct seq_file *m, void *v)
  2950. {
  2951. struct mgsl_struct *info;
  2952. seq_printf(m, "synclink driver:%s\n", driver_version);
  2953. info = mgsl_device_list;
  2954. while( info ) {
  2955. line_info(m, info);
  2956. info = info->next_device;
  2957. }
  2958. return 0;
  2959. }
  2960. /* mgsl_allocate_dma_buffers()
  2961. *
  2962. * Allocate and format DMA buffers (ISA adapter)
  2963. * or format shared memory buffers (PCI adapter).
  2964. *
  2965. * Arguments: info pointer to device instance data
  2966. * Return Value: 0 if success, otherwise error
  2967. */
  2968. static int mgsl_allocate_dma_buffers(struct mgsl_struct *info)
  2969. {
  2970. unsigned short BuffersPerFrame;
  2971. info->last_mem_alloc = 0;
  2972. /* Calculate the number of DMA buffers necessary to hold the */
  2973. /* largest allowable frame size. Note: If the max frame size is */
  2974. /* not an even multiple of the DMA buffer size then we need to */
  2975. /* round the buffer count per frame up one. */
  2976. BuffersPerFrame = (unsigned short)(info->max_frame_size/DMABUFFERSIZE);
  2977. if ( info->max_frame_size % DMABUFFERSIZE )
  2978. BuffersPerFrame++;
  2979. /*
  2980. * The PCI adapter has 256KBytes of shared memory to use. This is 64
  2981. * PAGE_SIZE buffers.
  2982. *
  2983. * The first page is used for padding at this time so the buffer list
  2984. * does not begin at offset 0 of the PCI adapter's shared memory.
  2985. *
  2986. * The 2nd page is used for the buffer list. A 4K buffer list can hold
  2987. * 128 DMA_BUFFER structures at 32 bytes each.
  2988. *
  2989. * This leaves 62 4K pages.
  2990. *
  2991. * The next N pages are used for transmit frame(s). We reserve enough
  2992. * 4K page blocks to hold the required number of transmit dma buffers
  2993. * (num_tx_dma_buffers), each of MaxFrameSize size.
  2994. *
  2995. * Of the remaining pages (62-N), determine how many can be used to
  2996. * receive full MaxFrameSize inbound frames
  2997. */
  2998. info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
  2999. info->rx_buffer_count = 62 - info->tx_buffer_count;
  3000. if ( debug_level >= DEBUG_LEVEL_INFO )
  3001. printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n",
  3002. __FILE__,__LINE__, info->tx_buffer_count,info->rx_buffer_count);
  3003. if ( mgsl_alloc_buffer_list_memory( info ) < 0 ||
  3004. mgsl_alloc_frame_memory(info, info->rx_buffer_list, info->rx_buffer_count) < 0 ||
  3005. mgsl_alloc_frame_memory(info, info->tx_buffer_list, info->tx_buffer_count) < 0 ||
  3006. mgsl_alloc_intermediate_rxbuffer_memory(info) < 0 ||
  3007. mgsl_alloc_intermediate_txbuffer_memory(info) < 0 ) {
  3008. printk("%s(%d):Can't allocate DMA buffer memory\n",__FILE__,__LINE__);
  3009. return -ENOMEM;
  3010. }
  3011. mgsl_reset_rx_dma_buffers( info );
  3012. mgsl_reset_tx_dma_buffers( info );
  3013. return 0;
  3014. } /* end of mgsl_allocate_dma_buffers() */
  3015. /*
  3016. * mgsl_alloc_buffer_list_memory()
  3017. *
  3018. * Allocate a common DMA buffer for use as the
  3019. * receive and transmit buffer lists.
  3020. *
  3021. * A buffer list is a set of buffer entries where each entry contains
  3022. * a pointer to an actual buffer and a pointer to the next buffer entry
  3023. * (plus some other info about the buffer).
  3024. *
  3025. * The buffer entries for a list are built to form a circular list so
  3026. * that when the entire list has been traversed you start back at the
  3027. * beginning.
  3028. *
  3029. * This function allocates memory for just the buffer entries.
  3030. * The links (pointer to next entry) are filled in with the physical
  3031. * address of the next entry so the adapter can navigate the list
  3032. * using bus master DMA. The pointers to the actual buffers are filled
  3033. * out later when the actual buffers are allocated.
  3034. *
  3035. * Arguments: info pointer to device instance data
  3036. * Return Value: 0 if success, otherwise error
  3037. */
  3038. static int mgsl_alloc_buffer_list_memory( struct mgsl_struct *info )
  3039. {
  3040. unsigned int i;
  3041. /* PCI adapter uses shared memory. */
  3042. info->buffer_list = info->memory_base + info->last_mem_alloc;
  3043. info->buffer_list_phys = info->last_mem_alloc;
  3044. info->last_mem_alloc += BUFFERLISTSIZE;
  3045. /* We got the memory for the buffer entry lists. */
  3046. /* Initialize the memory block to all zeros. */
  3047. memset( info->buffer_list, 0, BUFFERLISTSIZE );
  3048. /* Save virtual address pointers to the receive and */
  3049. /* transmit buffer lists. (Receive 1st). These pointers will */
  3050. /* be used by the processor to access the lists. */
  3051. info->rx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
  3052. info->tx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
  3053. info->tx_buffer_list += info->rx_buffer_count;
  3054. /*
  3055. * Build the links for the buffer entry lists such that
  3056. * two circular lists are built. (Transmit and Receive).
  3057. *
  3058. * Note: the links are physical addresses
  3059. * which are read by the adapter to determine the next
  3060. * buffer entry to use.
  3061. */
  3062. for ( i = 0; i < info->rx_buffer_count; i++ ) {
  3063. /* calculate and store physical address of this buffer entry */
  3064. info->rx_buffer_list[i].phys_entry =
  3065. info->buffer_list_phys + (i * sizeof(DMABUFFERENTRY));
  3066. /* calculate and store physical address of */
  3067. /* next entry in cirular list of entries */
  3068. info->rx_buffer_list[i].link = info->buffer_list_phys;
  3069. if ( i < info->rx_buffer_count - 1 )
  3070. info->rx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
  3071. }
  3072. for ( i = 0; i < info->tx_buffer_count; i++ ) {
  3073. /* calculate and store physical address of this buffer entry */
  3074. info->tx_buffer_list[i].phys_entry = info->buffer_list_phys +
  3075. ((info->rx_buffer_count + i) * sizeof(DMABUFFERENTRY));
  3076. /* calculate and store physical address of */
  3077. /* next entry in cirular list of entries */
  3078. info->tx_buffer_list[i].link = info->buffer_list_phys +
  3079. info->rx_buffer_count * sizeof(DMABUFFERENTRY);
  3080. if ( i < info->tx_buffer_count - 1 )
  3081. info->tx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
  3082. }
  3083. return 0;
  3084. } /* end of mgsl_alloc_buffer_list_memory() */
  3085. /* Free DMA buffers allocated for use as the
  3086. * receive and transmit buffer lists.
  3087. * Warning:
  3088. *
  3089. * The data transfer buffers associated with the buffer list
  3090. * MUST be freed before freeing the buffer list itself because
  3091. * the buffer list contains the information necessary to free
  3092. * the individual buffers!
  3093. */
  3094. static void mgsl_free_buffer_list_memory( struct mgsl_struct *info )
  3095. {
  3096. info->buffer_list = NULL;
  3097. info->rx_buffer_list = NULL;
  3098. info->tx_buffer_list = NULL;
  3099. } /* end of mgsl_free_buffer_list_memory() */
  3100. /*
  3101. * mgsl_alloc_frame_memory()
  3102. *
  3103. * Allocate the frame DMA buffers used by the specified buffer list.
  3104. * Each DMA buffer will be one memory page in size. This is necessary
  3105. * because memory can fragment enough that it may be impossible
  3106. * contiguous pages.
  3107. *
  3108. * Arguments:
  3109. *
  3110. * info pointer to device instance data
  3111. * BufferList pointer to list of buffer entries
  3112. * Buffercount count of buffer entries in buffer list
  3113. *
  3114. * Return Value: 0 if success, otherwise -ENOMEM
  3115. */
  3116. static int mgsl_alloc_frame_memory(struct mgsl_struct *info,DMABUFFERENTRY *BufferList,int Buffercount)
  3117. {
  3118. int i;
  3119. /* Allocate page sized buffers for the receive buffer list */
  3120. for ( i = 0; i < Buffercount; i++ ) {
  3121. BufferList[i].virt_addr = info->memory_base + info->last_mem_alloc;
  3122. BufferList[i].phys_addr = info->last_mem_alloc;
  3123. info->last_mem_alloc += DMABUFFERSIZE;
  3124. }
  3125. return 0;
  3126. } /* end of mgsl_alloc_frame_memory() */
  3127. /*
  3128. * mgsl_free_frame_memory()
  3129. *
  3130. * Free the buffers associated with
  3131. * each buffer entry of a buffer list.
  3132. *
  3133. * Arguments:
  3134. *
  3135. * info pointer to device instance data
  3136. * BufferList pointer to list of buffer entries
  3137. * Buffercount count of buffer entries in buffer list
  3138. *
  3139. * Return Value: None
  3140. */
  3141. static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList, int Buffercount)
  3142. {
  3143. int i;
  3144. if ( BufferList ) {
  3145. for ( i = 0 ; i < Buffercount ; i++ ) {
  3146. if ( BufferList[i].virt_addr ) {
  3147. BufferList[i].virt_addr = NULL;
  3148. }
  3149. }
  3150. }
  3151. } /* end of mgsl_free_frame_memory() */
  3152. /* mgsl_free_dma_buffers()
  3153. *
  3154. * Free DMA buffers
  3155. *
  3156. * Arguments: info pointer to device instance data
  3157. * Return Value: None
  3158. */
  3159. static void mgsl_free_dma_buffers( struct mgsl_struct *info )
  3160. {
  3161. mgsl_free_frame_memory( info, info->rx_buffer_list, info->rx_buffer_count );
  3162. mgsl_free_frame_memory( info, info->tx_buffer_list, info->tx_buffer_count );
  3163. mgsl_free_buffer_list_memory( info );
  3164. } /* end of mgsl_free_dma_buffers() */
  3165. /*
  3166. * mgsl_alloc_intermediate_rxbuffer_memory()
  3167. *
  3168. * Allocate a buffer large enough to hold max_frame_size. This buffer
  3169. * is used to pass an assembled frame to the line discipline.
  3170. *
  3171. * Arguments:
  3172. *
  3173. * info pointer to device instance data
  3174. *
  3175. * Return Value: 0 if success, otherwise -ENOMEM
  3176. */
  3177. static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info)
  3178. {
  3179. info->intermediate_rxbuffer = kmalloc(info->max_frame_size, GFP_KERNEL | GFP_DMA);
  3180. if ( info->intermediate_rxbuffer == NULL )
  3181. return -ENOMEM;
  3182. /* unused flag buffer to satisfy receive_buf calling interface */
  3183. info->flag_buf = kzalloc(info->max_frame_size, GFP_KERNEL);
  3184. if (!info->flag_buf) {
  3185. kfree(info->intermediate_rxbuffer);
  3186. info->intermediate_rxbuffer = NULL;
  3187. return -ENOMEM;
  3188. }
  3189. return 0;
  3190. } /* end of mgsl_alloc_intermediate_rxbuffer_memory() */
  3191. /*
  3192. * mgsl_free_intermediate_rxbuffer_memory()
  3193. *
  3194. *
  3195. * Arguments:
  3196. *
  3197. * info pointer to device instance data
  3198. *
  3199. * Return Value: None
  3200. */
  3201. static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info)
  3202. {
  3203. kfree(info->intermediate_rxbuffer);
  3204. info->intermediate_rxbuffer = NULL;
  3205. kfree(info->flag_buf);
  3206. info->flag_buf = NULL;
  3207. } /* end of mgsl_free_intermediate_rxbuffer_memory() */
  3208. /*
  3209. * mgsl_alloc_intermediate_txbuffer_memory()
  3210. *
  3211. * Allocate intermdiate transmit buffer(s) large enough to hold max_frame_size.
  3212. * This buffer is used to load transmit frames into the adapter's dma transfer
  3213. * buffers when there is sufficient space.
  3214. *
  3215. * Arguments:
  3216. *
  3217. * info pointer to device instance data
  3218. *
  3219. * Return Value: 0 if success, otherwise -ENOMEM
  3220. */
  3221. static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info)
  3222. {
  3223. int i;
  3224. if ( debug_level >= DEBUG_LEVEL_INFO )
  3225. printk("%s %s(%d) allocating %d tx holding buffers\n",
  3226. info->device_name, __FILE__,__LINE__,info->num_tx_holding_buffers);
  3227. memset(info->tx_holding_buffers,0,sizeof(info->tx_holding_buffers));
  3228. for ( i=0; i<info->num_tx_holding_buffers; ++i) {
  3229. info->tx_holding_buffers[i].buffer =
  3230. kmalloc(info->max_frame_size, GFP_KERNEL);
  3231. if (info->tx_holding_buffers[i].buffer == NULL) {
  3232. for (--i; i >= 0; i--) {
  3233. kfree(info->tx_holding_buffers[i].buffer);
  3234. info->tx_holding_buffers[i].buffer = NULL;
  3235. }
  3236. return -ENOMEM;
  3237. }
  3238. }
  3239. return 0;
  3240. } /* end of mgsl_alloc_intermediate_txbuffer_memory() */
  3241. /*
  3242. * mgsl_free_intermediate_txbuffer_memory()
  3243. *
  3244. *
  3245. * Arguments:
  3246. *
  3247. * info pointer to device instance data
  3248. *
  3249. * Return Value: None
  3250. */
  3251. static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info)
  3252. {
  3253. int i;
  3254. for ( i=0; i<info->num_tx_holding_buffers; ++i ) {
  3255. kfree(info->tx_holding_buffers[i].buffer);
  3256. info->tx_holding_buffers[i].buffer = NULL;
  3257. }
  3258. info->get_tx_holding_index = 0;
  3259. info->put_tx_holding_index = 0;
  3260. info->tx_holding_count = 0;
  3261. } /* end of mgsl_free_intermediate_txbuffer_memory() */
  3262. /*
  3263. * load_next_tx_holding_buffer()
  3264. *
  3265. * attempts to load the next buffered tx request into the
  3266. * tx dma buffers
  3267. *
  3268. * Arguments:
  3269. *
  3270. * info pointer to device instance data
  3271. *
  3272. * Return Value: true if next buffered tx request loaded
  3273. * into adapter's tx dma buffer,
  3274. * false otherwise
  3275. */
  3276. static bool load_next_tx_holding_buffer(struct mgsl_struct *info)
  3277. {
  3278. bool ret = false;
  3279. if ( info->tx_holding_count ) {
  3280. /* determine if we have enough tx dma buffers
  3281. * to accommodate the next tx frame
  3282. */
  3283. struct tx_holding_buffer *ptx =
  3284. &info->tx_holding_buffers[info->get_tx_holding_index];
  3285. int num_free = num_free_tx_dma_buffers(info);
  3286. int num_needed = ptx->buffer_size / DMABUFFERSIZE;
  3287. if ( ptx->buffer_size % DMABUFFERSIZE )
  3288. ++num_needed;
  3289. if (num_needed <= num_free) {
  3290. info->xmit_cnt = ptx->buffer_size;
  3291. mgsl_load_tx_dma_buffer(info,ptx->buffer,ptx->buffer_size);
  3292. --info->tx_holding_count;
  3293. if ( ++info->get_tx_holding_index >= info->num_tx_holding_buffers)
  3294. info->get_tx_holding_index=0;
  3295. /* restart transmit timer */
  3296. mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(5000));
  3297. ret = true;
  3298. }
  3299. }
  3300. return ret;
  3301. }
  3302. /*
  3303. * save_tx_buffer_request()
  3304. *
  3305. * attempt to store transmit frame request for later transmission
  3306. *
  3307. * Arguments:
  3308. *
  3309. * info pointer to device instance data
  3310. * Buffer pointer to buffer containing frame to load
  3311. * BufferSize size in bytes of frame in Buffer
  3312. *
  3313. * Return Value: 1 if able to store, 0 otherwise
  3314. */
  3315. static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize)
  3316. {
  3317. struct tx_holding_buffer *ptx;
  3318. if ( info->tx_holding_count >= info->num_tx_holding_buffers ) {
  3319. return 0; /* all buffers in use */
  3320. }
  3321. ptx = &info->tx_holding_buffers[info->put_tx_holding_index];
  3322. ptx->buffer_size = BufferSize;
  3323. memcpy( ptx->buffer, Buffer, BufferSize);
  3324. ++info->tx_holding_count;
  3325. if ( ++info->put_tx_holding_index >= info->num_tx_holding_buffers)
  3326. info->put_tx_holding_index=0;
  3327. return 1;
  3328. }
  3329. static int mgsl_claim_resources(struct mgsl_struct *info)
  3330. {
  3331. if (request_region(info->io_base,info->io_addr_size,"synclink") == NULL) {
  3332. printk( "%s(%d):I/O address conflict on device %s Addr=%08X\n",
  3333. __FILE__,__LINE__,info->device_name, info->io_base);
  3334. return -ENODEV;
  3335. }
  3336. info->io_addr_requested = true;
  3337. if ( request_irq(info->irq_level,mgsl_interrupt,info->irq_flags,
  3338. info->device_name, info ) < 0 ) {
  3339. printk( "%s(%d):Can't request interrupt on device %s IRQ=%d\n",
  3340. __FILE__,__LINE__,info->device_name, info->irq_level );
  3341. goto errout;
  3342. }
  3343. info->irq_requested = true;
  3344. if (request_mem_region(info->phys_memory_base,0x40000,"synclink") == NULL) {
  3345. printk( "%s(%d):mem addr conflict device %s Addr=%08X\n",
  3346. __FILE__,__LINE__,info->device_name, info->phys_memory_base);
  3347. goto errout;
  3348. }
  3349. info->shared_mem_requested = true;
  3350. if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclink") == NULL) {
  3351. printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n",
  3352. __FILE__,__LINE__,info->device_name, info->phys_lcr_base + info->lcr_offset);
  3353. goto errout;
  3354. }
  3355. info->lcr_mem_requested = true;
  3356. info->memory_base = ioremap(info->phys_memory_base, 0x40000);
  3357. if (!info->memory_base) {
  3358. printk( "%s(%d):Can't map shared memory on device %s MemAddr=%08X\n",
  3359. __FILE__,__LINE__,info->device_name, info->phys_memory_base );
  3360. goto errout;
  3361. }
  3362. if ( !mgsl_memory_test(info) ) {
  3363. printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
  3364. __FILE__,__LINE__,info->device_name, info->phys_memory_base );
  3365. goto errout;
  3366. }
  3367. info->lcr_base = ioremap(info->phys_lcr_base, PAGE_SIZE);
  3368. if (!info->lcr_base) {
  3369. printk( "%s(%d):Can't map LCR memory on device %s MemAddr=%08X\n",
  3370. __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
  3371. goto errout;
  3372. }
  3373. info->lcr_base += info->lcr_offset;
  3374. if ( mgsl_allocate_dma_buffers(info) < 0 ) {
  3375. printk( "%s(%d):Can't allocate DMA buffers on device %s DMA=%d\n",
  3376. __FILE__,__LINE__,info->device_name, info->dma_level );
  3377. goto errout;
  3378. }
  3379. return 0;
  3380. errout:
  3381. mgsl_release_resources(info);
  3382. return -ENODEV;
  3383. } /* end of mgsl_claim_resources() */
  3384. static void mgsl_release_resources(struct mgsl_struct *info)
  3385. {
  3386. if ( debug_level >= DEBUG_LEVEL_INFO )
  3387. printk( "%s(%d):mgsl_release_resources(%s) entry\n",
  3388. __FILE__,__LINE__,info->device_name );
  3389. if ( info->irq_requested ) {
  3390. free_irq(info->irq_level, info);
  3391. info->irq_requested = false;
  3392. }
  3393. if ( info->dma_requested ) {
  3394. disable_dma(info->dma_level);
  3395. free_dma(info->dma_level);
  3396. info->dma_requested = false;
  3397. }
  3398. mgsl_free_dma_buffers(info);
  3399. mgsl_free_intermediate_rxbuffer_memory(info);
  3400. mgsl_free_intermediate_txbuffer_memory(info);
  3401. if ( info->io_addr_requested ) {
  3402. release_region(info->io_base,info->io_addr_size);
  3403. info->io_addr_requested = false;
  3404. }
  3405. if ( info->shared_mem_requested ) {
  3406. release_mem_region(info->phys_memory_base,0x40000);
  3407. info->shared_mem_requested = false;
  3408. }
  3409. if ( info->lcr_mem_requested ) {
  3410. release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
  3411. info->lcr_mem_requested = false;
  3412. }
  3413. if (info->memory_base){
  3414. iounmap(info->memory_base);
  3415. info->memory_base = NULL;
  3416. }
  3417. if (info->lcr_base){
  3418. iounmap(info->lcr_base - info->lcr_offset);
  3419. info->lcr_base = NULL;
  3420. }
  3421. if ( debug_level >= DEBUG_LEVEL_INFO )
  3422. printk( "%s(%d):mgsl_release_resources(%s) exit\n",
  3423. __FILE__,__LINE__,info->device_name );
  3424. } /* end of mgsl_release_resources() */
  3425. /* mgsl_add_device()
  3426. *
  3427. * Add the specified device instance data structure to the
  3428. * global linked list of devices and increment the device count.
  3429. *
  3430. * Arguments: info pointer to device instance data
  3431. * Return Value: None
  3432. */
  3433. static void mgsl_add_device( struct mgsl_struct *info )
  3434. {
  3435. info->next_device = NULL;
  3436. info->line = mgsl_device_count;
  3437. sprintf(info->device_name,"ttySL%d",info->line);
  3438. if (info->line < MAX_TOTAL_DEVICES) {
  3439. if (maxframe[info->line])
  3440. info->max_frame_size = maxframe[info->line];
  3441. if (txdmabufs[info->line]) {
  3442. info->num_tx_dma_buffers = txdmabufs[info->line];
  3443. if (info->num_tx_dma_buffers < 1)
  3444. info->num_tx_dma_buffers = 1;
  3445. }
  3446. if (txholdbufs[info->line]) {
  3447. info->num_tx_holding_buffers = txholdbufs[info->line];
  3448. if (info->num_tx_holding_buffers < 1)
  3449. info->num_tx_holding_buffers = 1;
  3450. else if (info->num_tx_holding_buffers > MAX_TX_HOLDING_BUFFERS)
  3451. info->num_tx_holding_buffers = MAX_TX_HOLDING_BUFFERS;
  3452. }
  3453. }
  3454. mgsl_device_count++;
  3455. if ( !mgsl_device_list )
  3456. mgsl_device_list = info;
  3457. else {
  3458. struct mgsl_struct *current_dev = mgsl_device_list;
  3459. while( current_dev->next_device )
  3460. current_dev = current_dev->next_device;
  3461. current_dev->next_device = info;
  3462. }
  3463. if ( info->max_frame_size < 4096 )
  3464. info->max_frame_size = 4096;
  3465. else if ( info->max_frame_size > 65535 )
  3466. info->max_frame_size = 65535;
  3467. printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n",
  3468. info->hw_version + 1, info->device_name, info->io_base, info->irq_level,
  3469. info->phys_memory_base, info->phys_lcr_base,
  3470. info->max_frame_size );
  3471. #if SYNCLINK_GENERIC_HDLC
  3472. hdlcdev_init(info);
  3473. #endif
  3474. } /* end of mgsl_add_device() */
  3475. static const struct tty_port_operations mgsl_port_ops = {
  3476. .carrier_raised = carrier_raised,
  3477. .dtr_rts = dtr_rts,
  3478. };
  3479. /* mgsl_allocate_device()
  3480. *
  3481. * Allocate and initialize a device instance structure
  3482. *
  3483. * Arguments: none
  3484. * Return Value: pointer to mgsl_struct if success, otherwise NULL
  3485. */
  3486. static struct mgsl_struct* mgsl_allocate_device(void)
  3487. {
  3488. struct mgsl_struct *info;
  3489. info = kzalloc(sizeof(struct mgsl_struct),
  3490. GFP_KERNEL);
  3491. if (!info) {
  3492. printk("Error can't allocate device instance data\n");
  3493. } else {
  3494. tty_port_init(&info->port);
  3495. info->port.ops = &mgsl_port_ops;
  3496. info->magic = MGSL_MAGIC;
  3497. INIT_WORK(&info->task, mgsl_bh_handler);
  3498. info->max_frame_size = 4096;
  3499. info->port.close_delay = 5*HZ/10;
  3500. info->port.closing_wait = 30*HZ;
  3501. init_waitqueue_head(&info->status_event_wait_q);
  3502. init_waitqueue_head(&info->event_wait_q);
  3503. spin_lock_init(&info->irq_spinlock);
  3504. spin_lock_init(&info->netlock);
  3505. memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
  3506. info->idle_mode = HDLC_TXIDLE_FLAGS;
  3507. info->num_tx_dma_buffers = 1;
  3508. info->num_tx_holding_buffers = 0;
  3509. }
  3510. return info;
  3511. } /* end of mgsl_allocate_device()*/
  3512. static const struct tty_operations mgsl_ops = {
  3513. .install = mgsl_install,
  3514. .open = mgsl_open,
  3515. .close = mgsl_close,
  3516. .write = mgsl_write,
  3517. .put_char = mgsl_put_char,
  3518. .flush_chars = mgsl_flush_chars,
  3519. .write_room = mgsl_write_room,
  3520. .chars_in_buffer = mgsl_chars_in_buffer,
  3521. .flush_buffer = mgsl_flush_buffer,
  3522. .ioctl = mgsl_ioctl,
  3523. .throttle = mgsl_throttle,
  3524. .unthrottle = mgsl_unthrottle,
  3525. .send_xchar = mgsl_send_xchar,
  3526. .break_ctl = mgsl_break,
  3527. .wait_until_sent = mgsl_wait_until_sent,
  3528. .set_termios = mgsl_set_termios,
  3529. .stop = mgsl_stop,
  3530. .start = mgsl_start,
  3531. .hangup = mgsl_hangup,
  3532. .tiocmget = tiocmget,
  3533. .tiocmset = tiocmset,
  3534. .get_icount = msgl_get_icount,
  3535. .proc_show = mgsl_proc_show,
  3536. };
  3537. /*
  3538. * perform tty device initialization
  3539. */
  3540. static int mgsl_init_tty(void)
  3541. {
  3542. int rc;
  3543. serial_driver = alloc_tty_driver(128);
  3544. if (!serial_driver)
  3545. return -ENOMEM;
  3546. serial_driver->driver_name = "synclink";
  3547. serial_driver->name = "ttySL";
  3548. serial_driver->major = ttymajor;
  3549. serial_driver->minor_start = 64;
  3550. serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
  3551. serial_driver->subtype = SERIAL_TYPE_NORMAL;
  3552. serial_driver->init_termios = tty_std_termios;
  3553. serial_driver->init_termios.c_cflag =
  3554. B9600 | CS8 | CREAD | HUPCL | CLOCAL;
  3555. serial_driver->init_termios.c_ispeed = 9600;
  3556. serial_driver->init_termios.c_ospeed = 9600;
  3557. serial_driver->flags = TTY_DRIVER_REAL_RAW;
  3558. tty_set_operations(serial_driver, &mgsl_ops);
  3559. if ((rc = tty_register_driver(serial_driver)) < 0) {
  3560. printk("%s(%d):Couldn't register serial driver\n",
  3561. __FILE__,__LINE__);
  3562. put_tty_driver(serial_driver);
  3563. serial_driver = NULL;
  3564. return rc;
  3565. }
  3566. printk("%s %s, tty major#%d\n",
  3567. driver_name, driver_version,
  3568. serial_driver->major);
  3569. return 0;
  3570. }
  3571. static void synclink_cleanup(void)
  3572. {
  3573. int rc;
  3574. struct mgsl_struct *info;
  3575. struct mgsl_struct *tmp;
  3576. printk("Unloading %s: %s\n", driver_name, driver_version);
  3577. if (serial_driver) {
  3578. rc = tty_unregister_driver(serial_driver);
  3579. if (rc)
  3580. printk("%s(%d) failed to unregister tty driver err=%d\n",
  3581. __FILE__,__LINE__,rc);
  3582. put_tty_driver(serial_driver);
  3583. }
  3584. info = mgsl_device_list;
  3585. while(info) {
  3586. #if SYNCLINK_GENERIC_HDLC
  3587. hdlcdev_exit(info);
  3588. #endif
  3589. mgsl_release_resources(info);
  3590. tmp = info;
  3591. info = info->next_device;
  3592. tty_port_destroy(&tmp->port);
  3593. kfree(tmp);
  3594. }
  3595. if (pci_registered)
  3596. pci_unregister_driver(&synclink_pci_driver);
  3597. }
  3598. static int __init synclink_init(void)
  3599. {
  3600. int rc;
  3601. if (break_on_load) {
  3602. mgsl_get_text_ptr();
  3603. BREAKPOINT();
  3604. }
  3605. printk("%s %s\n", driver_name, driver_version);
  3606. if ((rc = pci_register_driver(&synclink_pci_driver)) < 0)
  3607. printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
  3608. else
  3609. pci_registered = true;
  3610. if ((rc = mgsl_init_tty()) < 0)
  3611. goto error;
  3612. return 0;
  3613. error:
  3614. synclink_cleanup();
  3615. return rc;
  3616. }
  3617. static void __exit synclink_exit(void)
  3618. {
  3619. synclink_cleanup();
  3620. }
  3621. module_init(synclink_init);
  3622. module_exit(synclink_exit);
  3623. /*
  3624. * usc_RTCmd()
  3625. *
  3626. * Issue a USC Receive/Transmit command to the
  3627. * Channel Command/Address Register (CCAR).
  3628. *
  3629. * Notes:
  3630. *
  3631. * The command is encoded in the most significant 5 bits <15..11>
  3632. * of the CCAR value. Bits <10..7> of the CCAR must be preserved
  3633. * and Bits <6..0> must be written as zeros.
  3634. *
  3635. * Arguments:
  3636. *
  3637. * info pointer to device information structure
  3638. * Cmd command mask (use symbolic macros)
  3639. *
  3640. * Return Value:
  3641. *
  3642. * None
  3643. */
  3644. static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd )
  3645. {
  3646. /* output command to CCAR in bits <15..11> */
  3647. /* preserve bits <10..7>, bits <6..0> must be zero */
  3648. outw( Cmd + info->loopback_bits, info->io_base + CCAR );
  3649. /* Read to flush write to CCAR */
  3650. inw( info->io_base + CCAR );
  3651. } /* end of usc_RTCmd() */
  3652. /*
  3653. * usc_DmaCmd()
  3654. *
  3655. * Issue a DMA command to the DMA Command/Address Register (DCAR).
  3656. *
  3657. * Arguments:
  3658. *
  3659. * info pointer to device information structure
  3660. * Cmd DMA command mask (usc_DmaCmd_XX Macros)
  3661. *
  3662. * Return Value:
  3663. *
  3664. * None
  3665. */
  3666. static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd )
  3667. {
  3668. /* write command mask to DCAR */
  3669. outw( Cmd + info->mbre_bit, info->io_base );
  3670. /* Read to flush write to DCAR */
  3671. inw( info->io_base );
  3672. } /* end of usc_DmaCmd() */
  3673. /*
  3674. * usc_OutDmaReg()
  3675. *
  3676. * Write a 16-bit value to a USC DMA register
  3677. *
  3678. * Arguments:
  3679. *
  3680. * info pointer to device info structure
  3681. * RegAddr register address (number) for write
  3682. * RegValue 16-bit value to write to register
  3683. *
  3684. * Return Value:
  3685. *
  3686. * None
  3687. *
  3688. */
  3689. static void usc_OutDmaReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
  3690. {
  3691. /* Note: The DCAR is located at the adapter base address */
  3692. /* Note: must preserve state of BIT8 in DCAR */
  3693. outw( RegAddr + info->mbre_bit, info->io_base );
  3694. outw( RegValue, info->io_base );
  3695. /* Read to flush write to DCAR */
  3696. inw( info->io_base );
  3697. } /* end of usc_OutDmaReg() */
  3698. /*
  3699. * usc_InDmaReg()
  3700. *
  3701. * Read a 16-bit value from a DMA register
  3702. *
  3703. * Arguments:
  3704. *
  3705. * info pointer to device info structure
  3706. * RegAddr register address (number) to read from
  3707. *
  3708. * Return Value:
  3709. *
  3710. * The 16-bit value read from register
  3711. *
  3712. */
  3713. static u16 usc_InDmaReg( struct mgsl_struct *info, u16 RegAddr )
  3714. {
  3715. /* Note: The DCAR is located at the adapter base address */
  3716. /* Note: must preserve state of BIT8 in DCAR */
  3717. outw( RegAddr + info->mbre_bit, info->io_base );
  3718. return inw( info->io_base );
  3719. } /* end of usc_InDmaReg() */
  3720. /*
  3721. *
  3722. * usc_OutReg()
  3723. *
  3724. * Write a 16-bit value to a USC serial channel register
  3725. *
  3726. * Arguments:
  3727. *
  3728. * info pointer to device info structure
  3729. * RegAddr register address (number) to write to
  3730. * RegValue 16-bit value to write to register
  3731. *
  3732. * Return Value:
  3733. *
  3734. * None
  3735. *
  3736. */
  3737. static void usc_OutReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
  3738. {
  3739. outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
  3740. outw( RegValue, info->io_base + CCAR );
  3741. /* Read to flush write to CCAR */
  3742. inw( info->io_base + CCAR );
  3743. } /* end of usc_OutReg() */
  3744. /*
  3745. * usc_InReg()
  3746. *
  3747. * Reads a 16-bit value from a USC serial channel register
  3748. *
  3749. * Arguments:
  3750. *
  3751. * info pointer to device extension
  3752. * RegAddr register address (number) to read from
  3753. *
  3754. * Return Value:
  3755. *
  3756. * 16-bit value read from register
  3757. */
  3758. static u16 usc_InReg( struct mgsl_struct *info, u16 RegAddr )
  3759. {
  3760. outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
  3761. return inw( info->io_base + CCAR );
  3762. } /* end of usc_InReg() */
  3763. /* usc_set_sdlc_mode()
  3764. *
  3765. * Set up the adapter for SDLC DMA communications.
  3766. *
  3767. * Arguments: info pointer to device instance data
  3768. * Return Value: NONE
  3769. */
  3770. static void usc_set_sdlc_mode( struct mgsl_struct *info )
  3771. {
  3772. u16 RegValue;
  3773. bool PreSL1660;
  3774. /*
  3775. * determine if the IUSC on the adapter is pre-SL1660. If
  3776. * not, take advantage of the UnderWait feature of more
  3777. * modern chips. If an underrun occurs and this bit is set,
  3778. * the transmitter will idle the programmed idle pattern
  3779. * until the driver has time to service the underrun. Otherwise,
  3780. * the dma controller may get the cycles previously requested
  3781. * and begin transmitting queued tx data.
  3782. */
  3783. usc_OutReg(info,TMCR,0x1f);
  3784. RegValue=usc_InReg(info,TMDR);
  3785. PreSL1660 = (RegValue == IUSC_PRE_SL1660);
  3786. if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
  3787. {
  3788. /*
  3789. ** Channel Mode Register (CMR)
  3790. **
  3791. ** <15..14> 10 Tx Sub Modes, Send Flag on Underrun
  3792. ** <13> 0 0 = Transmit Disabled (initially)
  3793. ** <12> 0 1 = Consecutive Idles share common 0
  3794. ** <11..8> 1110 Transmitter Mode = HDLC/SDLC Loop
  3795. ** <7..4> 0000 Rx Sub Modes, addr/ctrl field handling
  3796. ** <3..0> 0110 Receiver Mode = HDLC/SDLC
  3797. **
  3798. ** 1000 1110 0000 0110 = 0x8e06
  3799. */
  3800. RegValue = 0x8e06;
  3801. /*--------------------------------------------------
  3802. * ignore user options for UnderRun Actions and
  3803. * preambles
  3804. *--------------------------------------------------*/
  3805. }
  3806. else
  3807. {
  3808. /* Channel mode Register (CMR)
  3809. *
  3810. * <15..14> 00 Tx Sub modes, Underrun Action
  3811. * <13> 0 1 = Send Preamble before opening flag
  3812. * <12> 0 1 = Consecutive Idles share common 0
  3813. * <11..8> 0110 Transmitter mode = HDLC/SDLC
  3814. * <7..4> 0000 Rx Sub modes, addr/ctrl field handling
  3815. * <3..0> 0110 Receiver mode = HDLC/SDLC
  3816. *
  3817. * 0000 0110 0000 0110 = 0x0606
  3818. */
  3819. if (info->params.mode == MGSL_MODE_RAW) {
  3820. RegValue = 0x0001; /* Set Receive mode = external sync */
  3821. usc_OutReg( info, IOCR, /* Set IOCR DCD is RxSync Detect Input */
  3822. (unsigned short)((usc_InReg(info, IOCR) & ~(BIT13|BIT12)) | BIT12));
  3823. /*
  3824. * TxSubMode:
  3825. * CMR <15> 0 Don't send CRC on Tx Underrun
  3826. * CMR <14> x undefined
  3827. * CMR <13> 0 Send preamble before openning sync
  3828. * CMR <12> 0 Send 8-bit syncs, 1=send Syncs per TxLength
  3829. *
  3830. * TxMode:
  3831. * CMR <11-8) 0100 MonoSync
  3832. *
  3833. * 0x00 0100 xxxx xxxx 04xx
  3834. */
  3835. RegValue |= 0x0400;
  3836. }
  3837. else {
  3838. RegValue = 0x0606;
  3839. if ( info->params.flags & HDLC_FLAG_UNDERRUN_ABORT15 )
  3840. RegValue |= BIT14;
  3841. else if ( info->params.flags & HDLC_FLAG_UNDERRUN_FLAG )
  3842. RegValue |= BIT15;
  3843. else if ( info->params.flags & HDLC_FLAG_UNDERRUN_CRC )
  3844. RegValue |= BIT15 | BIT14;
  3845. }
  3846. if ( info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE )
  3847. RegValue |= BIT13;
  3848. }
  3849. if ( info->params.mode == MGSL_MODE_HDLC &&
  3850. (info->params.flags & HDLC_FLAG_SHARE_ZERO) )
  3851. RegValue |= BIT12;
  3852. if ( info->params.addr_filter != 0xff )
  3853. {
  3854. /* set up receive address filtering */
  3855. usc_OutReg( info, RSR, info->params.addr_filter );
  3856. RegValue |= BIT4;
  3857. }
  3858. usc_OutReg( info, CMR, RegValue );
  3859. info->cmr_value = RegValue;
  3860. /* Receiver mode Register (RMR)
  3861. *
  3862. * <15..13> 000 encoding
  3863. * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
  3864. * <10> 1 1 = Set CRC to all 1s (use for SDLC/HDLC)
  3865. * <9> 0 1 = Include Receive chars in CRC
  3866. * <8> 1 1 = Use Abort/PE bit as abort indicator
  3867. * <7..6> 00 Even parity
  3868. * <5> 0 parity disabled
  3869. * <4..2> 000 Receive Char Length = 8 bits
  3870. * <1..0> 00 Disable Receiver
  3871. *
  3872. * 0000 0101 0000 0000 = 0x0500
  3873. */
  3874. RegValue = 0x0500;
  3875. switch ( info->params.encoding ) {
  3876. case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
  3877. case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
  3878. case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 | BIT13; break;
  3879. case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
  3880. case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 | BIT13; break;
  3881. case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14; break;
  3882. case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14 | BIT13; break;
  3883. }
  3884. if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
  3885. RegValue |= BIT9;
  3886. else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
  3887. RegValue |= ( BIT12 | BIT10 | BIT9 );
  3888. usc_OutReg( info, RMR, RegValue );
  3889. /* Set the Receive count Limit Register (RCLR) to 0xffff. */
  3890. /* When an opening flag of an SDLC frame is recognized the */
  3891. /* Receive Character count (RCC) is loaded with the value in */
  3892. /* RCLR. The RCC is decremented for each received byte. The */
  3893. /* value of RCC is stored after the closing flag of the frame */
  3894. /* allowing the frame size to be computed. */
  3895. usc_OutReg( info, RCLR, RCLRVALUE );
  3896. usc_RCmd( info, RCmd_SelectRicrdma_level );
  3897. /* Receive Interrupt Control Register (RICR)
  3898. *
  3899. * <15..8> ? RxFIFO DMA Request Level
  3900. * <7> 0 Exited Hunt IA (Interrupt Arm)
  3901. * <6> 0 Idle Received IA
  3902. * <5> 0 Break/Abort IA
  3903. * <4> 0 Rx Bound IA
  3904. * <3> 1 Queued status reflects oldest 2 bytes in FIFO
  3905. * <2> 0 Abort/PE IA
  3906. * <1> 1 Rx Overrun IA
  3907. * <0> 0 Select TC0 value for readback
  3908. *
  3909. * 0000 0000 0000 1000 = 0x000a
  3910. */
  3911. /* Carry over the Exit Hunt and Idle Received bits */
  3912. /* in case they have been armed by usc_ArmEvents. */
  3913. RegValue = usc_InReg( info, RICR ) & 0xc0;
  3914. usc_OutReg( info, RICR, (u16)(0x030a | RegValue) );
  3915. /* Unlatch all Rx status bits and clear Rx status IRQ Pending */
  3916. usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
  3917. usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
  3918. /* Transmit mode Register (TMR)
  3919. *
  3920. * <15..13> 000 encoding
  3921. * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
  3922. * <10> 1 1 = Start CRC as all 1s (use for SDLC/HDLC)
  3923. * <9> 0 1 = Tx CRC Enabled
  3924. * <8> 0 1 = Append CRC to end of transmit frame
  3925. * <7..6> 00 Transmit parity Even
  3926. * <5> 0 Transmit parity Disabled
  3927. * <4..2> 000 Tx Char Length = 8 bits
  3928. * <1..0> 00 Disable Transmitter
  3929. *
  3930. * 0000 0100 0000 0000 = 0x0400
  3931. */
  3932. RegValue = 0x0400;
  3933. switch ( info->params.encoding ) {
  3934. case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
  3935. case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
  3936. case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 | BIT13; break;
  3937. case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
  3938. case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 | BIT13; break;
  3939. case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14; break;
  3940. case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14 | BIT13; break;
  3941. }
  3942. if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
  3943. RegValue |= BIT9 | BIT8;
  3944. else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
  3945. RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8);
  3946. usc_OutReg( info, TMR, RegValue );
  3947. usc_set_txidle( info );
  3948. usc_TCmd( info, TCmd_SelectTicrdma_level );
  3949. /* Transmit Interrupt Control Register (TICR)
  3950. *
  3951. * <15..8> ? Transmit FIFO DMA Level
  3952. * <7> 0 Present IA (Interrupt Arm)
  3953. * <6> 0 Idle Sent IA
  3954. * <5> 1 Abort Sent IA
  3955. * <4> 1 EOF/EOM Sent IA
  3956. * <3> 0 CRC Sent IA
  3957. * <2> 1 1 = Wait for SW Trigger to Start Frame
  3958. * <1> 1 Tx Underrun IA
  3959. * <0> 0 TC0 constant on read back
  3960. *
  3961. * 0000 0000 0011 0110 = 0x0036
  3962. */
  3963. usc_OutReg( info, TICR, 0x0736 );
  3964. usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
  3965. usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
  3966. /*
  3967. ** Transmit Command/Status Register (TCSR)
  3968. **
  3969. ** <15..12> 0000 TCmd
  3970. ** <11> 0/1 UnderWait
  3971. ** <10..08> 000 TxIdle
  3972. ** <7> x PreSent
  3973. ** <6> x IdleSent
  3974. ** <5> x AbortSent
  3975. ** <4> x EOF/EOM Sent
  3976. ** <3> x CRC Sent
  3977. ** <2> x All Sent
  3978. ** <1> x TxUnder
  3979. ** <0> x TxEmpty
  3980. **
  3981. ** 0000 0000 0000 0000 = 0x0000
  3982. */
  3983. info->tcsr_value = 0;
  3984. if ( !PreSL1660 )
  3985. info->tcsr_value |= TCSR_UNDERWAIT;
  3986. usc_OutReg( info, TCSR, info->tcsr_value );
  3987. /* Clock mode Control Register (CMCR)
  3988. *
  3989. * <15..14> 00 counter 1 Source = Disabled
  3990. * <13..12> 00 counter 0 Source = Disabled
  3991. * <11..10> 11 BRG1 Input is TxC Pin
  3992. * <9..8> 11 BRG0 Input is TxC Pin
  3993. * <7..6> 01 DPLL Input is BRG1 Output
  3994. * <5..3> XXX TxCLK comes from Port 0
  3995. * <2..0> XXX RxCLK comes from Port 1
  3996. *
  3997. * 0000 1111 0111 0111 = 0x0f77
  3998. */
  3999. RegValue = 0x0f40;
  4000. if ( info->params.flags & HDLC_FLAG_RXC_DPLL )
  4001. RegValue |= 0x0003; /* RxCLK from DPLL */
  4002. else if ( info->params.flags & HDLC_FLAG_RXC_BRG )
  4003. RegValue |= 0x0004; /* RxCLK from BRG0 */
  4004. else if ( info->params.flags & HDLC_FLAG_RXC_TXCPIN)
  4005. RegValue |= 0x0006; /* RxCLK from TXC Input */
  4006. else
  4007. RegValue |= 0x0007; /* RxCLK from Port1 */
  4008. if ( info->params.flags & HDLC_FLAG_TXC_DPLL )
  4009. RegValue |= 0x0018; /* TxCLK from DPLL */
  4010. else if ( info->params.flags & HDLC_FLAG_TXC_BRG )
  4011. RegValue |= 0x0020; /* TxCLK from BRG0 */
  4012. else if ( info->params.flags & HDLC_FLAG_TXC_RXCPIN)
  4013. RegValue |= 0x0038; /* RxCLK from TXC Input */
  4014. else
  4015. RegValue |= 0x0030; /* TxCLK from Port0 */
  4016. usc_OutReg( info, CMCR, RegValue );
  4017. /* Hardware Configuration Register (HCR)
  4018. *
  4019. * <15..14> 00 CTR0 Divisor:00=32,01=16,10=8,11=4
  4020. * <13> 0 CTR1DSel:0=CTR0Div determines CTR0Div
  4021. * <12> 0 CVOK:0=report code violation in biphase
  4022. * <11..10> 00 DPLL Divisor:00=32,01=16,10=8,11=4
  4023. * <9..8> XX DPLL mode:00=disable,01=NRZ,10=Biphase,11=Biphase Level
  4024. * <7..6> 00 reserved
  4025. * <5> 0 BRG1 mode:0=continuous,1=single cycle
  4026. * <4> X BRG1 Enable
  4027. * <3..2> 00 reserved
  4028. * <1> 0 BRG0 mode:0=continuous,1=single cycle
  4029. * <0> 0 BRG0 Enable
  4030. */
  4031. RegValue = 0x0000;
  4032. if ( info->params.flags & (HDLC_FLAG_RXC_DPLL | HDLC_FLAG_TXC_DPLL) ) {
  4033. u32 XtalSpeed;
  4034. u32 DpllDivisor;
  4035. u16 Tc;
  4036. /* DPLL is enabled. Use BRG1 to provide continuous reference clock */
  4037. /* for DPLL. DPLL mode in HCR is dependent on the encoding used. */
  4038. XtalSpeed = 11059200;
  4039. if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
  4040. DpllDivisor = 16;
  4041. RegValue |= BIT10;
  4042. }
  4043. else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
  4044. DpllDivisor = 8;
  4045. RegValue |= BIT11;
  4046. }
  4047. else
  4048. DpllDivisor = 32;
  4049. /* Tc = (Xtal/Speed) - 1 */
  4050. /* If twice the remainder of (Xtal/Speed) is greater than Speed */
  4051. /* then rounding up gives a more precise time constant. Instead */
  4052. /* of rounding up and then subtracting 1 we just don't subtract */
  4053. /* the one in this case. */
  4054. /*--------------------------------------------------
  4055. * ejz: for DPLL mode, application should use the
  4056. * same clock speed as the partner system, even
  4057. * though clocking is derived from the input RxData.
  4058. * In case the user uses a 0 for the clock speed,
  4059. * default to 0xffffffff and don't try to divide by
  4060. * zero
  4061. *--------------------------------------------------*/
  4062. if ( info->params.clock_speed )
  4063. {
  4064. Tc = (u16)((XtalSpeed/DpllDivisor)/info->params.clock_speed);
  4065. if ( !((((XtalSpeed/DpllDivisor) % info->params.clock_speed) * 2)
  4066. / info->params.clock_speed) )
  4067. Tc--;
  4068. }
  4069. else
  4070. Tc = -1;
  4071. /* Write 16-bit Time Constant for BRG1 */
  4072. usc_OutReg( info, TC1R, Tc );
  4073. RegValue |= BIT4; /* enable BRG1 */
  4074. switch ( info->params.encoding ) {
  4075. case HDLC_ENCODING_NRZ:
  4076. case HDLC_ENCODING_NRZB:
  4077. case HDLC_ENCODING_NRZI_MARK:
  4078. case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT8; break;
  4079. case HDLC_ENCODING_BIPHASE_MARK:
  4080. case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT9; break;
  4081. case HDLC_ENCODING_BIPHASE_LEVEL:
  4082. case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 | BIT8; break;
  4083. }
  4084. }
  4085. usc_OutReg( info, HCR, RegValue );
  4086. /* Channel Control/status Register (CCSR)
  4087. *
  4088. * <15> X RCC FIFO Overflow status (RO)
  4089. * <14> X RCC FIFO Not Empty status (RO)
  4090. * <13> 0 1 = Clear RCC FIFO (WO)
  4091. * <12> X DPLL Sync (RW)
  4092. * <11> X DPLL 2 Missed Clocks status (RO)
  4093. * <10> X DPLL 1 Missed Clock status (RO)
  4094. * <9..8> 00 DPLL Resync on rising and falling edges (RW)
  4095. * <7> X SDLC Loop On status (RO)
  4096. * <6> X SDLC Loop Send status (RO)
  4097. * <5> 1 Bypass counters for TxClk and RxClk (RW)
  4098. * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
  4099. * <1..0> 00 reserved
  4100. *
  4101. * 0000 0000 0010 0000 = 0x0020
  4102. */
  4103. usc_OutReg( info, CCSR, 0x1020 );
  4104. if ( info->params.flags & HDLC_FLAG_AUTO_CTS ) {
  4105. usc_OutReg( info, SICR,
  4106. (u16)(usc_InReg(info,SICR) | SICR_CTS_INACTIVE) );
  4107. }
  4108. /* enable Master Interrupt Enable bit (MIE) */
  4109. usc_EnableMasterIrqBit( info );
  4110. usc_ClearIrqPendingBits( info, RECEIVE_STATUS | RECEIVE_DATA |
  4111. TRANSMIT_STATUS | TRANSMIT_DATA | MISC);
  4112. /* arm RCC underflow interrupt */
  4113. usc_OutReg(info, SICR, (u16)(usc_InReg(info,SICR) | BIT3));
  4114. usc_EnableInterrupts(info, MISC);
  4115. info->mbre_bit = 0;
  4116. outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
  4117. usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */
  4118. info->mbre_bit = BIT8;
  4119. outw( BIT8, info->io_base ); /* set Master Bus Enable (DCAR) */
  4120. /* DMA Control Register (DCR)
  4121. *
  4122. * <15..14> 10 Priority mode = Alternating Tx/Rx
  4123. * 01 Rx has priority
  4124. * 00 Tx has priority
  4125. *
  4126. * <13> 1 Enable Priority Preempt per DCR<15..14>
  4127. * (WARNING DCR<11..10> must be 00 when this is 1)
  4128. * 0 Choose activate channel per DCR<11..10>
  4129. *
  4130. * <12> 0 Little Endian for Array/List
  4131. * <11..10> 00 Both Channels can use each bus grant
  4132. * <9..6> 0000 reserved
  4133. * <5> 0 7 CLK - Minimum Bus Re-request Interval
  4134. * <4> 0 1 = drive D/C and S/D pins
  4135. * <3> 1 1 = Add one wait state to all DMA cycles.
  4136. * <2> 0 1 = Strobe /UAS on every transfer.
  4137. * <1..0> 11 Addr incrementing only affects LS24 bits
  4138. *
  4139. * 0110 0000 0000 1011 = 0x600b
  4140. */
  4141. /* PCI adapter does not need DMA wait state */
  4142. usc_OutDmaReg( info, DCR, 0xa00b );
  4143. /* Receive DMA mode Register (RDMR)
  4144. *
  4145. * <15..14> 11 DMA mode = Linked List Buffer mode
  4146. * <13> 1 RSBinA/L = store Rx status Block in Arrary/List entry
  4147. * <12> 1 Clear count of List Entry after fetching
  4148. * <11..10> 00 Address mode = Increment
  4149. * <9> 1 Terminate Buffer on RxBound
  4150. * <8> 0 Bus Width = 16bits
  4151. * <7..0> ? status Bits (write as 0s)
  4152. *
  4153. * 1111 0010 0000 0000 = 0xf200
  4154. */
  4155. usc_OutDmaReg( info, RDMR, 0xf200 );
  4156. /* Transmit DMA mode Register (TDMR)
  4157. *
  4158. * <15..14> 11 DMA mode = Linked List Buffer mode
  4159. * <13> 1 TCBinA/L = fetch Tx Control Block from List entry
  4160. * <12> 1 Clear count of List Entry after fetching
  4161. * <11..10> 00 Address mode = Increment
  4162. * <9> 1 Terminate Buffer on end of frame
  4163. * <8> 0 Bus Width = 16bits
  4164. * <7..0> ? status Bits (Read Only so write as 0)
  4165. *
  4166. * 1111 0010 0000 0000 = 0xf200
  4167. */
  4168. usc_OutDmaReg( info, TDMR, 0xf200 );
  4169. /* DMA Interrupt Control Register (DICR)
  4170. *
  4171. * <15> 1 DMA Interrupt Enable
  4172. * <14> 0 1 = Disable IEO from USC
  4173. * <13> 0 1 = Don't provide vector during IntAck
  4174. * <12> 1 1 = Include status in Vector
  4175. * <10..2> 0 reserved, Must be 0s
  4176. * <1> 0 1 = Rx DMA Interrupt Enabled
  4177. * <0> 0 1 = Tx DMA Interrupt Enabled
  4178. *
  4179. * 1001 0000 0000 0000 = 0x9000
  4180. */
  4181. usc_OutDmaReg( info, DICR, 0x9000 );
  4182. usc_InDmaReg( info, RDMR ); /* clear pending receive DMA IRQ bits */
  4183. usc_InDmaReg( info, TDMR ); /* clear pending transmit DMA IRQ bits */
  4184. usc_OutDmaReg( info, CDIR, 0x0303 ); /* clear IUS and Pending for Tx and Rx */
  4185. /* Channel Control Register (CCR)
  4186. *
  4187. * <15..14> 10 Use 32-bit Tx Control Blocks (TCBs)
  4188. * <13> 0 Trigger Tx on SW Command Disabled
  4189. * <12> 0 Flag Preamble Disabled
  4190. * <11..10> 00 Preamble Length
  4191. * <9..8> 00 Preamble Pattern
  4192. * <7..6> 10 Use 32-bit Rx status Blocks (RSBs)
  4193. * <5> 0 Trigger Rx on SW Command Disabled
  4194. * <4..0> 0 reserved
  4195. *
  4196. * 1000 0000 1000 0000 = 0x8080
  4197. */
  4198. RegValue = 0x8080;
  4199. switch ( info->params.preamble_length ) {
  4200. case HDLC_PREAMBLE_LENGTH_16BITS: RegValue |= BIT10; break;
  4201. case HDLC_PREAMBLE_LENGTH_32BITS: RegValue |= BIT11; break;
  4202. case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 | BIT10; break;
  4203. }
  4204. switch ( info->params.preamble ) {
  4205. case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 | BIT12; break;
  4206. case HDLC_PREAMBLE_PATTERN_ONES: RegValue |= BIT8; break;
  4207. case HDLC_PREAMBLE_PATTERN_10: RegValue |= BIT9; break;
  4208. case HDLC_PREAMBLE_PATTERN_01: RegValue |= BIT9 | BIT8; break;
  4209. }
  4210. usc_OutReg( info, CCR, RegValue );
  4211. /*
  4212. * Burst/Dwell Control Register
  4213. *
  4214. * <15..8> 0x20 Maximum number of transfers per bus grant
  4215. * <7..0> 0x00 Maximum number of clock cycles per bus grant
  4216. */
  4217. /* don't limit bus occupancy on PCI adapter */
  4218. usc_OutDmaReg( info, BDCR, 0x0000 );
  4219. usc_stop_transmitter(info);
  4220. usc_stop_receiver(info);
  4221. } /* end of usc_set_sdlc_mode() */
  4222. /* usc_enable_loopback()
  4223. *
  4224. * Set the 16C32 for internal loopback mode.
  4225. * The TxCLK and RxCLK signals are generated from the BRG0 and
  4226. * the TxD is looped back to the RxD internally.
  4227. *
  4228. * Arguments: info pointer to device instance data
  4229. * enable 1 = enable loopback, 0 = disable
  4230. * Return Value: None
  4231. */
  4232. static void usc_enable_loopback(struct mgsl_struct *info, int enable)
  4233. {
  4234. if (enable) {
  4235. /* blank external TXD output */
  4236. usc_OutReg(info,IOCR,usc_InReg(info,IOCR) | (BIT7 | BIT6));
  4237. /* Clock mode Control Register (CMCR)
  4238. *
  4239. * <15..14> 00 counter 1 Disabled
  4240. * <13..12> 00 counter 0 Disabled
  4241. * <11..10> 11 BRG1 Input is TxC Pin
  4242. * <9..8> 11 BRG0 Input is TxC Pin
  4243. * <7..6> 01 DPLL Input is BRG1 Output
  4244. * <5..3> 100 TxCLK comes from BRG0
  4245. * <2..0> 100 RxCLK comes from BRG0
  4246. *
  4247. * 0000 1111 0110 0100 = 0x0f64
  4248. */
  4249. usc_OutReg( info, CMCR, 0x0f64 );
  4250. /* Write 16-bit Time Constant for BRG0 */
  4251. /* use clock speed if available, otherwise use 8 for diagnostics */
  4252. if (info->params.clock_speed) {
  4253. usc_OutReg(info, TC0R, (u16)((11059200/info->params.clock_speed)-1));
  4254. } else
  4255. usc_OutReg(info, TC0R, (u16)8);
  4256. /* Hardware Configuration Register (HCR) Clear Bit 1, BRG0
  4257. mode = Continuous Set Bit 0 to enable BRG0. */
  4258. usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
  4259. /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
  4260. usc_OutReg(info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004));
  4261. /* set Internal Data loopback mode */
  4262. info->loopback_bits = 0x300;
  4263. outw( 0x0300, info->io_base + CCAR );
  4264. } else {
  4265. /* enable external TXD output */
  4266. usc_OutReg(info,IOCR,usc_InReg(info,IOCR) & ~(BIT7 | BIT6));
  4267. /* clear Internal Data loopback mode */
  4268. info->loopback_bits = 0;
  4269. outw( 0,info->io_base + CCAR );
  4270. }
  4271. } /* end of usc_enable_loopback() */
  4272. /* usc_enable_aux_clock()
  4273. *
  4274. * Enabled the AUX clock output at the specified frequency.
  4275. *
  4276. * Arguments:
  4277. *
  4278. * info pointer to device extension
  4279. * data_rate data rate of clock in bits per second
  4280. * A data rate of 0 disables the AUX clock.
  4281. *
  4282. * Return Value: None
  4283. */
  4284. static void usc_enable_aux_clock( struct mgsl_struct *info, u32 data_rate )
  4285. {
  4286. u32 XtalSpeed;
  4287. u16 Tc;
  4288. if ( data_rate ) {
  4289. XtalSpeed = 11059200;
  4290. /* Tc = (Xtal/Speed) - 1 */
  4291. /* If twice the remainder of (Xtal/Speed) is greater than Speed */
  4292. /* then rounding up gives a more precise time constant. Instead */
  4293. /* of rounding up and then subtracting 1 we just don't subtract */
  4294. /* the one in this case. */
  4295. Tc = (u16)(XtalSpeed/data_rate);
  4296. if ( !(((XtalSpeed % data_rate) * 2) / data_rate) )
  4297. Tc--;
  4298. /* Write 16-bit Time Constant for BRG0 */
  4299. usc_OutReg( info, TC0R, Tc );
  4300. /*
  4301. * Hardware Configuration Register (HCR)
  4302. * Clear Bit 1, BRG0 mode = Continuous
  4303. * Set Bit 0 to enable BRG0.
  4304. */
  4305. usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
  4306. /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
  4307. usc_OutReg( info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
  4308. } else {
  4309. /* data rate == 0 so turn off BRG0 */
  4310. usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
  4311. }
  4312. } /* end of usc_enable_aux_clock() */
  4313. /*
  4314. *
  4315. * usc_process_rxoverrun_sync()
  4316. *
  4317. * This function processes a receive overrun by resetting the
  4318. * receive DMA buffers and issuing a Purge Rx FIFO command
  4319. * to allow the receiver to continue receiving.
  4320. *
  4321. * Arguments:
  4322. *
  4323. * info pointer to device extension
  4324. *
  4325. * Return Value: None
  4326. */
  4327. static void usc_process_rxoverrun_sync( struct mgsl_struct *info )
  4328. {
  4329. int start_index;
  4330. int end_index;
  4331. int frame_start_index;
  4332. bool start_of_frame_found = false;
  4333. bool end_of_frame_found = false;
  4334. bool reprogram_dma = false;
  4335. DMABUFFERENTRY *buffer_list = info->rx_buffer_list;
  4336. u32 phys_addr;
  4337. usc_DmaCmd( info, DmaCmd_PauseRxChannel );
  4338. usc_RCmd( info, RCmd_EnterHuntmode );
  4339. usc_RTCmd( info, RTCmd_PurgeRxFifo );
  4340. /* CurrentRxBuffer points to the 1st buffer of the next */
  4341. /* possibly available receive frame. */
  4342. frame_start_index = start_index = end_index = info->current_rx_buffer;
  4343. /* Search for an unfinished string of buffers. This means */
  4344. /* that a receive frame started (at least one buffer with */
  4345. /* count set to zero) but there is no terminiting buffer */
  4346. /* (status set to non-zero). */
  4347. while( !buffer_list[end_index].count )
  4348. {
  4349. /* Count field has been reset to zero by 16C32. */
  4350. /* This buffer is currently in use. */
  4351. if ( !start_of_frame_found )
  4352. {
  4353. start_of_frame_found = true;
  4354. frame_start_index = end_index;
  4355. end_of_frame_found = false;
  4356. }
  4357. if ( buffer_list[end_index].status )
  4358. {
  4359. /* Status field has been set by 16C32. */
  4360. /* This is the last buffer of a received frame. */
  4361. /* We want to leave the buffers for this frame intact. */
  4362. /* Move on to next possible frame. */
  4363. start_of_frame_found = false;
  4364. end_of_frame_found = true;
  4365. }
  4366. /* advance to next buffer entry in linked list */
  4367. end_index++;
  4368. if ( end_index == info->rx_buffer_count )
  4369. end_index = 0;
  4370. if ( start_index == end_index )
  4371. {
  4372. /* The entire list has been searched with all Counts == 0 and */
  4373. /* all Status == 0. The receive buffers are */
  4374. /* completely screwed, reset all receive buffers! */
  4375. mgsl_reset_rx_dma_buffers( info );
  4376. frame_start_index = 0;
  4377. start_of_frame_found = false;
  4378. reprogram_dma = true;
  4379. break;
  4380. }
  4381. }
  4382. if ( start_of_frame_found && !end_of_frame_found )
  4383. {
  4384. /* There is an unfinished string of receive DMA buffers */
  4385. /* as a result of the receiver overrun. */
  4386. /* Reset the buffers for the unfinished frame */
  4387. /* and reprogram the receive DMA controller to start */
  4388. /* at the 1st buffer of unfinished frame. */
  4389. start_index = frame_start_index;
  4390. do
  4391. {
  4392. *((unsigned long *)&(info->rx_buffer_list[start_index++].count)) = DMABUFFERSIZE;
  4393. /* Adjust index for wrap around. */
  4394. if ( start_index == info->rx_buffer_count )
  4395. start_index = 0;
  4396. } while( start_index != end_index );
  4397. reprogram_dma = true;
  4398. }
  4399. if ( reprogram_dma )
  4400. {
  4401. usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
  4402. usc_ClearIrqPendingBits(info, RECEIVE_DATA|RECEIVE_STATUS);
  4403. usc_UnlatchRxstatusBits(info, RECEIVE_DATA|RECEIVE_STATUS);
  4404. usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
  4405. /* This empties the receive FIFO and loads the RCC with RCLR */
  4406. usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
  4407. /* program 16C32 with physical address of 1st DMA buffer entry */
  4408. phys_addr = info->rx_buffer_list[frame_start_index].phys_entry;
  4409. usc_OutDmaReg( info, NRARL, (u16)phys_addr );
  4410. usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
  4411. usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
  4412. usc_ClearIrqPendingBits( info, RECEIVE_DATA | RECEIVE_STATUS );
  4413. usc_EnableInterrupts( info, RECEIVE_STATUS );
  4414. /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
  4415. /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
  4416. usc_OutDmaReg( info, RDIAR, BIT3 | BIT2 );
  4417. usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
  4418. usc_DmaCmd( info, DmaCmd_InitRxChannel );
  4419. if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
  4420. usc_EnableReceiver(info,ENABLE_AUTO_DCD);
  4421. else
  4422. usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
  4423. }
  4424. else
  4425. {
  4426. /* This empties the receive FIFO and loads the RCC with RCLR */
  4427. usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
  4428. usc_RTCmd( info, RTCmd_PurgeRxFifo );
  4429. }
  4430. } /* end of usc_process_rxoverrun_sync() */
  4431. /* usc_stop_receiver()
  4432. *
  4433. * Disable USC receiver
  4434. *
  4435. * Arguments: info pointer to device instance data
  4436. * Return Value: None
  4437. */
  4438. static void usc_stop_receiver( struct mgsl_struct *info )
  4439. {
  4440. if (debug_level >= DEBUG_LEVEL_ISR)
  4441. printk("%s(%d):usc_stop_receiver(%s)\n",
  4442. __FILE__,__LINE__, info->device_name );
  4443. /* Disable receive DMA channel. */
  4444. /* This also disables receive DMA channel interrupts */
  4445. usc_DmaCmd( info, DmaCmd_ResetRxChannel );
  4446. usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
  4447. usc_ClearIrqPendingBits( info, RECEIVE_DATA | RECEIVE_STATUS );
  4448. usc_DisableInterrupts( info, RECEIVE_DATA | RECEIVE_STATUS );
  4449. usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
  4450. /* This empties the receive FIFO and loads the RCC with RCLR */
  4451. usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
  4452. usc_RTCmd( info, RTCmd_PurgeRxFifo );
  4453. info->rx_enabled = false;
  4454. info->rx_overflow = false;
  4455. info->rx_rcc_underrun = false;
  4456. } /* end of stop_receiver() */
  4457. /* usc_start_receiver()
  4458. *
  4459. * Enable the USC receiver
  4460. *
  4461. * Arguments: info pointer to device instance data
  4462. * Return Value: None
  4463. */
  4464. static void usc_start_receiver( struct mgsl_struct *info )
  4465. {
  4466. u32 phys_addr;
  4467. if (debug_level >= DEBUG_LEVEL_ISR)
  4468. printk("%s(%d):usc_start_receiver(%s)\n",
  4469. __FILE__,__LINE__, info->device_name );
  4470. mgsl_reset_rx_dma_buffers( info );
  4471. usc_stop_receiver( info );
  4472. usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
  4473. usc_RTCmd( info, RTCmd_PurgeRxFifo );
  4474. if ( info->params.mode == MGSL_MODE_HDLC ||
  4475. info->params.mode == MGSL_MODE_RAW ) {
  4476. /* DMA mode Transfers */
  4477. /* Program the DMA controller. */
  4478. /* Enable the DMA controller end of buffer interrupt. */
  4479. /* program 16C32 with physical address of 1st DMA buffer entry */
  4480. phys_addr = info->rx_buffer_list[0].phys_entry;
  4481. usc_OutDmaReg( info, NRARL, (u16)phys_addr );
  4482. usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
  4483. usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
  4484. usc_ClearIrqPendingBits( info, RECEIVE_DATA | RECEIVE_STATUS );
  4485. usc_EnableInterrupts( info, RECEIVE_STATUS );
  4486. /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
  4487. /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
  4488. usc_OutDmaReg( info, RDIAR, BIT3 | BIT2 );
  4489. usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
  4490. usc_DmaCmd( info, DmaCmd_InitRxChannel );
  4491. if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
  4492. usc_EnableReceiver(info,ENABLE_AUTO_DCD);
  4493. else
  4494. usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
  4495. } else {
  4496. usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
  4497. usc_ClearIrqPendingBits(info, RECEIVE_DATA | RECEIVE_STATUS);
  4498. usc_EnableInterrupts(info, RECEIVE_DATA);
  4499. usc_RTCmd( info, RTCmd_PurgeRxFifo );
  4500. usc_RCmd( info, RCmd_EnterHuntmode );
  4501. usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
  4502. }
  4503. usc_OutReg( info, CCSR, 0x1020 );
  4504. info->rx_enabled = true;
  4505. } /* end of usc_start_receiver() */
  4506. /* usc_start_transmitter()
  4507. *
  4508. * Enable the USC transmitter and send a transmit frame if
  4509. * one is loaded in the DMA buffers.
  4510. *
  4511. * Arguments: info pointer to device instance data
  4512. * Return Value: None
  4513. */
  4514. static void usc_start_transmitter( struct mgsl_struct *info )
  4515. {
  4516. u32 phys_addr;
  4517. unsigned int FrameSize;
  4518. if (debug_level >= DEBUG_LEVEL_ISR)
  4519. printk("%s(%d):usc_start_transmitter(%s)\n",
  4520. __FILE__,__LINE__, info->device_name );
  4521. if ( info->xmit_cnt ) {
  4522. /* If auto RTS enabled and RTS is inactive, then assert */
  4523. /* RTS and set a flag indicating that the driver should */
  4524. /* negate RTS when the transmission completes. */
  4525. info->drop_rts_on_tx_done = false;
  4526. if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
  4527. usc_get_serial_signals( info );
  4528. if ( !(info->serial_signals & SerialSignal_RTS) ) {
  4529. info->serial_signals |= SerialSignal_RTS;
  4530. usc_set_serial_signals( info );
  4531. info->drop_rts_on_tx_done = true;
  4532. }
  4533. }
  4534. if ( info->params.mode == MGSL_MODE_ASYNC ) {
  4535. if ( !info->tx_active ) {
  4536. usc_UnlatchTxstatusBits(info, TXSTATUS_ALL);
  4537. usc_ClearIrqPendingBits(info, TRANSMIT_STATUS + TRANSMIT_DATA);
  4538. usc_EnableInterrupts(info, TRANSMIT_DATA);
  4539. usc_load_txfifo(info);
  4540. }
  4541. } else {
  4542. /* Disable transmit DMA controller while programming. */
  4543. usc_DmaCmd( info, DmaCmd_ResetTxChannel );
  4544. /* Transmit DMA buffer is loaded, so program USC */
  4545. /* to send the frame contained in the buffers. */
  4546. FrameSize = info->tx_buffer_list[info->start_tx_dma_buffer].rcc;
  4547. /* if operating in Raw sync mode, reset the rcc component
  4548. * of the tx dma buffer entry, otherwise, the serial controller
  4549. * will send a closing sync char after this count.
  4550. */
  4551. if ( info->params.mode == MGSL_MODE_RAW )
  4552. info->tx_buffer_list[info->start_tx_dma_buffer].rcc = 0;
  4553. /* Program the Transmit Character Length Register (TCLR) */
  4554. /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
  4555. usc_OutReg( info, TCLR, (u16)FrameSize );
  4556. usc_RTCmd( info, RTCmd_PurgeTxFifo );
  4557. /* Program the address of the 1st DMA Buffer Entry in linked list */
  4558. phys_addr = info->tx_buffer_list[info->start_tx_dma_buffer].phys_entry;
  4559. usc_OutDmaReg( info, NTARL, (u16)phys_addr );
  4560. usc_OutDmaReg( info, NTARU, (u16)(phys_addr >> 16) );
  4561. usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
  4562. usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
  4563. usc_EnableInterrupts( info, TRANSMIT_STATUS );
  4564. if ( info->params.mode == MGSL_MODE_RAW &&
  4565. info->num_tx_dma_buffers > 1 ) {
  4566. /* When running external sync mode, attempt to 'stream' transmit */
  4567. /* by filling tx dma buffers as they become available. To do this */
  4568. /* we need to enable Tx DMA EOB Status interrupts : */
  4569. /* */
  4570. /* 1. Arm End of Buffer (EOB) Transmit DMA Interrupt (BIT2 of TDIAR) */
  4571. /* 2. Enable Transmit DMA Interrupts (BIT0 of DICR) */
  4572. usc_OutDmaReg( info, TDIAR, BIT2|BIT3 );
  4573. usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT0) );
  4574. }
  4575. /* Initialize Transmit DMA Channel */
  4576. usc_DmaCmd( info, DmaCmd_InitTxChannel );
  4577. usc_TCmd( info, TCmd_SendFrame );
  4578. mod_timer(&info->tx_timer, jiffies +
  4579. msecs_to_jiffies(5000));
  4580. }
  4581. info->tx_active = true;
  4582. }
  4583. if ( !info->tx_enabled ) {
  4584. info->tx_enabled = true;
  4585. if ( info->params.flags & HDLC_FLAG_AUTO_CTS )
  4586. usc_EnableTransmitter(info,ENABLE_AUTO_CTS);
  4587. else
  4588. usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
  4589. }
  4590. } /* end of usc_start_transmitter() */
  4591. /* usc_stop_transmitter()
  4592. *
  4593. * Stops the transmitter and DMA
  4594. *
  4595. * Arguments: info pointer to device isntance data
  4596. * Return Value: None
  4597. */
  4598. static void usc_stop_transmitter( struct mgsl_struct *info )
  4599. {
  4600. if (debug_level >= DEBUG_LEVEL_ISR)
  4601. printk("%s(%d):usc_stop_transmitter(%s)\n",
  4602. __FILE__,__LINE__, info->device_name );
  4603. del_timer(&info->tx_timer);
  4604. usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
  4605. usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA );
  4606. usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA );
  4607. usc_EnableTransmitter(info,DISABLE_UNCONDITIONAL);
  4608. usc_DmaCmd( info, DmaCmd_ResetTxChannel );
  4609. usc_RTCmd( info, RTCmd_PurgeTxFifo );
  4610. info->tx_enabled = false;
  4611. info->tx_active = false;
  4612. } /* end of usc_stop_transmitter() */
  4613. /* usc_load_txfifo()
  4614. *
  4615. * Fill the transmit FIFO until the FIFO is full or
  4616. * there is no more data to load.
  4617. *
  4618. * Arguments: info pointer to device extension (instance data)
  4619. * Return Value: None
  4620. */
  4621. static void usc_load_txfifo( struct mgsl_struct *info )
  4622. {
  4623. int Fifocount;
  4624. u8 TwoBytes[2];
  4625. if ( !info->xmit_cnt && !info->x_char )
  4626. return;
  4627. /* Select transmit FIFO status readback in TICR */
  4628. usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
  4629. /* load the Transmit FIFO until FIFOs full or all data sent */
  4630. while( (Fifocount = usc_InReg(info, TICR) >> 8) && info->xmit_cnt ) {
  4631. /* there is more space in the transmit FIFO and */
  4632. /* there is more data in transmit buffer */
  4633. if ( (info->xmit_cnt > 1) && (Fifocount > 1) && !info->x_char ) {
  4634. /* write a 16-bit word from transmit buffer to 16C32 */
  4635. TwoBytes[0] = info->xmit_buf[info->xmit_tail++];
  4636. info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
  4637. TwoBytes[1] = info->xmit_buf[info->xmit_tail++];
  4638. info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
  4639. outw( *((u16 *)TwoBytes), info->io_base + DATAREG);
  4640. info->xmit_cnt -= 2;
  4641. info->icount.tx += 2;
  4642. } else {
  4643. /* only 1 byte left to transmit or 1 FIFO slot left */
  4644. outw( (inw( info->io_base + CCAR) & 0x0780) | (TDR+LSBONLY),
  4645. info->io_base + CCAR );
  4646. if (info->x_char) {
  4647. /* transmit pending high priority char */
  4648. outw( info->x_char,info->io_base + CCAR );
  4649. info->x_char = 0;
  4650. } else {
  4651. outw( info->xmit_buf[info->xmit_tail++],info->io_base + CCAR );
  4652. info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
  4653. info->xmit_cnt--;
  4654. }
  4655. info->icount.tx++;
  4656. }
  4657. }
  4658. } /* end of usc_load_txfifo() */
  4659. /* usc_reset()
  4660. *
  4661. * Reset the adapter to a known state and prepare it for further use.
  4662. *
  4663. * Arguments: info pointer to device instance data
  4664. * Return Value: None
  4665. */
  4666. static void usc_reset( struct mgsl_struct *info )
  4667. {
  4668. int i;
  4669. u32 readval;
  4670. /* Set BIT30 of Misc Control Register */
  4671. /* (Local Control Register 0x50) to force reset of USC. */
  4672. volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
  4673. u32 *LCR0BRDR = (u32 *)(info->lcr_base + 0x28);
  4674. info->misc_ctrl_value |= BIT30;
  4675. *MiscCtrl = info->misc_ctrl_value;
  4676. /*
  4677. * Force at least 170ns delay before clearing reset bit. Each read from
  4678. * LCR takes at least 30ns so 10 times for 300ns to be safe.
  4679. */
  4680. for(i=0;i<10;i++)
  4681. readval = *MiscCtrl;
  4682. info->misc_ctrl_value &= ~BIT30;
  4683. *MiscCtrl = info->misc_ctrl_value;
  4684. *LCR0BRDR = BUS_DESCRIPTOR(
  4685. 1, // Write Strobe Hold (0-3)
  4686. 2, // Write Strobe Delay (0-3)
  4687. 2, // Read Strobe Delay (0-3)
  4688. 0, // NWDD (Write data-data) (0-3)
  4689. 4, // NWAD (Write Addr-data) (0-31)
  4690. 0, // NXDA (Read/Write Data-Addr) (0-3)
  4691. 0, // NRDD (Read Data-Data) (0-3)
  4692. 5 // NRAD (Read Addr-Data) (0-31)
  4693. );
  4694. info->mbre_bit = 0;
  4695. info->loopback_bits = 0;
  4696. info->usc_idle_mode = 0;
  4697. /*
  4698. * Program the Bus Configuration Register (BCR)
  4699. *
  4700. * <15> 0 Don't use separate address
  4701. * <14..6> 0 reserved
  4702. * <5..4> 00 IAckmode = Default, don't care
  4703. * <3> 1 Bus Request Totem Pole output
  4704. * <2> 1 Use 16 Bit data bus
  4705. * <1> 0 IRQ Totem Pole output
  4706. * <0> 0 Don't Shift Right Addr
  4707. *
  4708. * 0000 0000 0000 1100 = 0x000c
  4709. *
  4710. * By writing to io_base + SDPIN the Wait/Ack pin is
  4711. * programmed to work as a Wait pin.
  4712. */
  4713. outw( 0x000c,info->io_base + SDPIN );
  4714. outw( 0,info->io_base );
  4715. outw( 0,info->io_base + CCAR );
  4716. /* select little endian byte ordering */
  4717. usc_RTCmd( info, RTCmd_SelectLittleEndian );
  4718. /* Port Control Register (PCR)
  4719. *
  4720. * <15..14> 11 Port 7 is Output (~DMAEN, Bit 14 : 0 = Enabled)
  4721. * <13..12> 11 Port 6 is Output (~INTEN, Bit 12 : 0 = Enabled)
  4722. * <11..10> 00 Port 5 is Input (No Connect, Don't Care)
  4723. * <9..8> 00 Port 4 is Input (No Connect, Don't Care)
  4724. * <7..6> 11 Port 3 is Output (~RTS, Bit 6 : 0 = Enabled )
  4725. * <5..4> 11 Port 2 is Output (~DTR, Bit 4 : 0 = Enabled )
  4726. * <3..2> 01 Port 1 is Input (Dedicated RxC)
  4727. * <1..0> 01 Port 0 is Input (Dedicated TxC)
  4728. *
  4729. * 1111 0000 1111 0101 = 0xf0f5
  4730. */
  4731. usc_OutReg( info, PCR, 0xf0f5 );
  4732. /*
  4733. * Input/Output Control Register
  4734. *
  4735. * <15..14> 00 CTS is active low input
  4736. * <13..12> 00 DCD is active low input
  4737. * <11..10> 00 TxREQ pin is input (DSR)
  4738. * <9..8> 00 RxREQ pin is input (RI)
  4739. * <7..6> 00 TxD is output (Transmit Data)
  4740. * <5..3> 000 TxC Pin in Input (14.7456MHz Clock)
  4741. * <2..0> 100 RxC is Output (drive with BRG0)
  4742. *
  4743. * 0000 0000 0000 0100 = 0x0004
  4744. */
  4745. usc_OutReg( info, IOCR, 0x0004 );
  4746. } /* end of usc_reset() */
  4747. /* usc_set_async_mode()
  4748. *
  4749. * Program adapter for asynchronous communications.
  4750. *
  4751. * Arguments: info pointer to device instance data
  4752. * Return Value: None
  4753. */
  4754. static void usc_set_async_mode( struct mgsl_struct *info )
  4755. {
  4756. u16 RegValue;
  4757. /* disable interrupts while programming USC */
  4758. usc_DisableMasterIrqBit( info );
  4759. outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
  4760. usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */
  4761. usc_loopback_frame( info );
  4762. /* Channel mode Register (CMR)
  4763. *
  4764. * <15..14> 00 Tx Sub modes, 00 = 1 Stop Bit
  4765. * <13..12> 00 00 = 16X Clock
  4766. * <11..8> 0000 Transmitter mode = Asynchronous
  4767. * <7..6> 00 reserved?
  4768. * <5..4> 00 Rx Sub modes, 00 = 16X Clock
  4769. * <3..0> 0000 Receiver mode = Asynchronous
  4770. *
  4771. * 0000 0000 0000 0000 = 0x0
  4772. */
  4773. RegValue = 0;
  4774. if ( info->params.stop_bits != 1 )
  4775. RegValue |= BIT14;
  4776. usc_OutReg( info, CMR, RegValue );
  4777. /* Receiver mode Register (RMR)
  4778. *
  4779. * <15..13> 000 encoding = None
  4780. * <12..08> 00000 reserved (Sync Only)
  4781. * <7..6> 00 Even parity
  4782. * <5> 0 parity disabled
  4783. * <4..2> 000 Receive Char Length = 8 bits
  4784. * <1..0> 00 Disable Receiver
  4785. *
  4786. * 0000 0000 0000 0000 = 0x0
  4787. */
  4788. RegValue = 0;
  4789. if ( info->params.data_bits != 8 )
  4790. RegValue |= BIT4 | BIT3 | BIT2;
  4791. if ( info->params.parity != ASYNC_PARITY_NONE ) {
  4792. RegValue |= BIT5;
  4793. if ( info->params.parity != ASYNC_PARITY_ODD )
  4794. RegValue |= BIT6;
  4795. }
  4796. usc_OutReg( info, RMR, RegValue );
  4797. /* Set IRQ trigger level */
  4798. usc_RCmd( info, RCmd_SelectRicrIntLevel );
  4799. /* Receive Interrupt Control Register (RICR)
  4800. *
  4801. * <15..8> ? RxFIFO IRQ Request Level
  4802. *
  4803. * Note: For async mode the receive FIFO level must be set
  4804. * to 0 to avoid the situation where the FIFO contains fewer bytes
  4805. * than the trigger level and no more data is expected.
  4806. *
  4807. * <7> 0 Exited Hunt IA (Interrupt Arm)
  4808. * <6> 0 Idle Received IA
  4809. * <5> 0 Break/Abort IA
  4810. * <4> 0 Rx Bound IA
  4811. * <3> 0 Queued status reflects oldest byte in FIFO
  4812. * <2> 0 Abort/PE IA
  4813. * <1> 0 Rx Overrun IA
  4814. * <0> 0 Select TC0 value for readback
  4815. *
  4816. * 0000 0000 0100 0000 = 0x0000 + (FIFOLEVEL in MSB)
  4817. */
  4818. usc_OutReg( info, RICR, 0x0000 );
  4819. usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
  4820. usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
  4821. /* Transmit mode Register (TMR)
  4822. *
  4823. * <15..13> 000 encoding = None
  4824. * <12..08> 00000 reserved (Sync Only)
  4825. * <7..6> 00 Transmit parity Even
  4826. * <5> 0 Transmit parity Disabled
  4827. * <4..2> 000 Tx Char Length = 8 bits
  4828. * <1..0> 00 Disable Transmitter
  4829. *
  4830. * 0000 0000 0000 0000 = 0x0
  4831. */
  4832. RegValue = 0;
  4833. if ( info->params.data_bits != 8 )
  4834. RegValue |= BIT4 | BIT3 | BIT2;
  4835. if ( info->params.parity != ASYNC_PARITY_NONE ) {
  4836. RegValue |= BIT5;
  4837. if ( info->params.parity != ASYNC_PARITY_ODD )
  4838. RegValue |= BIT6;
  4839. }
  4840. usc_OutReg( info, TMR, RegValue );
  4841. usc_set_txidle( info );
  4842. /* Set IRQ trigger level */
  4843. usc_TCmd( info, TCmd_SelectTicrIntLevel );
  4844. /* Transmit Interrupt Control Register (TICR)
  4845. *
  4846. * <15..8> ? Transmit FIFO IRQ Level
  4847. * <7> 0 Present IA (Interrupt Arm)
  4848. * <6> 1 Idle Sent IA
  4849. * <5> 0 Abort Sent IA
  4850. * <4> 0 EOF/EOM Sent IA
  4851. * <3> 0 CRC Sent IA
  4852. * <2> 0 1 = Wait for SW Trigger to Start Frame
  4853. * <1> 0 Tx Underrun IA
  4854. * <0> 0 TC0 constant on read back
  4855. *
  4856. * 0000 0000 0100 0000 = 0x0040
  4857. */
  4858. usc_OutReg( info, TICR, 0x1f40 );
  4859. usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
  4860. usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
  4861. usc_enable_async_clock( info, info->params.data_rate );
  4862. /* Channel Control/status Register (CCSR)
  4863. *
  4864. * <15> X RCC FIFO Overflow status (RO)
  4865. * <14> X RCC FIFO Not Empty status (RO)
  4866. * <13> 0 1 = Clear RCC FIFO (WO)
  4867. * <12> X DPLL in Sync status (RO)
  4868. * <11> X DPLL 2 Missed Clocks status (RO)
  4869. * <10> X DPLL 1 Missed Clock status (RO)
  4870. * <9..8> 00 DPLL Resync on rising and falling edges (RW)
  4871. * <7> X SDLC Loop On status (RO)
  4872. * <6> X SDLC Loop Send status (RO)
  4873. * <5> 1 Bypass counters for TxClk and RxClk (RW)
  4874. * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
  4875. * <1..0> 00 reserved
  4876. *
  4877. * 0000 0000 0010 0000 = 0x0020
  4878. */
  4879. usc_OutReg( info, CCSR, 0x0020 );
  4880. usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA +
  4881. RECEIVE_DATA + RECEIVE_STATUS );
  4882. usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA +
  4883. RECEIVE_DATA + RECEIVE_STATUS );
  4884. usc_EnableMasterIrqBit( info );
  4885. if (info->params.loopback) {
  4886. info->loopback_bits = 0x300;
  4887. outw(0x0300, info->io_base + CCAR);
  4888. }
  4889. } /* end of usc_set_async_mode() */
  4890. /* usc_loopback_frame()
  4891. *
  4892. * Loop back a small (2 byte) dummy SDLC frame.
  4893. * Interrupts and DMA are NOT used. The purpose of this is to
  4894. * clear any 'stale' status info left over from running in async mode.
  4895. *
  4896. * The 16C32 shows the strange behaviour of marking the 1st
  4897. * received SDLC frame with a CRC error even when there is no
  4898. * CRC error. To get around this a small dummy from of 2 bytes
  4899. * is looped back when switching from async to sync mode.
  4900. *
  4901. * Arguments: info pointer to device instance data
  4902. * Return Value: None
  4903. */
  4904. static void usc_loopback_frame( struct mgsl_struct *info )
  4905. {
  4906. int i;
  4907. unsigned long oldmode = info->params.mode;
  4908. info->params.mode = MGSL_MODE_HDLC;
  4909. usc_DisableMasterIrqBit( info );
  4910. usc_set_sdlc_mode( info );
  4911. usc_enable_loopback( info, 1 );
  4912. /* Write 16-bit Time Constant for BRG0 */
  4913. usc_OutReg( info, TC0R, 0 );
  4914. /* Channel Control Register (CCR)
  4915. *
  4916. * <15..14> 00 Don't use 32-bit Tx Control Blocks (TCBs)
  4917. * <13> 0 Trigger Tx on SW Command Disabled
  4918. * <12> 0 Flag Preamble Disabled
  4919. * <11..10> 00 Preamble Length = 8-Bits
  4920. * <9..8> 01 Preamble Pattern = flags
  4921. * <7..6> 10 Don't use 32-bit Rx status Blocks (RSBs)
  4922. * <5> 0 Trigger Rx on SW Command Disabled
  4923. * <4..0> 0 reserved
  4924. *
  4925. * 0000 0001 0000 0000 = 0x0100
  4926. */
  4927. usc_OutReg( info, CCR, 0x0100 );
  4928. /* SETUP RECEIVER */
  4929. usc_RTCmd( info, RTCmd_PurgeRxFifo );
  4930. usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
  4931. /* SETUP TRANSMITTER */
  4932. /* Program the Transmit Character Length Register (TCLR) */
  4933. /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
  4934. usc_OutReg( info, TCLR, 2 );
  4935. usc_RTCmd( info, RTCmd_PurgeTxFifo );
  4936. /* unlatch Tx status bits, and start transmit channel. */
  4937. usc_UnlatchTxstatusBits(info,TXSTATUS_ALL);
  4938. outw(0,info->io_base + DATAREG);
  4939. /* ENABLE TRANSMITTER */
  4940. usc_TCmd( info, TCmd_SendFrame );
  4941. usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
  4942. /* WAIT FOR RECEIVE COMPLETE */
  4943. for (i=0 ; i<1000 ; i++)
  4944. if (usc_InReg( info, RCSR ) & (BIT8 | BIT4 | BIT3 | BIT1))
  4945. break;
  4946. /* clear Internal Data loopback mode */
  4947. usc_enable_loopback(info, 0);
  4948. usc_EnableMasterIrqBit(info);
  4949. info->params.mode = oldmode;
  4950. } /* end of usc_loopback_frame() */
  4951. /* usc_set_sync_mode() Programs the USC for SDLC communications.
  4952. *
  4953. * Arguments: info pointer to adapter info structure
  4954. * Return Value: None
  4955. */
  4956. static void usc_set_sync_mode( struct mgsl_struct *info )
  4957. {
  4958. usc_loopback_frame( info );
  4959. usc_set_sdlc_mode( info );
  4960. usc_enable_aux_clock(info, info->params.clock_speed);
  4961. if (info->params.loopback)
  4962. usc_enable_loopback(info,1);
  4963. } /* end of mgsl_set_sync_mode() */
  4964. /* usc_set_txidle() Set the HDLC idle mode for the transmitter.
  4965. *
  4966. * Arguments: info pointer to device instance data
  4967. * Return Value: None
  4968. */
  4969. static void usc_set_txidle( struct mgsl_struct *info )
  4970. {
  4971. u16 usc_idle_mode = IDLEMODE_FLAGS;
  4972. /* Map API idle mode to USC register bits */
  4973. switch( info->idle_mode ){
  4974. case HDLC_TXIDLE_FLAGS: usc_idle_mode = IDLEMODE_FLAGS; break;
  4975. case HDLC_TXIDLE_ALT_ZEROS_ONES: usc_idle_mode = IDLEMODE_ALT_ONE_ZERO; break;
  4976. case HDLC_TXIDLE_ZEROS: usc_idle_mode = IDLEMODE_ZERO; break;
  4977. case HDLC_TXIDLE_ONES: usc_idle_mode = IDLEMODE_ONE; break;
  4978. case HDLC_TXIDLE_ALT_MARK_SPACE: usc_idle_mode = IDLEMODE_ALT_MARK_SPACE; break;
  4979. case HDLC_TXIDLE_SPACE: usc_idle_mode = IDLEMODE_SPACE; break;
  4980. case HDLC_TXIDLE_MARK: usc_idle_mode = IDLEMODE_MARK; break;
  4981. }
  4982. info->usc_idle_mode = usc_idle_mode;
  4983. //usc_OutReg(info, TCSR, usc_idle_mode);
  4984. info->tcsr_value &= ~IDLEMODE_MASK; /* clear idle mode bits */
  4985. info->tcsr_value += usc_idle_mode;
  4986. usc_OutReg(info, TCSR, info->tcsr_value);
  4987. /*
  4988. * if SyncLink WAN adapter is running in external sync mode, the
  4989. * transmitter has been set to Monosync in order to try to mimic
  4990. * a true raw outbound bit stream. Monosync still sends an open/close
  4991. * sync char at the start/end of a frame. Try to match those sync
  4992. * patterns to the idle mode set here
  4993. */
  4994. if ( info->params.mode == MGSL_MODE_RAW ) {
  4995. unsigned char syncpat = 0;
  4996. switch( info->idle_mode ) {
  4997. case HDLC_TXIDLE_FLAGS:
  4998. syncpat = 0x7e;
  4999. break;
  5000. case HDLC_TXIDLE_ALT_ZEROS_ONES:
  5001. syncpat = 0x55;
  5002. break;
  5003. case HDLC_TXIDLE_ZEROS:
  5004. case HDLC_TXIDLE_SPACE:
  5005. syncpat = 0x00;
  5006. break;
  5007. case HDLC_TXIDLE_ONES:
  5008. case HDLC_TXIDLE_MARK:
  5009. syncpat = 0xff;
  5010. break;
  5011. case HDLC_TXIDLE_ALT_MARK_SPACE:
  5012. syncpat = 0xaa;
  5013. break;
  5014. }
  5015. usc_SetTransmitSyncChars(info,syncpat,syncpat);
  5016. }
  5017. } /* end of usc_set_txidle() */
  5018. /* usc_get_serial_signals()
  5019. *
  5020. * Query the adapter for the state of the V24 status (input) signals.
  5021. *
  5022. * Arguments: info pointer to device instance data
  5023. * Return Value: None
  5024. */
  5025. static void usc_get_serial_signals( struct mgsl_struct *info )
  5026. {
  5027. u16 status;
  5028. /* clear all serial signals except RTS and DTR */
  5029. info->serial_signals &= SerialSignal_RTS | SerialSignal_DTR;
  5030. /* Read the Misc Interrupt status Register (MISR) to get */
  5031. /* the V24 status signals. */
  5032. status = usc_InReg( info, MISR );
  5033. /* set serial signal bits to reflect MISR */
  5034. if ( status & MISCSTATUS_CTS )
  5035. info->serial_signals |= SerialSignal_CTS;
  5036. if ( status & MISCSTATUS_DCD )
  5037. info->serial_signals |= SerialSignal_DCD;
  5038. if ( status & MISCSTATUS_RI )
  5039. info->serial_signals |= SerialSignal_RI;
  5040. if ( status & MISCSTATUS_DSR )
  5041. info->serial_signals |= SerialSignal_DSR;
  5042. } /* end of usc_get_serial_signals() */
  5043. /* usc_set_serial_signals()
  5044. *
  5045. * Set the state of RTS and DTR based on contents of
  5046. * serial_signals member of device extension.
  5047. *
  5048. * Arguments: info pointer to device instance data
  5049. * Return Value: None
  5050. */
  5051. static void usc_set_serial_signals( struct mgsl_struct *info )
  5052. {
  5053. u16 Control;
  5054. unsigned char V24Out = info->serial_signals;
  5055. /* get the current value of the Port Control Register (PCR) */
  5056. Control = usc_InReg( info, PCR );
  5057. if ( V24Out & SerialSignal_RTS )
  5058. Control &= ~(BIT6);
  5059. else
  5060. Control |= BIT6;
  5061. if ( V24Out & SerialSignal_DTR )
  5062. Control &= ~(BIT4);
  5063. else
  5064. Control |= BIT4;
  5065. usc_OutReg( info, PCR, Control );
  5066. } /* end of usc_set_serial_signals() */
  5067. /* usc_enable_async_clock()
  5068. *
  5069. * Enable the async clock at the specified frequency.
  5070. *
  5071. * Arguments: info pointer to device instance data
  5072. * data_rate data rate of clock in bps
  5073. * 0 disables the AUX clock.
  5074. * Return Value: None
  5075. */
  5076. static void usc_enable_async_clock( struct mgsl_struct *info, u32 data_rate )
  5077. {
  5078. if ( data_rate ) {
  5079. /*
  5080. * Clock mode Control Register (CMCR)
  5081. *
  5082. * <15..14> 00 counter 1 Disabled
  5083. * <13..12> 00 counter 0 Disabled
  5084. * <11..10> 11 BRG1 Input is TxC Pin
  5085. * <9..8> 11 BRG0 Input is TxC Pin
  5086. * <7..6> 01 DPLL Input is BRG1 Output
  5087. * <5..3> 100 TxCLK comes from BRG0
  5088. * <2..0> 100 RxCLK comes from BRG0
  5089. *
  5090. * 0000 1111 0110 0100 = 0x0f64
  5091. */
  5092. usc_OutReg( info, CMCR, 0x0f64 );
  5093. /*
  5094. * Write 16-bit Time Constant for BRG0
  5095. * Time Constant = (ClkSpeed / data_rate) - 1
  5096. * ClkSpeed = 921600 (ISA), 691200 (PCI)
  5097. */
  5098. usc_OutReg( info, TC0R, (u16)((691200/data_rate) - 1) );
  5099. /*
  5100. * Hardware Configuration Register (HCR)
  5101. * Clear Bit 1, BRG0 mode = Continuous
  5102. * Set Bit 0 to enable BRG0.
  5103. */
  5104. usc_OutReg( info, HCR,
  5105. (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
  5106. /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
  5107. usc_OutReg( info, IOCR,
  5108. (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
  5109. } else {
  5110. /* data rate == 0 so turn off BRG0 */
  5111. usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
  5112. }
  5113. } /* end of usc_enable_async_clock() */
  5114. /*
  5115. * Buffer Structures:
  5116. *
  5117. * Normal memory access uses virtual addresses that can make discontiguous
  5118. * physical memory pages appear to be contiguous in the virtual address
  5119. * space (the processors memory mapping handles the conversions).
  5120. *
  5121. * DMA transfers require physically contiguous memory. This is because
  5122. * the DMA system controller and DMA bus masters deal with memory using
  5123. * only physical addresses.
  5124. *
  5125. * This causes a problem under Windows NT when large DMA buffers are
  5126. * needed. Fragmentation of the nonpaged pool prevents allocations of
  5127. * physically contiguous buffers larger than the PAGE_SIZE.
  5128. *
  5129. * However the 16C32 supports Bus Master Scatter/Gather DMA which
  5130. * allows DMA transfers to physically discontiguous buffers. Information
  5131. * about each data transfer buffer is contained in a memory structure
  5132. * called a 'buffer entry'. A list of buffer entries is maintained
  5133. * to track and control the use of the data transfer buffers.
  5134. *
  5135. * To support this strategy we will allocate sufficient PAGE_SIZE
  5136. * contiguous memory buffers to allow for the total required buffer
  5137. * space.
  5138. *
  5139. * The 16C32 accesses the list of buffer entries using Bus Master
  5140. * DMA. Control information is read from the buffer entries by the
  5141. * 16C32 to control data transfers. status information is written to
  5142. * the buffer entries by the 16C32 to indicate the status of completed
  5143. * transfers.
  5144. *
  5145. * The CPU writes control information to the buffer entries to control
  5146. * the 16C32 and reads status information from the buffer entries to
  5147. * determine information about received and transmitted frames.
  5148. *
  5149. * Because the CPU and 16C32 (adapter) both need simultaneous access
  5150. * to the buffer entries, the buffer entry memory is allocated with
  5151. * HalAllocateCommonBuffer(). This restricts the size of the buffer
  5152. * entry list to PAGE_SIZE.
  5153. *
  5154. * The actual data buffers on the other hand will only be accessed
  5155. * by the CPU or the adapter but not by both simultaneously. This allows
  5156. * Scatter/Gather packet based DMA procedures for using physically
  5157. * discontiguous pages.
  5158. */
  5159. /*
  5160. * mgsl_reset_tx_dma_buffers()
  5161. *
  5162. * Set the count for all transmit buffers to 0 to indicate the
  5163. * buffer is available for use and set the current buffer to the
  5164. * first buffer. This effectively makes all buffers free and
  5165. * discards any data in buffers.
  5166. *
  5167. * Arguments: info pointer to device instance data
  5168. * Return Value: None
  5169. */
  5170. static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info )
  5171. {
  5172. unsigned int i;
  5173. for ( i = 0; i < info->tx_buffer_count; i++ ) {
  5174. *((unsigned long *)&(info->tx_buffer_list[i].count)) = 0;
  5175. }
  5176. info->current_tx_buffer = 0;
  5177. info->start_tx_dma_buffer = 0;
  5178. info->tx_dma_buffers_used = 0;
  5179. info->get_tx_holding_index = 0;
  5180. info->put_tx_holding_index = 0;
  5181. info->tx_holding_count = 0;
  5182. } /* end of mgsl_reset_tx_dma_buffers() */
  5183. /*
  5184. * num_free_tx_dma_buffers()
  5185. *
  5186. * returns the number of free tx dma buffers available
  5187. *
  5188. * Arguments: info pointer to device instance data
  5189. * Return Value: number of free tx dma buffers
  5190. */
  5191. static int num_free_tx_dma_buffers(struct mgsl_struct *info)
  5192. {
  5193. return info->tx_buffer_count - info->tx_dma_buffers_used;
  5194. }
  5195. /*
  5196. * mgsl_reset_rx_dma_buffers()
  5197. *
  5198. * Set the count for all receive buffers to DMABUFFERSIZE
  5199. * and set the current buffer to the first buffer. This effectively
  5200. * makes all buffers free and discards any data in buffers.
  5201. *
  5202. * Arguments: info pointer to device instance data
  5203. * Return Value: None
  5204. */
  5205. static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info )
  5206. {
  5207. unsigned int i;
  5208. for ( i = 0; i < info->rx_buffer_count; i++ ) {
  5209. *((unsigned long *)&(info->rx_buffer_list[i].count)) = DMABUFFERSIZE;
  5210. // info->rx_buffer_list[i].count = DMABUFFERSIZE;
  5211. // info->rx_buffer_list[i].status = 0;
  5212. }
  5213. info->current_rx_buffer = 0;
  5214. } /* end of mgsl_reset_rx_dma_buffers() */
  5215. /*
  5216. * mgsl_free_rx_frame_buffers()
  5217. *
  5218. * Free the receive buffers used by a received SDLC
  5219. * frame such that the buffers can be reused.
  5220. *
  5221. * Arguments:
  5222. *
  5223. * info pointer to device instance data
  5224. * StartIndex index of 1st receive buffer of frame
  5225. * EndIndex index of last receive buffer of frame
  5226. *
  5227. * Return Value: None
  5228. */
  5229. static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex )
  5230. {
  5231. bool Done = false;
  5232. DMABUFFERENTRY *pBufEntry;
  5233. unsigned int Index;
  5234. /* Starting with 1st buffer entry of the frame clear the status */
  5235. /* field and set the count field to DMA Buffer Size. */
  5236. Index = StartIndex;
  5237. while( !Done ) {
  5238. pBufEntry = &(info->rx_buffer_list[Index]);
  5239. if ( Index == EndIndex ) {
  5240. /* This is the last buffer of the frame! */
  5241. Done = true;
  5242. }
  5243. /* reset current buffer for reuse */
  5244. // pBufEntry->status = 0;
  5245. // pBufEntry->count = DMABUFFERSIZE;
  5246. *((unsigned long *)&(pBufEntry->count)) = DMABUFFERSIZE;
  5247. /* advance to next buffer entry in linked list */
  5248. Index++;
  5249. if ( Index == info->rx_buffer_count )
  5250. Index = 0;
  5251. }
  5252. /* set current buffer to next buffer after last buffer of frame */
  5253. info->current_rx_buffer = Index;
  5254. } /* end of free_rx_frame_buffers() */
  5255. /* mgsl_get_rx_frame()
  5256. *
  5257. * This function attempts to return a received SDLC frame from the
  5258. * receive DMA buffers. Only frames received without errors are returned.
  5259. *
  5260. * Arguments: info pointer to device extension
  5261. * Return Value: true if frame returned, otherwise false
  5262. */
  5263. static bool mgsl_get_rx_frame(struct mgsl_struct *info)
  5264. {
  5265. unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
  5266. unsigned short status;
  5267. DMABUFFERENTRY *pBufEntry;
  5268. unsigned int framesize = 0;
  5269. bool ReturnCode = false;
  5270. unsigned long flags;
  5271. struct tty_struct *tty = info->port.tty;
  5272. bool return_frame = false;
  5273. /*
  5274. * current_rx_buffer points to the 1st buffer of the next available
  5275. * receive frame. To find the last buffer of the frame look for
  5276. * a non-zero status field in the buffer entries. (The status
  5277. * field is set by the 16C32 after completing a receive frame.
  5278. */
  5279. StartIndex = EndIndex = info->current_rx_buffer;
  5280. while( !info->rx_buffer_list[EndIndex].status ) {
  5281. /*
  5282. * If the count field of the buffer entry is non-zero then
  5283. * this buffer has not been used. (The 16C32 clears the count
  5284. * field when it starts using the buffer.) If an unused buffer
  5285. * is encountered then there are no frames available.
  5286. */
  5287. if ( info->rx_buffer_list[EndIndex].count )
  5288. goto Cleanup;
  5289. /* advance to next buffer entry in linked list */
  5290. EndIndex++;
  5291. if ( EndIndex == info->rx_buffer_count )
  5292. EndIndex = 0;
  5293. /* if entire list searched then no frame available */
  5294. if ( EndIndex == StartIndex ) {
  5295. /* If this occurs then something bad happened,
  5296. * all buffers have been 'used' but none mark
  5297. * the end of a frame. Reset buffers and receiver.
  5298. */
  5299. if ( info->rx_enabled ){
  5300. spin_lock_irqsave(&info->irq_spinlock,flags);
  5301. usc_start_receiver(info);
  5302. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  5303. }
  5304. goto Cleanup;
  5305. }
  5306. }
  5307. /* check status of receive frame */
  5308. status = info->rx_buffer_list[EndIndex].status;
  5309. if ( status & (RXSTATUS_SHORT_FRAME | RXSTATUS_OVERRUN |
  5310. RXSTATUS_CRC_ERROR | RXSTATUS_ABORT) ) {
  5311. if ( status & RXSTATUS_SHORT_FRAME )
  5312. info->icount.rxshort++;
  5313. else if ( status & RXSTATUS_ABORT )
  5314. info->icount.rxabort++;
  5315. else if ( status & RXSTATUS_OVERRUN )
  5316. info->icount.rxover++;
  5317. else {
  5318. info->icount.rxcrc++;
  5319. if ( info->params.crc_type & HDLC_CRC_RETURN_EX )
  5320. return_frame = true;
  5321. }
  5322. framesize = 0;
  5323. #if SYNCLINK_GENERIC_HDLC
  5324. {
  5325. info->netdev->stats.rx_errors++;
  5326. info->netdev->stats.rx_frame_errors++;
  5327. }
  5328. #endif
  5329. } else
  5330. return_frame = true;
  5331. if ( return_frame ) {
  5332. /* receive frame has no errors, get frame size.
  5333. * The frame size is the starting value of the RCC (which was
  5334. * set to 0xffff) minus the ending value of the RCC (decremented
  5335. * once for each receive character) minus 2 for the 16-bit CRC.
  5336. */
  5337. framesize = RCLRVALUE - info->rx_buffer_list[EndIndex].rcc;
  5338. /* adjust frame size for CRC if any */
  5339. if ( info->params.crc_type == HDLC_CRC_16_CCITT )
  5340. framesize -= 2;
  5341. else if ( info->params.crc_type == HDLC_CRC_32_CCITT )
  5342. framesize -= 4;
  5343. }
  5344. if ( debug_level >= DEBUG_LEVEL_BH )
  5345. printk("%s(%d):mgsl_get_rx_frame(%s) status=%04X size=%d\n",
  5346. __FILE__,__LINE__,info->device_name,status,framesize);
  5347. if ( debug_level >= DEBUG_LEVEL_DATA )
  5348. mgsl_trace_block(info,info->rx_buffer_list[StartIndex].virt_addr,
  5349. min_t(int, framesize, DMABUFFERSIZE),0);
  5350. if (framesize) {
  5351. if ( ( (info->params.crc_type & HDLC_CRC_RETURN_EX) &&
  5352. ((framesize+1) > info->max_frame_size) ) ||
  5353. (framesize > info->max_frame_size) )
  5354. info->icount.rxlong++;
  5355. else {
  5356. /* copy dma buffer(s) to contiguous intermediate buffer */
  5357. int copy_count = framesize;
  5358. int index = StartIndex;
  5359. unsigned char *ptmp = info->intermediate_rxbuffer;
  5360. if ( !(status & RXSTATUS_CRC_ERROR))
  5361. info->icount.rxok++;
  5362. while(copy_count) {
  5363. int partial_count;
  5364. if ( copy_count > DMABUFFERSIZE )
  5365. partial_count = DMABUFFERSIZE;
  5366. else
  5367. partial_count = copy_count;
  5368. pBufEntry = &(info->rx_buffer_list[index]);
  5369. memcpy( ptmp, pBufEntry->virt_addr, partial_count );
  5370. ptmp += partial_count;
  5371. copy_count -= partial_count;
  5372. if ( ++index == info->rx_buffer_count )
  5373. index = 0;
  5374. }
  5375. if ( info->params.crc_type & HDLC_CRC_RETURN_EX ) {
  5376. ++framesize;
  5377. *ptmp = (status & RXSTATUS_CRC_ERROR ?
  5378. RX_CRC_ERROR :
  5379. RX_OK);
  5380. if ( debug_level >= DEBUG_LEVEL_DATA )
  5381. printk("%s(%d):mgsl_get_rx_frame(%s) rx frame status=%d\n",
  5382. __FILE__,__LINE__,info->device_name,
  5383. *ptmp);
  5384. }
  5385. #if SYNCLINK_GENERIC_HDLC
  5386. if (info->netcount)
  5387. hdlcdev_rx(info,info->intermediate_rxbuffer,framesize);
  5388. else
  5389. #endif
  5390. ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
  5391. }
  5392. }
  5393. /* Free the buffers used by this frame. */
  5394. mgsl_free_rx_frame_buffers( info, StartIndex, EndIndex );
  5395. ReturnCode = true;
  5396. Cleanup:
  5397. if ( info->rx_enabled && info->rx_overflow ) {
  5398. /* The receiver needs to restarted because of
  5399. * a receive overflow (buffer or FIFO). If the
  5400. * receive buffers are now empty, then restart receiver.
  5401. */
  5402. if ( !info->rx_buffer_list[EndIndex].status &&
  5403. info->rx_buffer_list[EndIndex].count ) {
  5404. spin_lock_irqsave(&info->irq_spinlock,flags);
  5405. usc_start_receiver(info);
  5406. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  5407. }
  5408. }
  5409. return ReturnCode;
  5410. } /* end of mgsl_get_rx_frame() */
  5411. /* mgsl_get_raw_rx_frame()
  5412. *
  5413. * This function attempts to return a received frame from the
  5414. * receive DMA buffers when running in external loop mode. In this mode,
  5415. * we will return at most one DMABUFFERSIZE frame to the application.
  5416. * The USC receiver is triggering off of DCD going active to start a new
  5417. * frame, and DCD going inactive to terminate the frame (similar to
  5418. * processing a closing flag character).
  5419. *
  5420. * In this routine, we will return DMABUFFERSIZE "chunks" at a time.
  5421. * If DCD goes inactive, the last Rx DMA Buffer will have a non-zero
  5422. * status field and the RCC field will indicate the length of the
  5423. * entire received frame. We take this RCC field and get the modulus
  5424. * of RCC and DMABUFFERSIZE to determine if number of bytes in the
  5425. * last Rx DMA buffer and return that last portion of the frame.
  5426. *
  5427. * Arguments: info pointer to device extension
  5428. * Return Value: true if frame returned, otherwise false
  5429. */
  5430. static bool mgsl_get_raw_rx_frame(struct mgsl_struct *info)
  5431. {
  5432. unsigned int CurrentIndex, NextIndex;
  5433. unsigned short status;
  5434. DMABUFFERENTRY *pBufEntry;
  5435. unsigned int framesize = 0;
  5436. bool ReturnCode = false;
  5437. unsigned long flags;
  5438. struct tty_struct *tty = info->port.tty;
  5439. /*
  5440. * current_rx_buffer points to the 1st buffer of the next available
  5441. * receive frame. The status field is set by the 16C32 after
  5442. * completing a receive frame. If the status field of this buffer
  5443. * is zero, either the USC is still filling this buffer or this
  5444. * is one of a series of buffers making up a received frame.
  5445. *
  5446. * If the count field of this buffer is zero, the USC is either
  5447. * using this buffer or has used this buffer. Look at the count
  5448. * field of the next buffer. If that next buffer's count is
  5449. * non-zero, the USC is still actively using the current buffer.
  5450. * Otherwise, if the next buffer's count field is zero, the
  5451. * current buffer is complete and the USC is using the next
  5452. * buffer.
  5453. */
  5454. CurrentIndex = NextIndex = info->current_rx_buffer;
  5455. ++NextIndex;
  5456. if ( NextIndex == info->rx_buffer_count )
  5457. NextIndex = 0;
  5458. if ( info->rx_buffer_list[CurrentIndex].status != 0 ||
  5459. (info->rx_buffer_list[CurrentIndex].count == 0 &&
  5460. info->rx_buffer_list[NextIndex].count == 0)) {
  5461. /*
  5462. * Either the status field of this dma buffer is non-zero
  5463. * (indicating the last buffer of a receive frame) or the next
  5464. * buffer is marked as in use -- implying this buffer is complete
  5465. * and an intermediate buffer for this received frame.
  5466. */
  5467. status = info->rx_buffer_list[CurrentIndex].status;
  5468. if ( status & (RXSTATUS_SHORT_FRAME | RXSTATUS_OVERRUN |
  5469. RXSTATUS_CRC_ERROR | RXSTATUS_ABORT) ) {
  5470. if ( status & RXSTATUS_SHORT_FRAME )
  5471. info->icount.rxshort++;
  5472. else if ( status & RXSTATUS_ABORT )
  5473. info->icount.rxabort++;
  5474. else if ( status & RXSTATUS_OVERRUN )
  5475. info->icount.rxover++;
  5476. else
  5477. info->icount.rxcrc++;
  5478. framesize = 0;
  5479. } else {
  5480. /*
  5481. * A receive frame is available, get frame size and status.
  5482. *
  5483. * The frame size is the starting value of the RCC (which was
  5484. * set to 0xffff) minus the ending value of the RCC (decremented
  5485. * once for each receive character) minus 2 or 4 for the 16-bit
  5486. * or 32-bit CRC.
  5487. *
  5488. * If the status field is zero, this is an intermediate buffer.
  5489. * It's size is 4K.
  5490. *
  5491. * If the DMA Buffer Entry's Status field is non-zero, the
  5492. * receive operation completed normally (ie: DCD dropped). The
  5493. * RCC field is valid and holds the received frame size.
  5494. * It is possible that the RCC field will be zero on a DMA buffer
  5495. * entry with a non-zero status. This can occur if the total
  5496. * frame size (number of bytes between the time DCD goes active
  5497. * to the time DCD goes inactive) exceeds 65535 bytes. In this
  5498. * case the 16C32 has underrun on the RCC count and appears to
  5499. * stop updating this counter to let us know the actual received
  5500. * frame size. If this happens (non-zero status and zero RCC),
  5501. * simply return the entire RxDMA Buffer
  5502. */
  5503. if ( status ) {
  5504. /*
  5505. * In the event that the final RxDMA Buffer is
  5506. * terminated with a non-zero status and the RCC
  5507. * field is zero, we interpret this as the RCC
  5508. * having underflowed (received frame > 65535 bytes).
  5509. *
  5510. * Signal the event to the user by passing back
  5511. * a status of RxStatus_CrcError returning the full
  5512. * buffer and let the app figure out what data is
  5513. * actually valid
  5514. */
  5515. if ( info->rx_buffer_list[CurrentIndex].rcc )
  5516. framesize = RCLRVALUE - info->rx_buffer_list[CurrentIndex].rcc;
  5517. else
  5518. framesize = DMABUFFERSIZE;
  5519. }
  5520. else
  5521. framesize = DMABUFFERSIZE;
  5522. }
  5523. if ( framesize > DMABUFFERSIZE ) {
  5524. /*
  5525. * if running in raw sync mode, ISR handler for
  5526. * End Of Buffer events terminates all buffers at 4K.
  5527. * If this frame size is said to be >4K, get the
  5528. * actual number of bytes of the frame in this buffer.
  5529. */
  5530. framesize = framesize % DMABUFFERSIZE;
  5531. }
  5532. if ( debug_level >= DEBUG_LEVEL_BH )
  5533. printk("%s(%d):mgsl_get_raw_rx_frame(%s) status=%04X size=%d\n",
  5534. __FILE__,__LINE__,info->device_name,status,framesize);
  5535. if ( debug_level >= DEBUG_LEVEL_DATA )
  5536. mgsl_trace_block(info,info->rx_buffer_list[CurrentIndex].virt_addr,
  5537. min_t(int, framesize, DMABUFFERSIZE),0);
  5538. if (framesize) {
  5539. /* copy dma buffer(s) to contiguous intermediate buffer */
  5540. /* NOTE: we never copy more than DMABUFFERSIZE bytes */
  5541. pBufEntry = &(info->rx_buffer_list[CurrentIndex]);
  5542. memcpy( info->intermediate_rxbuffer, pBufEntry->virt_addr, framesize);
  5543. info->icount.rxok++;
  5544. ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
  5545. }
  5546. /* Free the buffers used by this frame. */
  5547. mgsl_free_rx_frame_buffers( info, CurrentIndex, CurrentIndex );
  5548. ReturnCode = true;
  5549. }
  5550. if ( info->rx_enabled && info->rx_overflow ) {
  5551. /* The receiver needs to restarted because of
  5552. * a receive overflow (buffer or FIFO). If the
  5553. * receive buffers are now empty, then restart receiver.
  5554. */
  5555. if ( !info->rx_buffer_list[CurrentIndex].status &&
  5556. info->rx_buffer_list[CurrentIndex].count ) {
  5557. spin_lock_irqsave(&info->irq_spinlock,flags);
  5558. usc_start_receiver(info);
  5559. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  5560. }
  5561. }
  5562. return ReturnCode;
  5563. } /* end of mgsl_get_raw_rx_frame() */
  5564. /* mgsl_load_tx_dma_buffer()
  5565. *
  5566. * Load the transmit DMA buffer with the specified data.
  5567. *
  5568. * Arguments:
  5569. *
  5570. * info pointer to device extension
  5571. * Buffer pointer to buffer containing frame to load
  5572. * BufferSize size in bytes of frame in Buffer
  5573. *
  5574. * Return Value: None
  5575. */
  5576. static void mgsl_load_tx_dma_buffer(struct mgsl_struct *info,
  5577. const char *Buffer, unsigned int BufferSize)
  5578. {
  5579. unsigned short Copycount;
  5580. unsigned int i = 0;
  5581. DMABUFFERENTRY *pBufEntry;
  5582. if ( debug_level >= DEBUG_LEVEL_DATA )
  5583. mgsl_trace_block(info,Buffer, min_t(int, BufferSize, DMABUFFERSIZE), 1);
  5584. if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
  5585. /* set CMR:13 to start transmit when
  5586. * next GoAhead (abort) is received
  5587. */
  5588. info->cmr_value |= BIT13;
  5589. }
  5590. /* begin loading the frame in the next available tx dma
  5591. * buffer, remember it's starting location for setting
  5592. * up tx dma operation
  5593. */
  5594. i = info->current_tx_buffer;
  5595. info->start_tx_dma_buffer = i;
  5596. /* Setup the status and RCC (Frame Size) fields of the 1st */
  5597. /* buffer entry in the transmit DMA buffer list. */
  5598. info->tx_buffer_list[i].status = info->cmr_value & 0xf000;
  5599. info->tx_buffer_list[i].rcc = BufferSize;
  5600. info->tx_buffer_list[i].count = BufferSize;
  5601. /* Copy frame data from 1st source buffer to the DMA buffers. */
  5602. /* The frame data may span multiple DMA buffers. */
  5603. while( BufferSize ){
  5604. /* Get a pointer to next DMA buffer entry. */
  5605. pBufEntry = &info->tx_buffer_list[i++];
  5606. if ( i == info->tx_buffer_count )
  5607. i=0;
  5608. /* Calculate the number of bytes that can be copied from */
  5609. /* the source buffer to this DMA buffer. */
  5610. if ( BufferSize > DMABUFFERSIZE )
  5611. Copycount = DMABUFFERSIZE;
  5612. else
  5613. Copycount = BufferSize;
  5614. /* Actually copy data from source buffer to DMA buffer. */
  5615. /* Also set the data count for this individual DMA buffer. */
  5616. mgsl_load_pci_memory(pBufEntry->virt_addr, Buffer,Copycount);
  5617. pBufEntry->count = Copycount;
  5618. /* Advance source pointer and reduce remaining data count. */
  5619. Buffer += Copycount;
  5620. BufferSize -= Copycount;
  5621. ++info->tx_dma_buffers_used;
  5622. }
  5623. /* remember next available tx dma buffer */
  5624. info->current_tx_buffer = i;
  5625. } /* end of mgsl_load_tx_dma_buffer() */
  5626. /*
  5627. * mgsl_register_test()
  5628. *
  5629. * Performs a register test of the 16C32.
  5630. *
  5631. * Arguments: info pointer to device instance data
  5632. * Return Value: true if test passed, otherwise false
  5633. */
  5634. static bool mgsl_register_test( struct mgsl_struct *info )
  5635. {
  5636. static unsigned short BitPatterns[] =
  5637. { 0x0000, 0xffff, 0xaaaa, 0x5555, 0x1234, 0x6969, 0x9696, 0x0f0f };
  5638. static unsigned int Patterncount = ARRAY_SIZE(BitPatterns);
  5639. unsigned int i;
  5640. bool rc = true;
  5641. unsigned long flags;
  5642. spin_lock_irqsave(&info->irq_spinlock,flags);
  5643. usc_reset(info);
  5644. /* Verify the reset state of some registers. */
  5645. if ( (usc_InReg( info, SICR ) != 0) ||
  5646. (usc_InReg( info, IVR ) != 0) ||
  5647. (usc_InDmaReg( info, DIVR ) != 0) ){
  5648. rc = false;
  5649. }
  5650. if ( rc ){
  5651. /* Write bit patterns to various registers but do it out of */
  5652. /* sync, then read back and verify values. */
  5653. for ( i = 0 ; i < Patterncount ; i++ ) {
  5654. usc_OutReg( info, TC0R, BitPatterns[i] );
  5655. usc_OutReg( info, TC1R, BitPatterns[(i+1)%Patterncount] );
  5656. usc_OutReg( info, TCLR, BitPatterns[(i+2)%Patterncount] );
  5657. usc_OutReg( info, RCLR, BitPatterns[(i+3)%Patterncount] );
  5658. usc_OutReg( info, RSR, BitPatterns[(i+4)%Patterncount] );
  5659. usc_OutDmaReg( info, TBCR, BitPatterns[(i+5)%Patterncount] );
  5660. if ( (usc_InReg( info, TC0R ) != BitPatterns[i]) ||
  5661. (usc_InReg( info, TC1R ) != BitPatterns[(i+1)%Patterncount]) ||
  5662. (usc_InReg( info, TCLR ) != BitPatterns[(i+2)%Patterncount]) ||
  5663. (usc_InReg( info, RCLR ) != BitPatterns[(i+3)%Patterncount]) ||
  5664. (usc_InReg( info, RSR ) != BitPatterns[(i+4)%Patterncount]) ||
  5665. (usc_InDmaReg( info, TBCR ) != BitPatterns[(i+5)%Patterncount]) ){
  5666. rc = false;
  5667. break;
  5668. }
  5669. }
  5670. }
  5671. usc_reset(info);
  5672. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  5673. return rc;
  5674. } /* end of mgsl_register_test() */
  5675. /* mgsl_irq_test() Perform interrupt test of the 16C32.
  5676. *
  5677. * Arguments: info pointer to device instance data
  5678. * Return Value: true if test passed, otherwise false
  5679. */
  5680. static bool mgsl_irq_test( struct mgsl_struct *info )
  5681. {
  5682. unsigned long EndTime;
  5683. unsigned long flags;
  5684. spin_lock_irqsave(&info->irq_spinlock,flags);
  5685. usc_reset(info);
  5686. /*
  5687. * Setup 16C32 to interrupt on TxC pin (14MHz clock) transition.
  5688. * The ISR sets irq_occurred to true.
  5689. */
  5690. info->irq_occurred = false;
  5691. /* Enable INTEN gate for ISA adapter (Port 6, Bit12) */
  5692. /* Enable INTEN (Port 6, Bit12) */
  5693. /* This connects the IRQ request signal to the ISA bus */
  5694. /* on the ISA adapter. This has no effect for the PCI adapter */
  5695. usc_OutReg( info, PCR, (unsigned short)((usc_InReg(info, PCR) | BIT13) & ~BIT12) );
  5696. usc_EnableMasterIrqBit(info);
  5697. usc_EnableInterrupts(info, IO_PIN);
  5698. usc_ClearIrqPendingBits(info, IO_PIN);
  5699. usc_UnlatchIostatusBits(info, MISCSTATUS_TXC_LATCHED);
  5700. usc_EnableStatusIrqs(info, SICR_TXC_ACTIVE + SICR_TXC_INACTIVE);
  5701. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  5702. EndTime=100;
  5703. while( EndTime-- && !info->irq_occurred ) {
  5704. msleep_interruptible(10);
  5705. }
  5706. spin_lock_irqsave(&info->irq_spinlock,flags);
  5707. usc_reset(info);
  5708. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  5709. return info->irq_occurred;
  5710. } /* end of mgsl_irq_test() */
  5711. /* mgsl_dma_test()
  5712. *
  5713. * Perform a DMA test of the 16C32. A small frame is
  5714. * transmitted via DMA from a transmit buffer to a receive buffer
  5715. * using single buffer DMA mode.
  5716. *
  5717. * Arguments: info pointer to device instance data
  5718. * Return Value: true if test passed, otherwise false
  5719. */
  5720. static bool mgsl_dma_test( struct mgsl_struct *info )
  5721. {
  5722. unsigned short FifoLevel;
  5723. unsigned long phys_addr;
  5724. unsigned int FrameSize;
  5725. unsigned int i;
  5726. char *TmpPtr;
  5727. bool rc = true;
  5728. unsigned short status=0;
  5729. unsigned long EndTime;
  5730. unsigned long flags;
  5731. MGSL_PARAMS tmp_params;
  5732. /* save current port options */
  5733. memcpy(&tmp_params,&info->params,sizeof(MGSL_PARAMS));
  5734. /* load default port options */
  5735. memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
  5736. #define TESTFRAMESIZE 40
  5737. spin_lock_irqsave(&info->irq_spinlock,flags);
  5738. /* setup 16C32 for SDLC DMA transfer mode */
  5739. usc_reset(info);
  5740. usc_set_sdlc_mode(info);
  5741. usc_enable_loopback(info,1);
  5742. /* Reprogram the RDMR so that the 16C32 does NOT clear the count
  5743. * field of the buffer entry after fetching buffer address. This
  5744. * way we can detect a DMA failure for a DMA read (which should be
  5745. * non-destructive to system memory) before we try and write to
  5746. * memory (where a failure could corrupt system memory).
  5747. */
  5748. /* Receive DMA mode Register (RDMR)
  5749. *
  5750. * <15..14> 11 DMA mode = Linked List Buffer mode
  5751. * <13> 1 RSBinA/L = store Rx status Block in List entry
  5752. * <12> 0 1 = Clear count of List Entry after fetching
  5753. * <11..10> 00 Address mode = Increment
  5754. * <9> 1 Terminate Buffer on RxBound
  5755. * <8> 0 Bus Width = 16bits
  5756. * <7..0> ? status Bits (write as 0s)
  5757. *
  5758. * 1110 0010 0000 0000 = 0xe200
  5759. */
  5760. usc_OutDmaReg( info, RDMR, 0xe200 );
  5761. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  5762. /* SETUP TRANSMIT AND RECEIVE DMA BUFFERS */
  5763. FrameSize = TESTFRAMESIZE;
  5764. /* setup 1st transmit buffer entry: */
  5765. /* with frame size and transmit control word */
  5766. info->tx_buffer_list[0].count = FrameSize;
  5767. info->tx_buffer_list[0].rcc = FrameSize;
  5768. info->tx_buffer_list[0].status = 0x4000;
  5769. /* build a transmit frame in 1st transmit DMA buffer */
  5770. TmpPtr = info->tx_buffer_list[0].virt_addr;
  5771. for (i = 0; i < FrameSize; i++ )
  5772. *TmpPtr++ = i;
  5773. /* setup 1st receive buffer entry: */
  5774. /* clear status, set max receive buffer size */
  5775. info->rx_buffer_list[0].status = 0;
  5776. info->rx_buffer_list[0].count = FrameSize + 4;
  5777. /* zero out the 1st receive buffer */
  5778. memset( info->rx_buffer_list[0].virt_addr, 0, FrameSize + 4 );
  5779. /* Set count field of next buffer entries to prevent */
  5780. /* 16C32 from using buffers after the 1st one. */
  5781. info->tx_buffer_list[1].count = 0;
  5782. info->rx_buffer_list[1].count = 0;
  5783. /***************************/
  5784. /* Program 16C32 receiver. */
  5785. /***************************/
  5786. spin_lock_irqsave(&info->irq_spinlock,flags);
  5787. /* setup DMA transfers */
  5788. usc_RTCmd( info, RTCmd_PurgeRxFifo );
  5789. /* program 16C32 receiver with physical address of 1st DMA buffer entry */
  5790. phys_addr = info->rx_buffer_list[0].phys_entry;
  5791. usc_OutDmaReg( info, NRARL, (unsigned short)phys_addr );
  5792. usc_OutDmaReg( info, NRARU, (unsigned short)(phys_addr >> 16) );
  5793. /* Clear the Rx DMA status bits (read RDMR) and start channel */
  5794. usc_InDmaReg( info, RDMR );
  5795. usc_DmaCmd( info, DmaCmd_InitRxChannel );
  5796. /* Enable Receiver (RMR <1..0> = 10) */
  5797. usc_OutReg( info, RMR, (unsigned short)((usc_InReg(info, RMR) & 0xfffc) | 0x0002) );
  5798. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  5799. /*************************************************************/
  5800. /* WAIT FOR RECEIVER TO DMA ALL PARAMETERS FROM BUFFER ENTRY */
  5801. /*************************************************************/
  5802. /* Wait 100ms for interrupt. */
  5803. EndTime = jiffies + msecs_to_jiffies(100);
  5804. for(;;) {
  5805. if (time_after(jiffies, EndTime)) {
  5806. rc = false;
  5807. break;
  5808. }
  5809. spin_lock_irqsave(&info->irq_spinlock,flags);
  5810. status = usc_InDmaReg( info, RDMR );
  5811. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  5812. if ( !(status & BIT4) && (status & BIT5) ) {
  5813. /* INITG (BIT 4) is inactive (no entry read in progress) AND */
  5814. /* BUSY (BIT 5) is active (channel still active). */
  5815. /* This means the buffer entry read has completed. */
  5816. break;
  5817. }
  5818. }
  5819. /******************************/
  5820. /* Program 16C32 transmitter. */
  5821. /******************************/
  5822. spin_lock_irqsave(&info->irq_spinlock,flags);
  5823. /* Program the Transmit Character Length Register (TCLR) */
  5824. /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
  5825. usc_OutReg( info, TCLR, (unsigned short)info->tx_buffer_list[0].count );
  5826. usc_RTCmd( info, RTCmd_PurgeTxFifo );
  5827. /* Program the address of the 1st DMA Buffer Entry in linked list */
  5828. phys_addr = info->tx_buffer_list[0].phys_entry;
  5829. usc_OutDmaReg( info, NTARL, (unsigned short)phys_addr );
  5830. usc_OutDmaReg( info, NTARU, (unsigned short)(phys_addr >> 16) );
  5831. /* unlatch Tx status bits, and start transmit channel. */
  5832. usc_OutReg( info, TCSR, (unsigned short)(( usc_InReg(info, TCSR) & 0x0f00) | 0xfa) );
  5833. usc_DmaCmd( info, DmaCmd_InitTxChannel );
  5834. /* wait for DMA controller to fill transmit FIFO */
  5835. usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
  5836. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  5837. /**********************************/
  5838. /* WAIT FOR TRANSMIT FIFO TO FILL */
  5839. /**********************************/
  5840. /* Wait 100ms */
  5841. EndTime = jiffies + msecs_to_jiffies(100);
  5842. for(;;) {
  5843. if (time_after(jiffies, EndTime)) {
  5844. rc = false;
  5845. break;
  5846. }
  5847. spin_lock_irqsave(&info->irq_spinlock,flags);
  5848. FifoLevel = usc_InReg(info, TICR) >> 8;
  5849. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  5850. if ( FifoLevel < 16 )
  5851. break;
  5852. else
  5853. if ( FrameSize < 32 ) {
  5854. /* This frame is smaller than the entire transmit FIFO */
  5855. /* so wait for the entire frame to be loaded. */
  5856. if ( FifoLevel <= (32 - FrameSize) )
  5857. break;
  5858. }
  5859. }
  5860. if ( rc )
  5861. {
  5862. /* Enable 16C32 transmitter. */
  5863. spin_lock_irqsave(&info->irq_spinlock,flags);
  5864. /* Transmit mode Register (TMR), <1..0> = 10, Enable Transmitter */
  5865. usc_TCmd( info, TCmd_SendFrame );
  5866. usc_OutReg( info, TMR, (unsigned short)((usc_InReg(info, TMR) & 0xfffc) | 0x0002) );
  5867. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  5868. /******************************/
  5869. /* WAIT FOR TRANSMIT COMPLETE */
  5870. /******************************/
  5871. /* Wait 100ms */
  5872. EndTime = jiffies + msecs_to_jiffies(100);
  5873. /* While timer not expired wait for transmit complete */
  5874. spin_lock_irqsave(&info->irq_spinlock,flags);
  5875. status = usc_InReg( info, TCSR );
  5876. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  5877. while ( !(status & (BIT6 | BIT5 | BIT4 | BIT2 | BIT1)) ) {
  5878. if (time_after(jiffies, EndTime)) {
  5879. rc = false;
  5880. break;
  5881. }
  5882. spin_lock_irqsave(&info->irq_spinlock,flags);
  5883. status = usc_InReg( info, TCSR );
  5884. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  5885. }
  5886. }
  5887. if ( rc ){
  5888. /* CHECK FOR TRANSMIT ERRORS */
  5889. if ( status & (BIT5 | BIT1) )
  5890. rc = false;
  5891. }
  5892. if ( rc ) {
  5893. /* WAIT FOR RECEIVE COMPLETE */
  5894. /* Wait 100ms */
  5895. EndTime = jiffies + msecs_to_jiffies(100);
  5896. /* Wait for 16C32 to write receive status to buffer entry. */
  5897. status=info->rx_buffer_list[0].status;
  5898. while ( status == 0 ) {
  5899. if (time_after(jiffies, EndTime)) {
  5900. rc = false;
  5901. break;
  5902. }
  5903. status=info->rx_buffer_list[0].status;
  5904. }
  5905. }
  5906. if ( rc ) {
  5907. /* CHECK FOR RECEIVE ERRORS */
  5908. status = info->rx_buffer_list[0].status;
  5909. if ( status & (BIT8 | BIT3 | BIT1) ) {
  5910. /* receive error has occurred */
  5911. rc = false;
  5912. } else {
  5913. if ( memcmp( info->tx_buffer_list[0].virt_addr ,
  5914. info->rx_buffer_list[0].virt_addr, FrameSize ) ){
  5915. rc = false;
  5916. }
  5917. }
  5918. }
  5919. spin_lock_irqsave(&info->irq_spinlock,flags);
  5920. usc_reset( info );
  5921. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  5922. /* restore current port options */
  5923. memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
  5924. return rc;
  5925. } /* end of mgsl_dma_test() */
  5926. /* mgsl_adapter_test()
  5927. *
  5928. * Perform the register, IRQ, and DMA tests for the 16C32.
  5929. *
  5930. * Arguments: info pointer to device instance data
  5931. * Return Value: 0 if success, otherwise -ENODEV
  5932. */
  5933. static int mgsl_adapter_test( struct mgsl_struct *info )
  5934. {
  5935. if ( debug_level >= DEBUG_LEVEL_INFO )
  5936. printk( "%s(%d):Testing device %s\n",
  5937. __FILE__,__LINE__,info->device_name );
  5938. if ( !mgsl_register_test( info ) ) {
  5939. info->init_error = DiagStatus_AddressFailure;
  5940. printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
  5941. __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );
  5942. return -ENODEV;
  5943. }
  5944. if ( !mgsl_irq_test( info ) ) {
  5945. info->init_error = DiagStatus_IrqFailure;
  5946. printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
  5947. __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
  5948. return -ENODEV;
  5949. }
  5950. if ( !mgsl_dma_test( info ) ) {
  5951. info->init_error = DiagStatus_DmaFailure;
  5952. printk( "%s(%d):DMA test failure for device %s DMA=%d\n",
  5953. __FILE__,__LINE__,info->device_name, (unsigned short)(info->dma_level) );
  5954. return -ENODEV;
  5955. }
  5956. if ( debug_level >= DEBUG_LEVEL_INFO )
  5957. printk( "%s(%d):device %s passed diagnostics\n",
  5958. __FILE__,__LINE__,info->device_name );
  5959. return 0;
  5960. } /* end of mgsl_adapter_test() */
  5961. /* mgsl_memory_test()
  5962. *
  5963. * Test the shared memory on a PCI adapter.
  5964. *
  5965. * Arguments: info pointer to device instance data
  5966. * Return Value: true if test passed, otherwise false
  5967. */
  5968. static bool mgsl_memory_test( struct mgsl_struct *info )
  5969. {
  5970. static unsigned long BitPatterns[] =
  5971. { 0x0, 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
  5972. unsigned long Patterncount = ARRAY_SIZE(BitPatterns);
  5973. unsigned long i;
  5974. unsigned long TestLimit = SHARED_MEM_ADDRESS_SIZE/sizeof(unsigned long);
  5975. unsigned long * TestAddr;
  5976. TestAddr = (unsigned long *)info->memory_base;
  5977. /* Test data lines with test pattern at one location. */
  5978. for ( i = 0 ; i < Patterncount ; i++ ) {
  5979. *TestAddr = BitPatterns[i];
  5980. if ( *TestAddr != BitPatterns[i] )
  5981. return false;
  5982. }
  5983. /* Test address lines with incrementing pattern over */
  5984. /* entire address range. */
  5985. for ( i = 0 ; i < TestLimit ; i++ ) {
  5986. *TestAddr = i * 4;
  5987. TestAddr++;
  5988. }
  5989. TestAddr = (unsigned long *)info->memory_base;
  5990. for ( i = 0 ; i < TestLimit ; i++ ) {
  5991. if ( *TestAddr != i * 4 )
  5992. return false;
  5993. TestAddr++;
  5994. }
  5995. memset( info->memory_base, 0, SHARED_MEM_ADDRESS_SIZE );
  5996. return true;
  5997. } /* End Of mgsl_memory_test() */
  5998. /* mgsl_load_pci_memory()
  5999. *
  6000. * Load a large block of data into the PCI shared memory.
  6001. * Use this instead of memcpy() or memmove() to move data
  6002. * into the PCI shared memory.
  6003. *
  6004. * Notes:
  6005. *
  6006. * This function prevents the PCI9050 interface chip from hogging
  6007. * the adapter local bus, which can starve the 16C32 by preventing
  6008. * 16C32 bus master cycles.
  6009. *
  6010. * The PCI9050 documentation says that the 9050 will always release
  6011. * control of the local bus after completing the current read
  6012. * or write operation.
  6013. *
  6014. * It appears that as long as the PCI9050 write FIFO is full, the
  6015. * PCI9050 treats all of the writes as a single burst transaction
  6016. * and will not release the bus. This causes DMA latency problems
  6017. * at high speeds when copying large data blocks to the shared
  6018. * memory.
  6019. *
  6020. * This function in effect, breaks the a large shared memory write
  6021. * into multiple transations by interleaving a shared memory read
  6022. * which will flush the write FIFO and 'complete' the write
  6023. * transation. This allows any pending DMA request to gain control
  6024. * of the local bus in a timely fasion.
  6025. *
  6026. * Arguments:
  6027. *
  6028. * TargetPtr pointer to target address in PCI shared memory
  6029. * SourcePtr pointer to source buffer for data
  6030. * count count in bytes of data to copy
  6031. *
  6032. * Return Value: None
  6033. */
  6034. static void mgsl_load_pci_memory( char* TargetPtr, const char* SourcePtr,
  6035. unsigned short count )
  6036. {
  6037. /* 16 32-bit writes @ 60ns each = 960ns max latency on local bus */
  6038. #define PCI_LOAD_INTERVAL 64
  6039. unsigned short Intervalcount = count / PCI_LOAD_INTERVAL;
  6040. unsigned short Index;
  6041. unsigned long Dummy;
  6042. for ( Index = 0 ; Index < Intervalcount ; Index++ )
  6043. {
  6044. memcpy(TargetPtr, SourcePtr, PCI_LOAD_INTERVAL);
  6045. Dummy = *((volatile unsigned long *)TargetPtr);
  6046. TargetPtr += PCI_LOAD_INTERVAL;
  6047. SourcePtr += PCI_LOAD_INTERVAL;
  6048. }
  6049. memcpy( TargetPtr, SourcePtr, count % PCI_LOAD_INTERVAL );
  6050. } /* End Of mgsl_load_pci_memory() */
  6051. static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit)
  6052. {
  6053. int i;
  6054. int linecount;
  6055. if (xmit)
  6056. printk("%s tx data:\n",info->device_name);
  6057. else
  6058. printk("%s rx data:\n",info->device_name);
  6059. while(count) {
  6060. if (count > 16)
  6061. linecount = 16;
  6062. else
  6063. linecount = count;
  6064. for(i=0;i<linecount;i++)
  6065. printk("%02X ",(unsigned char)data[i]);
  6066. for(;i<17;i++)
  6067. printk(" ");
  6068. for(i=0;i<linecount;i++) {
  6069. if (data[i]>=040 && data[i]<=0176)
  6070. printk("%c",data[i]);
  6071. else
  6072. printk(".");
  6073. }
  6074. printk("\n");
  6075. data += linecount;
  6076. count -= linecount;
  6077. }
  6078. } /* end of mgsl_trace_block() */
  6079. /* mgsl_tx_timeout()
  6080. *
  6081. * called when HDLC frame times out
  6082. * update stats and do tx completion processing
  6083. *
  6084. * Arguments: context pointer to device instance data
  6085. * Return Value: None
  6086. */
  6087. static void mgsl_tx_timeout(struct timer_list *t)
  6088. {
  6089. struct mgsl_struct *info = from_timer(info, t, tx_timer);
  6090. unsigned long flags;
  6091. if ( debug_level >= DEBUG_LEVEL_INFO )
  6092. printk( "%s(%d):mgsl_tx_timeout(%s)\n",
  6093. __FILE__,__LINE__,info->device_name);
  6094. if(info->tx_active &&
  6095. (info->params.mode == MGSL_MODE_HDLC ||
  6096. info->params.mode == MGSL_MODE_RAW) ) {
  6097. info->icount.txtimeout++;
  6098. }
  6099. spin_lock_irqsave(&info->irq_spinlock,flags);
  6100. info->tx_active = false;
  6101. info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
  6102. if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
  6103. usc_loopmode_cancel_transmit( info );
  6104. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  6105. #if SYNCLINK_GENERIC_HDLC
  6106. if (info->netcount)
  6107. hdlcdev_tx_done(info);
  6108. else
  6109. #endif
  6110. mgsl_bh_transmit(info);
  6111. } /* end of mgsl_tx_timeout() */
  6112. /* signal that there are no more frames to send, so that
  6113. * line is 'released' by echoing RxD to TxD when current
  6114. * transmission is complete (or immediately if no tx in progress).
  6115. */
  6116. static int mgsl_loopmode_send_done( struct mgsl_struct * info )
  6117. {
  6118. unsigned long flags;
  6119. spin_lock_irqsave(&info->irq_spinlock,flags);
  6120. if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
  6121. if (info->tx_active)
  6122. info->loopmode_send_done_requested = true;
  6123. else
  6124. usc_loopmode_send_done(info);
  6125. }
  6126. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  6127. return 0;
  6128. }
  6129. /* release the line by echoing RxD to TxD
  6130. * upon completion of a transmit frame
  6131. */
  6132. static void usc_loopmode_send_done( struct mgsl_struct * info )
  6133. {
  6134. info->loopmode_send_done_requested = false;
  6135. /* clear CMR:13 to 0 to start echoing RxData to TxData */
  6136. info->cmr_value &= ~BIT13;
  6137. usc_OutReg(info, CMR, info->cmr_value);
  6138. }
  6139. /* abort a transmit in progress while in HDLC LoopMode
  6140. */
  6141. static void usc_loopmode_cancel_transmit( struct mgsl_struct * info )
  6142. {
  6143. /* reset tx dma channel and purge TxFifo */
  6144. usc_RTCmd( info, RTCmd_PurgeTxFifo );
  6145. usc_DmaCmd( info, DmaCmd_ResetTxChannel );
  6146. usc_loopmode_send_done( info );
  6147. }
  6148. /* for HDLC/SDLC LoopMode, setting CMR:13 after the transmitter is enabled
  6149. * is an Insert Into Loop action. Upon receipt of a GoAhead sequence (RxAbort)
  6150. * we must clear CMR:13 to begin repeating TxData to RxData
  6151. */
  6152. static void usc_loopmode_insert_request( struct mgsl_struct * info )
  6153. {
  6154. info->loopmode_insert_requested = true;
  6155. /* enable RxAbort irq. On next RxAbort, clear CMR:13 to
  6156. * begin repeating TxData on RxData (complete insertion)
  6157. */
  6158. usc_OutReg( info, RICR,
  6159. (usc_InReg( info, RICR ) | RXSTATUS_ABORT_RECEIVED ) );
  6160. /* set CMR:13 to insert into loop on next GoAhead (RxAbort) */
  6161. info->cmr_value |= BIT13;
  6162. usc_OutReg(info, CMR, info->cmr_value);
  6163. }
  6164. /* return 1 if station is inserted into the loop, otherwise 0
  6165. */
  6166. static int usc_loopmode_active( struct mgsl_struct * info)
  6167. {
  6168. return usc_InReg( info, CCSR ) & BIT7 ? 1 : 0 ;
  6169. }
  6170. #if SYNCLINK_GENERIC_HDLC
  6171. /**
  6172. * hdlcdev_attach - called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
  6173. * @dev: pointer to network device structure
  6174. * @encoding: serial encoding setting
  6175. * @parity: FCS setting
  6176. *
  6177. * Set encoding and frame check sequence (FCS) options.
  6178. *
  6179. * Return: 0 if success, otherwise error code
  6180. */
  6181. static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
  6182. unsigned short parity)
  6183. {
  6184. struct mgsl_struct *info = dev_to_port(dev);
  6185. unsigned char new_encoding;
  6186. unsigned short new_crctype;
  6187. /* return error if TTY interface open */
  6188. if (info->port.count)
  6189. return -EBUSY;
  6190. switch (encoding)
  6191. {
  6192. case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
  6193. case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
  6194. case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
  6195. case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
  6196. case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
  6197. default: return -EINVAL;
  6198. }
  6199. switch (parity)
  6200. {
  6201. case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
  6202. case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
  6203. case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
  6204. default: return -EINVAL;
  6205. }
  6206. info->params.encoding = new_encoding;
  6207. info->params.crc_type = new_crctype;
  6208. /* if network interface up, reprogram hardware */
  6209. if (info->netcount)
  6210. mgsl_program_hw(info);
  6211. return 0;
  6212. }
  6213. /**
  6214. * hdlcdev_xmit - called by generic HDLC layer to send a frame
  6215. * @skb: socket buffer containing HDLC frame
  6216. * @dev: pointer to network device structure
  6217. */
  6218. static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
  6219. struct net_device *dev)
  6220. {
  6221. struct mgsl_struct *info = dev_to_port(dev);
  6222. unsigned long flags;
  6223. if (debug_level >= DEBUG_LEVEL_INFO)
  6224. printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
  6225. /* stop sending until this frame completes */
  6226. netif_stop_queue(dev);
  6227. /* copy data to device buffers */
  6228. info->xmit_cnt = skb->len;
  6229. mgsl_load_tx_dma_buffer(info, skb->data, skb->len);
  6230. /* update network statistics */
  6231. dev->stats.tx_packets++;
  6232. dev->stats.tx_bytes += skb->len;
  6233. /* done with socket buffer, so free it */
  6234. dev_kfree_skb(skb);
  6235. /* save start time for transmit timeout detection */
  6236. netif_trans_update(dev);
  6237. /* start hardware transmitter if necessary */
  6238. spin_lock_irqsave(&info->irq_spinlock,flags);
  6239. if (!info->tx_active)
  6240. usc_start_transmitter(info);
  6241. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  6242. return NETDEV_TX_OK;
  6243. }
  6244. /**
  6245. * hdlcdev_open - called by network layer when interface enabled
  6246. * @dev: pointer to network device structure
  6247. *
  6248. * Claim resources and initialize hardware.
  6249. *
  6250. * Return: 0 if success, otherwise error code
  6251. */
  6252. static int hdlcdev_open(struct net_device *dev)
  6253. {
  6254. struct mgsl_struct *info = dev_to_port(dev);
  6255. int rc;
  6256. unsigned long flags;
  6257. if (debug_level >= DEBUG_LEVEL_INFO)
  6258. printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
  6259. /* generic HDLC layer open processing */
  6260. rc = hdlc_open(dev);
  6261. if (rc)
  6262. return rc;
  6263. /* arbitrate between network and tty opens */
  6264. spin_lock_irqsave(&info->netlock, flags);
  6265. if (info->port.count != 0 || info->netcount != 0) {
  6266. printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
  6267. spin_unlock_irqrestore(&info->netlock, flags);
  6268. return -EBUSY;
  6269. }
  6270. info->netcount=1;
  6271. spin_unlock_irqrestore(&info->netlock, flags);
  6272. /* claim resources and init adapter */
  6273. if ((rc = startup(info)) != 0) {
  6274. spin_lock_irqsave(&info->netlock, flags);
  6275. info->netcount=0;
  6276. spin_unlock_irqrestore(&info->netlock, flags);
  6277. return rc;
  6278. }
  6279. /* assert RTS and DTR, apply hardware settings */
  6280. info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
  6281. mgsl_program_hw(info);
  6282. /* enable network layer transmit */
  6283. netif_trans_update(dev);
  6284. netif_start_queue(dev);
  6285. /* inform generic HDLC layer of current DCD status */
  6286. spin_lock_irqsave(&info->irq_spinlock, flags);
  6287. usc_get_serial_signals(info);
  6288. spin_unlock_irqrestore(&info->irq_spinlock, flags);
  6289. if (info->serial_signals & SerialSignal_DCD)
  6290. netif_carrier_on(dev);
  6291. else
  6292. netif_carrier_off(dev);
  6293. return 0;
  6294. }
  6295. /**
  6296. * hdlcdev_close - called by network layer when interface is disabled
  6297. * @dev: pointer to network device structure
  6298. *
  6299. * Shutdown hardware and release resources.
  6300. *
  6301. * Return: 0 if success, otherwise error code
  6302. */
  6303. static int hdlcdev_close(struct net_device *dev)
  6304. {
  6305. struct mgsl_struct *info = dev_to_port(dev);
  6306. unsigned long flags;
  6307. if (debug_level >= DEBUG_LEVEL_INFO)
  6308. printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
  6309. netif_stop_queue(dev);
  6310. /* shutdown adapter and release resources */
  6311. shutdown(info);
  6312. hdlc_close(dev);
  6313. spin_lock_irqsave(&info->netlock, flags);
  6314. info->netcount=0;
  6315. spin_unlock_irqrestore(&info->netlock, flags);
  6316. return 0;
  6317. }
  6318. /**
  6319. * hdlcdev_ioctl - called by network layer to process IOCTL call to network device
  6320. * @dev: pointer to network device structure
  6321. * @ifr: pointer to network interface request structure
  6322. * @cmd: IOCTL command code
  6323. *
  6324. * Return: 0 if success, otherwise error code
  6325. */
  6326. static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  6327. {
  6328. const size_t size = sizeof(sync_serial_settings);
  6329. sync_serial_settings new_line;
  6330. sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
  6331. struct mgsl_struct *info = dev_to_port(dev);
  6332. unsigned int flags;
  6333. if (debug_level >= DEBUG_LEVEL_INFO)
  6334. printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
  6335. /* return error if TTY interface open */
  6336. if (info->port.count)
  6337. return -EBUSY;
  6338. if (cmd != SIOCWANDEV)
  6339. return hdlc_ioctl(dev, ifr, cmd);
  6340. switch(ifr->ifr_settings.type) {
  6341. case IF_GET_IFACE: /* return current sync_serial_settings */
  6342. ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
  6343. if (ifr->ifr_settings.size < size) {
  6344. ifr->ifr_settings.size = size; /* data size wanted */
  6345. return -ENOBUFS;
  6346. }
  6347. flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  6348. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  6349. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  6350. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
  6351. memset(&new_line, 0, sizeof(new_line));
  6352. switch (flags){
  6353. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
  6354. case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
  6355. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
  6356. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
  6357. default: new_line.clock_type = CLOCK_DEFAULT;
  6358. }
  6359. new_line.clock_rate = info->params.clock_speed;
  6360. new_line.loopback = info->params.loopback ? 1:0;
  6361. if (copy_to_user(line, &new_line, size))
  6362. return -EFAULT;
  6363. return 0;
  6364. case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
  6365. if(!capable(CAP_NET_ADMIN))
  6366. return -EPERM;
  6367. if (copy_from_user(&new_line, line, size))
  6368. return -EFAULT;
  6369. switch (new_line.clock_type)
  6370. {
  6371. case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
  6372. case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
  6373. case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
  6374. case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
  6375. case CLOCK_DEFAULT: flags = info->params.flags &
  6376. (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  6377. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  6378. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  6379. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
  6380. default: return -EINVAL;
  6381. }
  6382. if (new_line.loopback != 0 && new_line.loopback != 1)
  6383. return -EINVAL;
  6384. info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  6385. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  6386. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  6387. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
  6388. info->params.flags |= flags;
  6389. info->params.loopback = new_line.loopback;
  6390. if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
  6391. info->params.clock_speed = new_line.clock_rate;
  6392. else
  6393. info->params.clock_speed = 0;
  6394. /* if network interface up, reprogram hardware */
  6395. if (info->netcount)
  6396. mgsl_program_hw(info);
  6397. return 0;
  6398. default:
  6399. return hdlc_ioctl(dev, ifr, cmd);
  6400. }
  6401. }
  6402. /**
  6403. * hdlcdev_tx_timeout - called by network layer when transmit timeout is detected
  6404. *
  6405. * @dev: pointer to network device structure
  6406. */
  6407. static void hdlcdev_tx_timeout(struct net_device *dev, unsigned int txqueue)
  6408. {
  6409. struct mgsl_struct *info = dev_to_port(dev);
  6410. unsigned long flags;
  6411. if (debug_level >= DEBUG_LEVEL_INFO)
  6412. printk("hdlcdev_tx_timeout(%s)\n",dev->name);
  6413. dev->stats.tx_errors++;
  6414. dev->stats.tx_aborted_errors++;
  6415. spin_lock_irqsave(&info->irq_spinlock,flags);
  6416. usc_stop_transmitter(info);
  6417. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  6418. netif_wake_queue(dev);
  6419. }
  6420. /**
  6421. * hdlcdev_tx_done - called by device driver when transmit completes
  6422. * @info: pointer to device instance information
  6423. *
  6424. * Reenable network layer transmit if stopped.
  6425. */
  6426. static void hdlcdev_tx_done(struct mgsl_struct *info)
  6427. {
  6428. if (netif_queue_stopped(info->netdev))
  6429. netif_wake_queue(info->netdev);
  6430. }
  6431. /**
  6432. * hdlcdev_rx - called by device driver when frame received
  6433. * @info: pointer to device instance information
  6434. * @buf: pointer to buffer contianing frame data
  6435. * @size: count of data bytes in buf
  6436. *
  6437. * Pass frame to network layer.
  6438. */
  6439. static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size)
  6440. {
  6441. struct sk_buff *skb = dev_alloc_skb(size);
  6442. struct net_device *dev = info->netdev;
  6443. if (debug_level >= DEBUG_LEVEL_INFO)
  6444. printk("hdlcdev_rx(%s)\n", dev->name);
  6445. if (skb == NULL) {
  6446. printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
  6447. dev->name);
  6448. dev->stats.rx_dropped++;
  6449. return;
  6450. }
  6451. skb_put_data(skb, buf, size);
  6452. skb->protocol = hdlc_type_trans(skb, dev);
  6453. dev->stats.rx_packets++;
  6454. dev->stats.rx_bytes += size;
  6455. netif_rx(skb);
  6456. }
  6457. static const struct net_device_ops hdlcdev_ops = {
  6458. .ndo_open = hdlcdev_open,
  6459. .ndo_stop = hdlcdev_close,
  6460. .ndo_start_xmit = hdlc_start_xmit,
  6461. .ndo_do_ioctl = hdlcdev_ioctl,
  6462. .ndo_tx_timeout = hdlcdev_tx_timeout,
  6463. };
  6464. /**
  6465. * hdlcdev_init - called by device driver when adding device instance
  6466. * @info: pointer to device instance information
  6467. *
  6468. * Do generic HDLC initialization.
  6469. *
  6470. * Return: 0 if success, otherwise error code
  6471. */
  6472. static int hdlcdev_init(struct mgsl_struct *info)
  6473. {
  6474. int rc;
  6475. struct net_device *dev;
  6476. hdlc_device *hdlc;
  6477. /* allocate and initialize network and HDLC layer objects */
  6478. dev = alloc_hdlcdev(info);
  6479. if (!dev) {
  6480. printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
  6481. return -ENOMEM;
  6482. }
  6483. /* for network layer reporting purposes only */
  6484. dev->base_addr = info->io_base;
  6485. dev->irq = info->irq_level;
  6486. dev->dma = info->dma_level;
  6487. /* network layer callbacks and settings */
  6488. dev->netdev_ops = &hdlcdev_ops;
  6489. dev->watchdog_timeo = 10 * HZ;
  6490. dev->tx_queue_len = 50;
  6491. /* generic HDLC layer callbacks and settings */
  6492. hdlc = dev_to_hdlc(dev);
  6493. hdlc->attach = hdlcdev_attach;
  6494. hdlc->xmit = hdlcdev_xmit;
  6495. /* register objects with HDLC layer */
  6496. rc = register_hdlc_device(dev);
  6497. if (rc) {
  6498. printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
  6499. free_netdev(dev);
  6500. return rc;
  6501. }
  6502. info->netdev = dev;
  6503. return 0;
  6504. }
  6505. /**
  6506. * hdlcdev_exit - called by device driver when removing device instance
  6507. * @info: pointer to device instance information
  6508. *
  6509. * Do generic HDLC cleanup.
  6510. */
  6511. static void hdlcdev_exit(struct mgsl_struct *info)
  6512. {
  6513. unregister_hdlc_device(info->netdev);
  6514. free_netdev(info->netdev);
  6515. info->netdev = NULL;
  6516. }
  6517. #endif /* CONFIG_HDLC */
  6518. static int synclink_init_one (struct pci_dev *dev,
  6519. const struct pci_device_id *ent)
  6520. {
  6521. struct mgsl_struct *info;
  6522. if (pci_enable_device(dev)) {
  6523. printk("error enabling pci device %p\n", dev);
  6524. return -EIO;
  6525. }
  6526. info = mgsl_allocate_device();
  6527. if (!info) {
  6528. printk("can't allocate device instance data.\n");
  6529. return -EIO;
  6530. }
  6531. /* Copy user configuration info to device instance data */
  6532. info->io_base = pci_resource_start(dev, 2);
  6533. info->irq_level = dev->irq;
  6534. info->phys_memory_base = pci_resource_start(dev, 3);
  6535. /* Because veremap only works on page boundaries we must map
  6536. * a larger area than is actually implemented for the LCR
  6537. * memory range. We map a full page starting at the page boundary.
  6538. */
  6539. info->phys_lcr_base = pci_resource_start(dev, 0);
  6540. info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
  6541. info->phys_lcr_base &= ~(PAGE_SIZE-1);
  6542. info->io_addr_size = 8;
  6543. info->irq_flags = IRQF_SHARED;
  6544. if (dev->device == 0x0210) {
  6545. /* Version 1 PCI9030 based universal PCI adapter */
  6546. info->misc_ctrl_value = 0x007c4080;
  6547. info->hw_version = 1;
  6548. } else {
  6549. /* Version 0 PCI9050 based 5V PCI adapter
  6550. * A PCI9050 bug prevents reading LCR registers if
  6551. * LCR base address bit 7 is set. Maintain shadow
  6552. * value so we can write to LCR misc control reg.
  6553. */
  6554. info->misc_ctrl_value = 0x087e4546;
  6555. info->hw_version = 0;
  6556. }
  6557. mgsl_add_device(info);
  6558. return 0;
  6559. }
  6560. static void synclink_remove_one (struct pci_dev *dev)
  6561. {
  6562. }