rocket.c 92 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
  2. /*
  3. * RocketPort device driver for Linux
  4. *
  5. * Written by Theodore Ts'o, 1995, 1996, 1997, 1998, 1999, 2000.
  6. *
  7. * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003 by Comtrol, Inc.
  8. */
  9. /*
  10. * Kernel Synchronization:
  11. *
  12. * This driver has 2 kernel control paths - exception handlers (calls into the driver
  13. * from user mode) and the timer bottom half (tasklet). This is a polled driver, interrupts
  14. * are not used.
  15. *
  16. * Critical data:
  17. * - rp_table[], accessed through passed "info" pointers, is a global (static) array of
  18. * serial port state information and the xmit_buf circular buffer. Protected by
  19. * a per port spinlock.
  20. * - xmit_flags[], an array of ints indexed by line (port) number, indicating that there
  21. * is data to be transmitted. Protected by atomic bit operations.
  22. * - rp_num_ports, int indicating number of open ports, protected by atomic operations.
  23. *
  24. * rp_write() and rp_write_char() functions use a per port semaphore to protect against
  25. * simultaneous access to the same port by more than one process.
  26. */
  27. /****** Defines ******/
  28. #define ROCKET_PARANOIA_CHECK
  29. #define ROCKET_DISABLE_SIMUSAGE
  30. #undef ROCKET_SOFT_FLOW
  31. #undef ROCKET_DEBUG_OPEN
  32. #undef ROCKET_DEBUG_INTR
  33. #undef ROCKET_DEBUG_WRITE
  34. #undef ROCKET_DEBUG_FLOW
  35. #undef ROCKET_DEBUG_THROTTLE
  36. #undef ROCKET_DEBUG_WAIT_UNTIL_SENT
  37. #undef ROCKET_DEBUG_RECEIVE
  38. #undef ROCKET_DEBUG_HANGUP
  39. #undef REV_PCI_ORDER
  40. #undef ROCKET_DEBUG_IO
  41. #define POLL_PERIOD (HZ/100) /* Polling period .01 seconds (10ms) */
  42. /****** Kernel includes ******/
  43. #include <linux/module.h>
  44. #include <linux/errno.h>
  45. #include <linux/major.h>
  46. #include <linux/kernel.h>
  47. #include <linux/signal.h>
  48. #include <linux/slab.h>
  49. #include <linux/mm.h>
  50. #include <linux/sched.h>
  51. #include <linux/timer.h>
  52. #include <linux/interrupt.h>
  53. #include <linux/tty.h>
  54. #include <linux/tty_driver.h>
  55. #include <linux/tty_flip.h>
  56. #include <linux/serial.h>
  57. #include <linux/string.h>
  58. #include <linux/fcntl.h>
  59. #include <linux/ptrace.h>
  60. #include <linux/mutex.h>
  61. #include <linux/ioport.h>
  62. #include <linux/delay.h>
  63. #include <linux/completion.h>
  64. #include <linux/wait.h>
  65. #include <linux/pci.h>
  66. #include <linux/uaccess.h>
  67. #include <linux/atomic.h>
  68. #include <asm/unaligned.h>
  69. #include <linux/bitops.h>
  70. #include <linux/spinlock.h>
  71. #include <linux/init.h>
  72. /****** RocketPort includes ******/
  73. #include "rocket_int.h"
  74. #include "rocket.h"
  75. #define ROCKET_VERSION "2.09"
  76. #define ROCKET_DATE "12-June-2003"
  77. /****** RocketPort Local Variables ******/
  78. static void rp_do_poll(struct timer_list *unused);
  79. static struct tty_driver *rocket_driver;
  80. static struct rocket_version driver_version = {
  81. ROCKET_VERSION, ROCKET_DATE
  82. };
  83. static struct r_port *rp_table[MAX_RP_PORTS]; /* The main repository of serial port state information. */
  84. static unsigned int xmit_flags[NUM_BOARDS]; /* Bit significant, indicates port had data to transmit. */
  85. /* eg. Bit 0 indicates port 0 has xmit data, ... */
  86. static atomic_t rp_num_ports_open; /* Number of serial ports open */
  87. static DEFINE_TIMER(rocket_timer, rp_do_poll);
  88. static unsigned long board1; /* ISA addresses, retrieved from rocketport.conf */
  89. static unsigned long board2;
  90. static unsigned long board3;
  91. static unsigned long board4;
  92. static unsigned long controller;
  93. static bool support_low_speed;
  94. static unsigned long modem1;
  95. static unsigned long modem2;
  96. static unsigned long modem3;
  97. static unsigned long modem4;
  98. static unsigned long pc104_1[8];
  99. static unsigned long pc104_2[8];
  100. static unsigned long pc104_3[8];
  101. static unsigned long pc104_4[8];
  102. static unsigned long *pc104[4] = { pc104_1, pc104_2, pc104_3, pc104_4 };
  103. static int rp_baud_base[NUM_BOARDS]; /* Board config info (Someday make a per-board structure) */
  104. static unsigned long rcktpt_io_addr[NUM_BOARDS];
  105. static int rcktpt_type[NUM_BOARDS];
  106. static int is_PCI[NUM_BOARDS];
  107. static rocketModel_t rocketModel[NUM_BOARDS];
  108. static int max_board;
  109. static const struct tty_port_operations rocket_port_ops;
  110. /*
  111. * The following arrays define the interrupt bits corresponding to each AIOP.
  112. * These bits are different between the ISA and regular PCI boards and the
  113. * Universal PCI boards.
  114. */
  115. static Word_t aiop_intr_bits[AIOP_CTL_SIZE] = {
  116. AIOP_INTR_BIT_0,
  117. AIOP_INTR_BIT_1,
  118. AIOP_INTR_BIT_2,
  119. AIOP_INTR_BIT_3
  120. };
  121. #ifdef CONFIG_PCI
  122. static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = {
  123. UPCI_AIOP_INTR_BIT_0,
  124. UPCI_AIOP_INTR_BIT_1,
  125. UPCI_AIOP_INTR_BIT_2,
  126. UPCI_AIOP_INTR_BIT_3
  127. };
  128. #endif
  129. static Byte_t RData[RDATASIZE] = {
  130. 0x00, 0x09, 0xf6, 0x82,
  131. 0x02, 0x09, 0x86, 0xfb,
  132. 0x04, 0x09, 0x00, 0x0a,
  133. 0x06, 0x09, 0x01, 0x0a,
  134. 0x08, 0x09, 0x8a, 0x13,
  135. 0x0a, 0x09, 0xc5, 0x11,
  136. 0x0c, 0x09, 0x86, 0x85,
  137. 0x0e, 0x09, 0x20, 0x0a,
  138. 0x10, 0x09, 0x21, 0x0a,
  139. 0x12, 0x09, 0x41, 0xff,
  140. 0x14, 0x09, 0x82, 0x00,
  141. 0x16, 0x09, 0x82, 0x7b,
  142. 0x18, 0x09, 0x8a, 0x7d,
  143. 0x1a, 0x09, 0x88, 0x81,
  144. 0x1c, 0x09, 0x86, 0x7a,
  145. 0x1e, 0x09, 0x84, 0x81,
  146. 0x20, 0x09, 0x82, 0x7c,
  147. 0x22, 0x09, 0x0a, 0x0a
  148. };
  149. static Byte_t RRegData[RREGDATASIZE] = {
  150. 0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
  151. 0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
  152. 0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
  153. 0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
  154. 0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
  155. 0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
  156. 0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
  157. 0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
  158. 0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
  159. 0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
  160. 0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
  161. 0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
  162. 0x22, 0x09, 0x0a, 0x0a /* 30: Rx FIFO Enable */
  163. };
  164. static CONTROLLER_T sController[CTL_SIZE] = {
  165. {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
  166. {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
  167. {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
  168. {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
  169. {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
  170. {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
  171. {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
  172. {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}
  173. };
  174. static Byte_t sBitMapClrTbl[8] = {
  175. 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f
  176. };
  177. static Byte_t sBitMapSetTbl[8] = {
  178. 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
  179. };
  180. static int sClockPrescale = 0x14;
  181. /*
  182. * Line number is the ttySIx number (x), the Minor number. We
  183. * assign them sequentially, starting at zero. The following
  184. * array keeps track of the line number assigned to a given board/aiop/channel.
  185. */
  186. static unsigned char lineNumbers[MAX_RP_PORTS];
  187. static unsigned long nextLineNumber;
  188. /***** RocketPort Static Prototypes *********/
  189. static int __init init_ISA(int i);
  190. static void rp_wait_until_sent(struct tty_struct *tty, int timeout);
  191. static void rp_flush_buffer(struct tty_struct *tty);
  192. static unsigned char GetLineNumber(int ctrl, int aiop, int ch);
  193. static unsigned char SetLineNumber(int ctrl, int aiop, int ch);
  194. static void rp_start(struct tty_struct *tty);
  195. static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
  196. int ChanNum);
  197. static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
  198. static void sFlushRxFIFO(CHANNEL_T * ChP);
  199. static void sFlushTxFIFO(CHANNEL_T * ChP);
  200. static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
  201. static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
  202. static void sModemReset(CONTROLLER_T * CtlP, int chan, int on);
  203. static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on);
  204. static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
  205. static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
  206. ByteIO_t * AiopIOList, int AiopIOListSize,
  207. int IRQNum, Byte_t Frequency, int PeriodicOnly);
  208. static int sReadAiopID(ByteIO_t io);
  209. static int sReadAiopNumChan(WordIO_t io);
  210. MODULE_AUTHOR("Theodore Ts'o");
  211. MODULE_DESCRIPTION("Comtrol RocketPort driver");
  212. module_param_hw(board1, ulong, ioport, 0);
  213. MODULE_PARM_DESC(board1, "I/O port for (ISA) board #1");
  214. module_param_hw(board2, ulong, ioport, 0);
  215. MODULE_PARM_DESC(board2, "I/O port for (ISA) board #2");
  216. module_param_hw(board3, ulong, ioport, 0);
  217. MODULE_PARM_DESC(board3, "I/O port for (ISA) board #3");
  218. module_param_hw(board4, ulong, ioport, 0);
  219. MODULE_PARM_DESC(board4, "I/O port for (ISA) board #4");
  220. module_param_hw(controller, ulong, ioport, 0);
  221. MODULE_PARM_DESC(controller, "I/O port for (ISA) rocketport controller");
  222. module_param(support_low_speed, bool, 0);
  223. MODULE_PARM_DESC(support_low_speed, "1 means support 50 baud, 0 means support 460400 baud");
  224. module_param(modem1, ulong, 0);
  225. MODULE_PARM_DESC(modem1, "1 means (ISA) board #1 is a RocketModem");
  226. module_param(modem2, ulong, 0);
  227. MODULE_PARM_DESC(modem2, "1 means (ISA) board #2 is a RocketModem");
  228. module_param(modem3, ulong, 0);
  229. MODULE_PARM_DESC(modem3, "1 means (ISA) board #3 is a RocketModem");
  230. module_param(modem4, ulong, 0);
  231. MODULE_PARM_DESC(modem4, "1 means (ISA) board #4 is a RocketModem");
  232. module_param_array(pc104_1, ulong, NULL, 0);
  233. MODULE_PARM_DESC(pc104_1, "set interface types for ISA(PC104) board #1 (e.g. pc104_1=232,232,485,485,...");
  234. module_param_array(pc104_2, ulong, NULL, 0);
  235. MODULE_PARM_DESC(pc104_2, "set interface types for ISA(PC104) board #2 (e.g. pc104_2=232,232,485,485,...");
  236. module_param_array(pc104_3, ulong, NULL, 0);
  237. MODULE_PARM_DESC(pc104_3, "set interface types for ISA(PC104) board #3 (e.g. pc104_3=232,232,485,485,...");
  238. module_param_array(pc104_4, ulong, NULL, 0);
  239. MODULE_PARM_DESC(pc104_4, "set interface types for ISA(PC104) board #4 (e.g. pc104_4=232,232,485,485,...");
  240. static int __init rp_init(void);
  241. static void rp_cleanup_module(void);
  242. module_init(rp_init);
  243. module_exit(rp_cleanup_module);
  244. MODULE_LICENSE("Dual BSD/GPL");
  245. /*************************************************************************/
  246. /* Module code starts here */
  247. static inline int rocket_paranoia_check(struct r_port *info,
  248. const char *routine)
  249. {
  250. #ifdef ROCKET_PARANOIA_CHECK
  251. if (!info)
  252. return 1;
  253. if (info->magic != RPORT_MAGIC) {
  254. printk(KERN_WARNING "Warning: bad magic number for rocketport "
  255. "struct in %s\n", routine);
  256. return 1;
  257. }
  258. #endif
  259. return 0;
  260. }
  261. /* Serial port receive data function. Called (from timer poll) when an AIOPIC signals
  262. * that receive data is present on a serial port. Pulls data from FIFO, moves it into the
  263. * tty layer.
  264. */
  265. static void rp_do_receive(struct r_port *info, CHANNEL_t *cp,
  266. unsigned int ChanStatus)
  267. {
  268. unsigned int CharNStat;
  269. int ToRecv, wRecv, space;
  270. unsigned char *cbuf;
  271. ToRecv = sGetRxCnt(cp);
  272. #ifdef ROCKET_DEBUG_INTR
  273. printk(KERN_INFO "rp_do_receive(%d)...\n", ToRecv);
  274. #endif
  275. if (ToRecv == 0)
  276. return;
  277. /*
  278. * if status indicates there are errored characters in the
  279. * FIFO, then enter status mode (a word in FIFO holds
  280. * character and status).
  281. */
  282. if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
  283. if (!(ChanStatus & STATMODE)) {
  284. #ifdef ROCKET_DEBUG_RECEIVE
  285. printk(KERN_INFO "Entering STATMODE...\n");
  286. #endif
  287. ChanStatus |= STATMODE;
  288. sEnRxStatusMode(cp);
  289. }
  290. }
  291. /*
  292. * if we previously entered status mode, then read down the
  293. * FIFO one word at a time, pulling apart the character and
  294. * the status. Update error counters depending on status
  295. */
  296. if (ChanStatus & STATMODE) {
  297. #ifdef ROCKET_DEBUG_RECEIVE
  298. printk(KERN_INFO "Ignore %x, read %x...\n",
  299. info->ignore_status_mask, info->read_status_mask);
  300. #endif
  301. while (ToRecv) {
  302. char flag;
  303. CharNStat = sInW(sGetTxRxDataIO(cp));
  304. #ifdef ROCKET_DEBUG_RECEIVE
  305. printk(KERN_INFO "%x...\n", CharNStat);
  306. #endif
  307. if (CharNStat & STMBREAKH)
  308. CharNStat &= ~(STMFRAMEH | STMPARITYH);
  309. if (CharNStat & info->ignore_status_mask) {
  310. ToRecv--;
  311. continue;
  312. }
  313. CharNStat &= info->read_status_mask;
  314. if (CharNStat & STMBREAKH)
  315. flag = TTY_BREAK;
  316. else if (CharNStat & STMPARITYH)
  317. flag = TTY_PARITY;
  318. else if (CharNStat & STMFRAMEH)
  319. flag = TTY_FRAME;
  320. else if (CharNStat & STMRCVROVRH)
  321. flag = TTY_OVERRUN;
  322. else
  323. flag = TTY_NORMAL;
  324. tty_insert_flip_char(&info->port, CharNStat & 0xff,
  325. flag);
  326. ToRecv--;
  327. }
  328. /*
  329. * after we've emptied the FIFO in status mode, turn
  330. * status mode back off
  331. */
  332. if (sGetRxCnt(cp) == 0) {
  333. #ifdef ROCKET_DEBUG_RECEIVE
  334. printk(KERN_INFO "Status mode off.\n");
  335. #endif
  336. sDisRxStatusMode(cp);
  337. }
  338. } else {
  339. /*
  340. * we aren't in status mode, so read down the FIFO two
  341. * characters at time by doing repeated word IO
  342. * transfer.
  343. */
  344. space = tty_prepare_flip_string(&info->port, &cbuf, ToRecv);
  345. if (space < ToRecv) {
  346. #ifdef ROCKET_DEBUG_RECEIVE
  347. printk(KERN_INFO "rp_do_receive:insufficient space ToRecv=%d space=%d\n", ToRecv, space);
  348. #endif
  349. if (space <= 0)
  350. return;
  351. ToRecv = space;
  352. }
  353. wRecv = ToRecv >> 1;
  354. if (wRecv)
  355. sInStrW(sGetTxRxDataIO(cp), (unsigned short *) cbuf, wRecv);
  356. if (ToRecv & 1)
  357. cbuf[ToRecv - 1] = sInB(sGetTxRxDataIO(cp));
  358. }
  359. /* Push the data up to the tty layer */
  360. tty_flip_buffer_push(&info->port);
  361. }
  362. /*
  363. * Serial port transmit data function. Called from the timer polling loop as a
  364. * result of a bit set in xmit_flags[], indicating data (from the tty layer) is ready
  365. * to be sent out the serial port. Data is buffered in rp_table[line].xmit_buf, it is
  366. * moved to the port's xmit FIFO. *info is critical data, protected by spinlocks.
  367. */
  368. static void rp_do_transmit(struct r_port *info)
  369. {
  370. int c;
  371. CHANNEL_t *cp = &info->channel;
  372. struct tty_struct *tty;
  373. unsigned long flags;
  374. #ifdef ROCKET_DEBUG_INTR
  375. printk(KERN_DEBUG "%s\n", __func__);
  376. #endif
  377. if (!info)
  378. return;
  379. tty = tty_port_tty_get(&info->port);
  380. if (tty == NULL) {
  381. printk(KERN_WARNING "rp: WARNING %s called with tty==NULL\n", __func__);
  382. clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
  383. return;
  384. }
  385. spin_lock_irqsave(&info->slock, flags);
  386. info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
  387. /* Loop sending data to FIFO until done or FIFO full */
  388. while (1) {
  389. if (tty->stopped)
  390. break;
  391. c = min(info->xmit_fifo_room, info->xmit_cnt);
  392. c = min(c, XMIT_BUF_SIZE - info->xmit_tail);
  393. if (c <= 0 || info->xmit_fifo_room <= 0)
  394. break;
  395. sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) (info->xmit_buf + info->xmit_tail), c / 2);
  396. if (c & 1)
  397. sOutB(sGetTxRxDataIO(cp), info->xmit_buf[info->xmit_tail + c - 1]);
  398. info->xmit_tail += c;
  399. info->xmit_tail &= XMIT_BUF_SIZE - 1;
  400. info->xmit_cnt -= c;
  401. info->xmit_fifo_room -= c;
  402. #ifdef ROCKET_DEBUG_INTR
  403. printk(KERN_INFO "tx %d chars...\n", c);
  404. #endif
  405. }
  406. if (info->xmit_cnt == 0)
  407. clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
  408. if (info->xmit_cnt < WAKEUP_CHARS) {
  409. tty_wakeup(tty);
  410. #ifdef ROCKETPORT_HAVE_POLL_WAIT
  411. wake_up_interruptible(&tty->poll_wait);
  412. #endif
  413. }
  414. spin_unlock_irqrestore(&info->slock, flags);
  415. tty_kref_put(tty);
  416. #ifdef ROCKET_DEBUG_INTR
  417. printk(KERN_DEBUG "(%d,%d,%d,%d)...\n", info->xmit_cnt, info->xmit_head,
  418. info->xmit_tail, info->xmit_fifo_room);
  419. #endif
  420. }
  421. /*
  422. * Called when a serial port signals it has read data in it's RX FIFO.
  423. * It checks what interrupts are pending and services them, including
  424. * receiving serial data.
  425. */
  426. static void rp_handle_port(struct r_port *info)
  427. {
  428. CHANNEL_t *cp;
  429. unsigned int IntMask, ChanStatus;
  430. if (!info)
  431. return;
  432. if (!tty_port_initialized(&info->port)) {
  433. printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
  434. "info->flags & NOT_INIT\n");
  435. return;
  436. }
  437. cp = &info->channel;
  438. IntMask = sGetChanIntID(cp) & info->intmask;
  439. #ifdef ROCKET_DEBUG_INTR
  440. printk(KERN_INFO "rp_interrupt %02x...\n", IntMask);
  441. #endif
  442. ChanStatus = sGetChanStatus(cp);
  443. if (IntMask & RXF_TRIG) { /* Rx FIFO trigger level */
  444. rp_do_receive(info, cp, ChanStatus);
  445. }
  446. if (IntMask & DELTA_CD) { /* CD change */
  447. #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || defined(ROCKET_DEBUG_HANGUP))
  448. printk(KERN_INFO "ttyR%d CD now %s...\n", info->line,
  449. (ChanStatus & CD_ACT) ? "on" : "off");
  450. #endif
  451. if (!(ChanStatus & CD_ACT) && info->cd_status) {
  452. #ifdef ROCKET_DEBUG_HANGUP
  453. printk(KERN_INFO "CD drop, calling hangup.\n");
  454. #endif
  455. tty_port_tty_hangup(&info->port, false);
  456. }
  457. info->cd_status = (ChanStatus & CD_ACT) ? 1 : 0;
  458. wake_up_interruptible(&info->port.open_wait);
  459. }
  460. #ifdef ROCKET_DEBUG_INTR
  461. if (IntMask & DELTA_CTS) { /* CTS change */
  462. printk(KERN_INFO "CTS change...\n");
  463. }
  464. if (IntMask & DELTA_DSR) { /* DSR change */
  465. printk(KERN_INFO "DSR change...\n");
  466. }
  467. #endif
  468. }
  469. /*
  470. * The top level polling routine. Repeats every 1/100 HZ (10ms).
  471. */
  472. static void rp_do_poll(struct timer_list *unused)
  473. {
  474. CONTROLLER_t *ctlp;
  475. int ctrl, aiop, ch, line;
  476. unsigned int xmitmask, i;
  477. unsigned int CtlMask;
  478. unsigned char AiopMask;
  479. Word_t bit;
  480. /* Walk through all the boards (ctrl's) */
  481. for (ctrl = 0; ctrl < max_board; ctrl++) {
  482. if (rcktpt_io_addr[ctrl] <= 0)
  483. continue;
  484. /* Get a ptr to the board's control struct */
  485. ctlp = sCtlNumToCtlPtr(ctrl);
  486. /* Get the interrupt status from the board */
  487. #ifdef CONFIG_PCI
  488. if (ctlp->BusType == isPCI)
  489. CtlMask = sPCIGetControllerIntStatus(ctlp);
  490. else
  491. #endif
  492. CtlMask = sGetControllerIntStatus(ctlp);
  493. /* Check if any AIOP read bits are set */
  494. for (aiop = 0; CtlMask; aiop++) {
  495. bit = ctlp->AiopIntrBits[aiop];
  496. if (CtlMask & bit) {
  497. CtlMask &= ~bit;
  498. AiopMask = sGetAiopIntStatus(ctlp, aiop);
  499. /* Check if any port read bits are set */
  500. for (ch = 0; AiopMask; AiopMask >>= 1, ch++) {
  501. if (AiopMask & 1) {
  502. /* Get the line number (/dev/ttyRx number). */
  503. /* Read the data from the port. */
  504. line = GetLineNumber(ctrl, aiop, ch);
  505. rp_handle_port(rp_table[line]);
  506. }
  507. }
  508. }
  509. }
  510. xmitmask = xmit_flags[ctrl];
  511. /*
  512. * xmit_flags contains bit-significant flags, indicating there is data
  513. * to xmit on the port. Bit 0 is port 0 on this board, bit 1 is port
  514. * 1, ... (32 total possible). The variable i has the aiop and ch
  515. * numbers encoded in it (port 0-7 are aiop0, 8-15 are aiop1, etc).
  516. */
  517. if (xmitmask) {
  518. for (i = 0; i < rocketModel[ctrl].numPorts; i++) {
  519. if (xmitmask & (1 << i)) {
  520. aiop = (i & 0x18) >> 3;
  521. ch = i & 0x07;
  522. line = GetLineNumber(ctrl, aiop, ch);
  523. rp_do_transmit(rp_table[line]);
  524. }
  525. }
  526. }
  527. }
  528. /*
  529. * Reset the timer so we get called at the next clock tick (10ms).
  530. */
  531. if (atomic_read(&rp_num_ports_open))
  532. mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
  533. }
  534. /*
  535. * Initializes the r_port structure for a port, as well as enabling the port on
  536. * the board.
  537. * Inputs: board, aiop, chan numbers
  538. */
  539. static void __init
  540. init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev)
  541. {
  542. unsigned rocketMode;
  543. struct r_port *info;
  544. int line;
  545. CONTROLLER_T *ctlp;
  546. /* Get the next available line number */
  547. line = SetLineNumber(board, aiop, chan);
  548. ctlp = sCtlNumToCtlPtr(board);
  549. /* Get a r_port struct for the port, fill it in and save it globally, indexed by line number */
  550. info = kzalloc(sizeof (struct r_port), GFP_KERNEL);
  551. if (!info) {
  552. printk(KERN_ERR "Couldn't allocate info struct for line #%d\n",
  553. line);
  554. return;
  555. }
  556. info->magic = RPORT_MAGIC;
  557. info->line = line;
  558. info->ctlp = ctlp;
  559. info->board = board;
  560. info->aiop = aiop;
  561. info->chan = chan;
  562. tty_port_init(&info->port);
  563. info->port.ops = &rocket_port_ops;
  564. info->flags &= ~ROCKET_MODE_MASK;
  565. if (board < ARRAY_SIZE(pc104) && line < ARRAY_SIZE(pc104_1))
  566. switch (pc104[board][line]) {
  567. case 422:
  568. info->flags |= ROCKET_MODE_RS422;
  569. break;
  570. case 485:
  571. info->flags |= ROCKET_MODE_RS485;
  572. break;
  573. case 232:
  574. default:
  575. info->flags |= ROCKET_MODE_RS232;
  576. break;
  577. }
  578. else
  579. info->flags |= ROCKET_MODE_RS232;
  580. info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR;
  581. if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) {
  582. printk(KERN_ERR "RocketPort sInitChan(%d, %d, %d) failed!\n",
  583. board, aiop, chan);
  584. tty_port_destroy(&info->port);
  585. kfree(info);
  586. return;
  587. }
  588. rocketMode = info->flags & ROCKET_MODE_MASK;
  589. if ((info->flags & ROCKET_RTS_TOGGLE) || (rocketMode == ROCKET_MODE_RS485))
  590. sEnRTSToggle(&info->channel);
  591. else
  592. sDisRTSToggle(&info->channel);
  593. if (ctlp->boardType == ROCKET_TYPE_PC104) {
  594. switch (rocketMode) {
  595. case ROCKET_MODE_RS485:
  596. sSetInterfaceMode(&info->channel, InterfaceModeRS485);
  597. break;
  598. case ROCKET_MODE_RS422:
  599. sSetInterfaceMode(&info->channel, InterfaceModeRS422);
  600. break;
  601. case ROCKET_MODE_RS232:
  602. default:
  603. if (info->flags & ROCKET_RTS_TOGGLE)
  604. sSetInterfaceMode(&info->channel, InterfaceModeRS232T);
  605. else
  606. sSetInterfaceMode(&info->channel, InterfaceModeRS232);
  607. break;
  608. }
  609. }
  610. spin_lock_init(&info->slock);
  611. mutex_init(&info->write_mtx);
  612. rp_table[line] = info;
  613. tty_port_register_device(&info->port, rocket_driver, line,
  614. pci_dev ? &pci_dev->dev : NULL);
  615. }
  616. /*
  617. * Configures a rocketport port according to its termio settings. Called from
  618. * user mode into the driver (exception handler). *info CD manipulation is spinlock protected.
  619. */
  620. static void configure_r_port(struct tty_struct *tty, struct r_port *info,
  621. struct ktermios *old_termios)
  622. {
  623. unsigned cflag;
  624. unsigned long flags;
  625. unsigned rocketMode;
  626. int bits, baud, divisor;
  627. CHANNEL_t *cp;
  628. struct ktermios *t = &tty->termios;
  629. cp = &info->channel;
  630. cflag = t->c_cflag;
  631. /* Byte size and parity */
  632. if ((cflag & CSIZE) == CS8) {
  633. sSetData8(cp);
  634. bits = 10;
  635. } else {
  636. sSetData7(cp);
  637. bits = 9;
  638. }
  639. if (cflag & CSTOPB) {
  640. sSetStop2(cp);
  641. bits++;
  642. } else {
  643. sSetStop1(cp);
  644. }
  645. if (cflag & PARENB) {
  646. sEnParity(cp);
  647. bits++;
  648. if (cflag & PARODD) {
  649. sSetOddParity(cp);
  650. } else {
  651. sSetEvenParity(cp);
  652. }
  653. } else {
  654. sDisParity(cp);
  655. }
  656. /* baud rate */
  657. baud = tty_get_baud_rate(tty);
  658. if (!baud)
  659. baud = 9600;
  660. divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1;
  661. if ((divisor >= 8192 || divisor < 0) && old_termios) {
  662. baud = tty_termios_baud_rate(old_termios);
  663. if (!baud)
  664. baud = 9600;
  665. divisor = (rp_baud_base[info->board] / baud) - 1;
  666. }
  667. if (divisor >= 8192 || divisor < 0) {
  668. baud = 9600;
  669. divisor = (rp_baud_base[info->board] / baud) - 1;
  670. }
  671. info->cps = baud / bits;
  672. sSetBaud(cp, divisor);
  673. /* FIXME: Should really back compute a baud rate from the divisor */
  674. tty_encode_baud_rate(tty, baud, baud);
  675. if (cflag & CRTSCTS) {
  676. info->intmask |= DELTA_CTS;
  677. sEnCTSFlowCtl(cp);
  678. } else {
  679. info->intmask &= ~DELTA_CTS;
  680. sDisCTSFlowCtl(cp);
  681. }
  682. if (cflag & CLOCAL) {
  683. info->intmask &= ~DELTA_CD;
  684. } else {
  685. spin_lock_irqsave(&info->slock, flags);
  686. if (sGetChanStatus(cp) & CD_ACT)
  687. info->cd_status = 1;
  688. else
  689. info->cd_status = 0;
  690. info->intmask |= DELTA_CD;
  691. spin_unlock_irqrestore(&info->slock, flags);
  692. }
  693. /*
  694. * Handle software flow control in the board
  695. */
  696. #ifdef ROCKET_SOFT_FLOW
  697. if (I_IXON(tty)) {
  698. sEnTxSoftFlowCtl(cp);
  699. if (I_IXANY(tty)) {
  700. sEnIXANY(cp);
  701. } else {
  702. sDisIXANY(cp);
  703. }
  704. sSetTxXONChar(cp, START_CHAR(tty));
  705. sSetTxXOFFChar(cp, STOP_CHAR(tty));
  706. } else {
  707. sDisTxSoftFlowCtl(cp);
  708. sDisIXANY(cp);
  709. sClrTxXOFF(cp);
  710. }
  711. #endif
  712. /*
  713. * Set up ignore/read mask words
  714. */
  715. info->read_status_mask = STMRCVROVRH | 0xFF;
  716. if (I_INPCK(tty))
  717. info->read_status_mask |= STMFRAMEH | STMPARITYH;
  718. if (I_BRKINT(tty) || I_PARMRK(tty))
  719. info->read_status_mask |= STMBREAKH;
  720. /*
  721. * Characters to ignore
  722. */
  723. info->ignore_status_mask = 0;
  724. if (I_IGNPAR(tty))
  725. info->ignore_status_mask |= STMFRAMEH | STMPARITYH;
  726. if (I_IGNBRK(tty)) {
  727. info->ignore_status_mask |= STMBREAKH;
  728. /*
  729. * If we're ignoring parity and break indicators,
  730. * ignore overruns too. (For real raw support).
  731. */
  732. if (I_IGNPAR(tty))
  733. info->ignore_status_mask |= STMRCVROVRH;
  734. }
  735. rocketMode = info->flags & ROCKET_MODE_MASK;
  736. if ((info->flags & ROCKET_RTS_TOGGLE)
  737. || (rocketMode == ROCKET_MODE_RS485))
  738. sEnRTSToggle(cp);
  739. else
  740. sDisRTSToggle(cp);
  741. sSetRTS(&info->channel);
  742. if (cp->CtlP->boardType == ROCKET_TYPE_PC104) {
  743. switch (rocketMode) {
  744. case ROCKET_MODE_RS485:
  745. sSetInterfaceMode(cp, InterfaceModeRS485);
  746. break;
  747. case ROCKET_MODE_RS422:
  748. sSetInterfaceMode(cp, InterfaceModeRS422);
  749. break;
  750. case ROCKET_MODE_RS232:
  751. default:
  752. if (info->flags & ROCKET_RTS_TOGGLE)
  753. sSetInterfaceMode(cp, InterfaceModeRS232T);
  754. else
  755. sSetInterfaceMode(cp, InterfaceModeRS232);
  756. break;
  757. }
  758. }
  759. }
  760. static int carrier_raised(struct tty_port *port)
  761. {
  762. struct r_port *info = container_of(port, struct r_port, port);
  763. return (sGetChanStatusLo(&info->channel) & CD_ACT) ? 1 : 0;
  764. }
  765. static void dtr_rts(struct tty_port *port, int on)
  766. {
  767. struct r_port *info = container_of(port, struct r_port, port);
  768. if (on) {
  769. sSetDTR(&info->channel);
  770. sSetRTS(&info->channel);
  771. } else {
  772. sClrDTR(&info->channel);
  773. sClrRTS(&info->channel);
  774. }
  775. }
  776. /*
  777. * Exception handler that opens a serial port. Creates xmit_buf storage, fills in
  778. * port's r_port struct. Initializes the port hardware.
  779. */
  780. static int rp_open(struct tty_struct *tty, struct file *filp)
  781. {
  782. struct r_port *info;
  783. struct tty_port *port;
  784. int retval;
  785. CHANNEL_t *cp;
  786. unsigned long page;
  787. info = rp_table[tty->index];
  788. if (info == NULL)
  789. return -ENXIO;
  790. port = &info->port;
  791. page = __get_free_page(GFP_KERNEL);
  792. if (!page)
  793. return -ENOMEM;
  794. /*
  795. * We must not sleep from here until the port is marked fully in use.
  796. */
  797. if (info->xmit_buf)
  798. free_page(page);
  799. else
  800. info->xmit_buf = (unsigned char *) page;
  801. tty->driver_data = info;
  802. tty_port_tty_set(port, tty);
  803. if (port->count++ == 0) {
  804. atomic_inc(&rp_num_ports_open);
  805. #ifdef ROCKET_DEBUG_OPEN
  806. printk(KERN_INFO "rocket mod++ = %d...\n",
  807. atomic_read(&rp_num_ports_open));
  808. #endif
  809. }
  810. #ifdef ROCKET_DEBUG_OPEN
  811. printk(KERN_INFO "rp_open ttyR%d, count=%d\n", info->line, info->port.count);
  812. #endif
  813. /*
  814. * Info->count is now 1; so it's safe to sleep now.
  815. */
  816. if (!tty_port_initialized(port)) {
  817. cp = &info->channel;
  818. sSetRxTrigger(cp, TRIG_1);
  819. if (sGetChanStatus(cp) & CD_ACT)
  820. info->cd_status = 1;
  821. else
  822. info->cd_status = 0;
  823. sDisRxStatusMode(cp);
  824. sFlushRxFIFO(cp);
  825. sFlushTxFIFO(cp);
  826. sEnInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
  827. sSetRxTrigger(cp, TRIG_1);
  828. sGetChanStatus(cp);
  829. sDisRxStatusMode(cp);
  830. sClrTxXOFF(cp);
  831. sDisCTSFlowCtl(cp);
  832. sDisTxSoftFlowCtl(cp);
  833. sEnRxFIFO(cp);
  834. sEnTransmit(cp);
  835. tty_port_set_initialized(&info->port, 1);
  836. configure_r_port(tty, info, NULL);
  837. if (C_BAUD(tty)) {
  838. sSetDTR(cp);
  839. sSetRTS(cp);
  840. }
  841. }
  842. /* Starts (or resets) the maint polling loop */
  843. mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
  844. retval = tty_port_block_til_ready(port, tty, filp);
  845. if (retval) {
  846. #ifdef ROCKET_DEBUG_OPEN
  847. printk(KERN_INFO "rp_open returning after block_til_ready with %d\n", retval);
  848. #endif
  849. return retval;
  850. }
  851. return 0;
  852. }
  853. /*
  854. * Exception handler that closes a serial port. info->port.count is considered critical.
  855. */
  856. static void rp_close(struct tty_struct *tty, struct file *filp)
  857. {
  858. struct r_port *info = tty->driver_data;
  859. struct tty_port *port = &info->port;
  860. int timeout;
  861. CHANNEL_t *cp;
  862. if (rocket_paranoia_check(info, "rp_close"))
  863. return;
  864. #ifdef ROCKET_DEBUG_OPEN
  865. printk(KERN_INFO "rp_close ttyR%d, count = %d\n", info->line, info->port.count);
  866. #endif
  867. if (tty_port_close_start(port, tty, filp) == 0)
  868. return;
  869. mutex_lock(&port->mutex);
  870. cp = &info->channel;
  871. /*
  872. * Before we drop DTR, make sure the UART transmitter
  873. * has completely drained; this is especially
  874. * important if there is a transmit FIFO!
  875. */
  876. timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps;
  877. if (timeout == 0)
  878. timeout = 1;
  879. rp_wait_until_sent(tty, timeout);
  880. clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
  881. sDisTransmit(cp);
  882. sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
  883. sDisCTSFlowCtl(cp);
  884. sDisTxSoftFlowCtl(cp);
  885. sClrTxXOFF(cp);
  886. sFlushRxFIFO(cp);
  887. sFlushTxFIFO(cp);
  888. sClrRTS(cp);
  889. if (C_HUPCL(tty))
  890. sClrDTR(cp);
  891. rp_flush_buffer(tty);
  892. tty_ldisc_flush(tty);
  893. clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
  894. /* We can't yet use tty_port_close_end as the buffer handling in this
  895. driver is a bit different to the usual */
  896. if (port->blocked_open) {
  897. if (port->close_delay) {
  898. msleep_interruptible(jiffies_to_msecs(port->close_delay));
  899. }
  900. wake_up_interruptible(&port->open_wait);
  901. } else {
  902. if (info->xmit_buf) {
  903. free_page((unsigned long) info->xmit_buf);
  904. info->xmit_buf = NULL;
  905. }
  906. }
  907. spin_lock_irq(&port->lock);
  908. tty->closing = 0;
  909. spin_unlock_irq(&port->lock);
  910. tty_port_set_initialized(port, 0);
  911. tty_port_set_active(port, 0);
  912. mutex_unlock(&port->mutex);
  913. tty_port_tty_set(port, NULL);
  914. atomic_dec(&rp_num_ports_open);
  915. #ifdef ROCKET_DEBUG_OPEN
  916. printk(KERN_INFO "rocket mod-- = %d...\n",
  917. atomic_read(&rp_num_ports_open));
  918. printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line);
  919. #endif
  920. }
  921. static void rp_set_termios(struct tty_struct *tty,
  922. struct ktermios *old_termios)
  923. {
  924. struct r_port *info = tty->driver_data;
  925. CHANNEL_t *cp;
  926. unsigned cflag;
  927. if (rocket_paranoia_check(info, "rp_set_termios"))
  928. return;
  929. cflag = tty->termios.c_cflag;
  930. /*
  931. * This driver doesn't support CS5 or CS6
  932. */
  933. if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6))
  934. tty->termios.c_cflag =
  935. ((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE));
  936. /* Or CMSPAR */
  937. tty->termios.c_cflag &= ~CMSPAR;
  938. configure_r_port(tty, info, old_termios);
  939. cp = &info->channel;
  940. /* Handle transition to B0 status */
  941. if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
  942. sClrDTR(cp);
  943. sClrRTS(cp);
  944. }
  945. /* Handle transition away from B0 status */
  946. if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
  947. sSetRTS(cp);
  948. sSetDTR(cp);
  949. }
  950. if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty))
  951. rp_start(tty);
  952. }
  953. static int rp_break(struct tty_struct *tty, int break_state)
  954. {
  955. struct r_port *info = tty->driver_data;
  956. unsigned long flags;
  957. if (rocket_paranoia_check(info, "rp_break"))
  958. return -EINVAL;
  959. spin_lock_irqsave(&info->slock, flags);
  960. if (break_state == -1)
  961. sSendBreak(&info->channel);
  962. else
  963. sClrBreak(&info->channel);
  964. spin_unlock_irqrestore(&info->slock, flags);
  965. return 0;
  966. }
  967. /*
  968. * sGetChanRI used to be a macro in rocket_int.h. When the functionality for
  969. * the UPCI boards was added, it was decided to make this a function because
  970. * the macro was getting too complicated. All cases except the first one
  971. * (UPCIRingInd) are taken directly from the original macro.
  972. */
  973. static int sGetChanRI(CHANNEL_T * ChP)
  974. {
  975. CONTROLLER_t *CtlP = ChP->CtlP;
  976. int ChanNum = ChP->ChanNum;
  977. int RingInd = 0;
  978. if (CtlP->UPCIRingInd)
  979. RingInd = !(sInB(CtlP->UPCIRingInd) & sBitMapSetTbl[ChanNum]);
  980. else if (CtlP->AltChanRingIndicator)
  981. RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT;
  982. else if (CtlP->boardType == ROCKET_TYPE_PC104)
  983. RingInd = !(sInB(CtlP->AiopIO[3]) & sBitMapSetTbl[ChanNum]);
  984. return RingInd;
  985. }
  986. /********************************************************************************************/
  987. /* Here are the routines used by rp_ioctl. These are all called from exception handlers. */
  988. /*
  989. * Returns the state of the serial modem control lines. These next 2 functions
  990. * are the way kernel versions > 2.5 handle modem control lines rather than IOCTLs.
  991. */
  992. static int rp_tiocmget(struct tty_struct *tty)
  993. {
  994. struct r_port *info = tty->driver_data;
  995. unsigned int control, result, ChanStatus;
  996. ChanStatus = sGetChanStatusLo(&info->channel);
  997. control = info->channel.TxControl[3];
  998. result = ((control & SET_RTS) ? TIOCM_RTS : 0) |
  999. ((control & SET_DTR) ? TIOCM_DTR : 0) |
  1000. ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0) |
  1001. (sGetChanRI(&info->channel) ? TIOCM_RNG : 0) |
  1002. ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0) |
  1003. ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0);
  1004. return result;
  1005. }
  1006. /*
  1007. * Sets the modem control lines
  1008. */
  1009. static int rp_tiocmset(struct tty_struct *tty,
  1010. unsigned int set, unsigned int clear)
  1011. {
  1012. struct r_port *info = tty->driver_data;
  1013. if (set & TIOCM_RTS)
  1014. info->channel.TxControl[3] |= SET_RTS;
  1015. if (set & TIOCM_DTR)
  1016. info->channel.TxControl[3] |= SET_DTR;
  1017. if (clear & TIOCM_RTS)
  1018. info->channel.TxControl[3] &= ~SET_RTS;
  1019. if (clear & TIOCM_DTR)
  1020. info->channel.TxControl[3] &= ~SET_DTR;
  1021. out32(info->channel.IndexAddr, info->channel.TxControl);
  1022. return 0;
  1023. }
  1024. static int get_config(struct r_port *info, struct rocket_config __user *retinfo)
  1025. {
  1026. struct rocket_config tmp;
  1027. memset(&tmp, 0, sizeof (tmp));
  1028. mutex_lock(&info->port.mutex);
  1029. tmp.line = info->line;
  1030. tmp.flags = info->flags;
  1031. tmp.close_delay = info->port.close_delay;
  1032. tmp.closing_wait = info->port.closing_wait;
  1033. tmp.port = rcktpt_io_addr[(info->line >> 5) & 3];
  1034. mutex_unlock(&info->port.mutex);
  1035. if (copy_to_user(retinfo, &tmp, sizeof (*retinfo)))
  1036. return -EFAULT;
  1037. return 0;
  1038. }
  1039. static int set_config(struct tty_struct *tty, struct r_port *info,
  1040. struct rocket_config __user *new_info)
  1041. {
  1042. struct rocket_config new_serial;
  1043. if (copy_from_user(&new_serial, new_info, sizeof (new_serial)))
  1044. return -EFAULT;
  1045. mutex_lock(&info->port.mutex);
  1046. if (!capable(CAP_SYS_ADMIN))
  1047. {
  1048. if ((new_serial.flags & ~ROCKET_USR_MASK) != (info->flags & ~ROCKET_USR_MASK)) {
  1049. mutex_unlock(&info->port.mutex);
  1050. return -EPERM;
  1051. }
  1052. info->flags = ((info->flags & ~ROCKET_USR_MASK) | (new_serial.flags & ROCKET_USR_MASK));
  1053. mutex_unlock(&info->port.mutex);
  1054. return 0;
  1055. }
  1056. if ((new_serial.flags ^ info->flags) & ROCKET_SPD_MASK) {
  1057. /* warn about deprecation, unless clearing */
  1058. if (new_serial.flags & ROCKET_SPD_MASK)
  1059. dev_warn_ratelimited(tty->dev, "use of SPD flags is deprecated\n");
  1060. }
  1061. info->flags = ((info->flags & ~ROCKET_FLAGS) | (new_serial.flags & ROCKET_FLAGS));
  1062. info->port.close_delay = new_serial.close_delay;
  1063. info->port.closing_wait = new_serial.closing_wait;
  1064. mutex_unlock(&info->port.mutex);
  1065. configure_r_port(tty, info, NULL);
  1066. return 0;
  1067. }
  1068. /*
  1069. * This function fills in a rocket_ports struct with information
  1070. * about what boards/ports are in the system. This info is passed
  1071. * to user space. See setrocket.c where the info is used to create
  1072. * the /dev/ttyRx ports.
  1073. */
  1074. static int get_ports(struct r_port *info, struct rocket_ports __user *retports)
  1075. {
  1076. struct rocket_ports *tmp;
  1077. int board, ret = 0;
  1078. tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
  1079. if (!tmp)
  1080. return -ENOMEM;
  1081. tmp->tty_major = rocket_driver->major;
  1082. for (board = 0; board < 4; board++) {
  1083. tmp->rocketModel[board].model = rocketModel[board].model;
  1084. strcpy(tmp->rocketModel[board].modelString,
  1085. rocketModel[board].modelString);
  1086. tmp->rocketModel[board].numPorts = rocketModel[board].numPorts;
  1087. tmp->rocketModel[board].loadrm2 = rocketModel[board].loadrm2;
  1088. tmp->rocketModel[board].startingPortNumber =
  1089. rocketModel[board].startingPortNumber;
  1090. }
  1091. if (copy_to_user(retports, tmp, sizeof(*retports)))
  1092. ret = -EFAULT;
  1093. kfree(tmp);
  1094. return ret;
  1095. }
  1096. static int reset_rm2(struct r_port *info, void __user *arg)
  1097. {
  1098. int reset;
  1099. if (!capable(CAP_SYS_ADMIN))
  1100. return -EPERM;
  1101. if (copy_from_user(&reset, arg, sizeof (int)))
  1102. return -EFAULT;
  1103. if (reset)
  1104. reset = 1;
  1105. if (rcktpt_type[info->board] != ROCKET_TYPE_MODEMII &&
  1106. rcktpt_type[info->board] != ROCKET_TYPE_MODEMIII)
  1107. return -EINVAL;
  1108. if (info->ctlp->BusType == isISA)
  1109. sModemReset(info->ctlp, info->chan, reset);
  1110. else
  1111. sPCIModemReset(info->ctlp, info->chan, reset);
  1112. return 0;
  1113. }
  1114. static int get_version(struct r_port *info, struct rocket_version __user *retvers)
  1115. {
  1116. if (copy_to_user(retvers, &driver_version, sizeof (*retvers)))
  1117. return -EFAULT;
  1118. return 0;
  1119. }
  1120. /* IOCTL call handler into the driver */
  1121. static int rp_ioctl(struct tty_struct *tty,
  1122. unsigned int cmd, unsigned long arg)
  1123. {
  1124. struct r_port *info = tty->driver_data;
  1125. void __user *argp = (void __user *)arg;
  1126. int ret = 0;
  1127. if (cmd != RCKP_GET_PORTS && rocket_paranoia_check(info, "rp_ioctl"))
  1128. return -ENXIO;
  1129. switch (cmd) {
  1130. case RCKP_GET_CONFIG:
  1131. dev_warn_ratelimited(tty->dev,
  1132. "RCKP_GET_CONFIG option is deprecated\n");
  1133. ret = get_config(info, argp);
  1134. break;
  1135. case RCKP_SET_CONFIG:
  1136. dev_warn_ratelimited(tty->dev,
  1137. "RCKP_SET_CONFIG option is deprecated\n");
  1138. ret = set_config(tty, info, argp);
  1139. break;
  1140. case RCKP_GET_PORTS:
  1141. dev_warn_ratelimited(tty->dev,
  1142. "RCKP_GET_PORTS option is deprecated\n");
  1143. ret = get_ports(info, argp);
  1144. break;
  1145. case RCKP_RESET_RM2:
  1146. dev_warn_ratelimited(tty->dev,
  1147. "RCKP_RESET_RM2 option is deprecated\n");
  1148. ret = reset_rm2(info, argp);
  1149. break;
  1150. case RCKP_GET_VERSION:
  1151. dev_warn_ratelimited(tty->dev,
  1152. "RCKP_GET_VERSION option is deprecated\n");
  1153. ret = get_version(info, argp);
  1154. break;
  1155. default:
  1156. ret = -ENOIOCTLCMD;
  1157. }
  1158. return ret;
  1159. }
  1160. static void rp_send_xchar(struct tty_struct *tty, char ch)
  1161. {
  1162. struct r_port *info = tty->driver_data;
  1163. CHANNEL_t *cp;
  1164. if (rocket_paranoia_check(info, "rp_send_xchar"))
  1165. return;
  1166. cp = &info->channel;
  1167. if (sGetTxCnt(cp))
  1168. sWriteTxPrioByte(cp, ch);
  1169. else
  1170. sWriteTxByte(sGetTxRxDataIO(cp), ch);
  1171. }
  1172. static void rp_throttle(struct tty_struct *tty)
  1173. {
  1174. struct r_port *info = tty->driver_data;
  1175. #ifdef ROCKET_DEBUG_THROTTLE
  1176. printk(KERN_INFO "throttle %s ....\n", tty->name);
  1177. #endif
  1178. if (rocket_paranoia_check(info, "rp_throttle"))
  1179. return;
  1180. if (I_IXOFF(tty))
  1181. rp_send_xchar(tty, STOP_CHAR(tty));
  1182. sClrRTS(&info->channel);
  1183. }
  1184. static void rp_unthrottle(struct tty_struct *tty)
  1185. {
  1186. struct r_port *info = tty->driver_data;
  1187. #ifdef ROCKET_DEBUG_THROTTLE
  1188. printk(KERN_INFO "unthrottle %s ....\n", tty->name);
  1189. #endif
  1190. if (rocket_paranoia_check(info, "rp_unthrottle"))
  1191. return;
  1192. if (I_IXOFF(tty))
  1193. rp_send_xchar(tty, START_CHAR(tty));
  1194. sSetRTS(&info->channel);
  1195. }
  1196. /*
  1197. * ------------------------------------------------------------
  1198. * rp_stop() and rp_start()
  1199. *
  1200. * This routines are called before setting or resetting tty->stopped.
  1201. * They enable or disable transmitter interrupts, as necessary.
  1202. * ------------------------------------------------------------
  1203. */
  1204. static void rp_stop(struct tty_struct *tty)
  1205. {
  1206. struct r_port *info = tty->driver_data;
  1207. #ifdef ROCKET_DEBUG_FLOW
  1208. printk(KERN_INFO "stop %s: %d %d....\n", tty->name,
  1209. info->xmit_cnt, info->xmit_fifo_room);
  1210. #endif
  1211. if (rocket_paranoia_check(info, "rp_stop"))
  1212. return;
  1213. if (sGetTxCnt(&info->channel))
  1214. sDisTransmit(&info->channel);
  1215. }
  1216. static void rp_start(struct tty_struct *tty)
  1217. {
  1218. struct r_port *info = tty->driver_data;
  1219. #ifdef ROCKET_DEBUG_FLOW
  1220. printk(KERN_INFO "start %s: %d %d....\n", tty->name,
  1221. info->xmit_cnt, info->xmit_fifo_room);
  1222. #endif
  1223. if (rocket_paranoia_check(info, "rp_stop"))
  1224. return;
  1225. sEnTransmit(&info->channel);
  1226. set_bit((info->aiop * 8) + info->chan,
  1227. (void *) &xmit_flags[info->board]);
  1228. }
  1229. /*
  1230. * rp_wait_until_sent() --- wait until the transmitter is empty
  1231. */
  1232. static void rp_wait_until_sent(struct tty_struct *tty, int timeout)
  1233. {
  1234. struct r_port *info = tty->driver_data;
  1235. CHANNEL_t *cp;
  1236. unsigned long orig_jiffies;
  1237. int check_time, exit_time;
  1238. int txcnt;
  1239. if (rocket_paranoia_check(info, "rp_wait_until_sent"))
  1240. return;
  1241. cp = &info->channel;
  1242. orig_jiffies = jiffies;
  1243. #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
  1244. printk(KERN_INFO "In %s(%d) (jiff=%lu)...\n", __func__, timeout,
  1245. jiffies);
  1246. printk(KERN_INFO "cps=%d...\n", info->cps);
  1247. #endif
  1248. while (1) {
  1249. txcnt = sGetTxCnt(cp);
  1250. if (!txcnt) {
  1251. if (sGetChanStatusLo(cp) & TXSHRMT)
  1252. break;
  1253. check_time = (HZ / info->cps) / 5;
  1254. } else {
  1255. check_time = HZ * txcnt / info->cps;
  1256. }
  1257. if (timeout) {
  1258. exit_time = orig_jiffies + timeout - jiffies;
  1259. if (exit_time <= 0)
  1260. break;
  1261. if (exit_time < check_time)
  1262. check_time = exit_time;
  1263. }
  1264. if (check_time == 0)
  1265. check_time = 1;
  1266. #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
  1267. printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...\n", txcnt,
  1268. jiffies, check_time);
  1269. #endif
  1270. msleep_interruptible(jiffies_to_msecs(check_time));
  1271. if (signal_pending(current))
  1272. break;
  1273. }
  1274. __set_current_state(TASK_RUNNING);
  1275. #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
  1276. printk(KERN_INFO "txcnt = %d (jiff=%lu)...done\n", txcnt, jiffies);
  1277. #endif
  1278. }
  1279. /*
  1280. * rp_hangup() --- called by tty_hangup() when a hangup is signaled.
  1281. */
  1282. static void rp_hangup(struct tty_struct *tty)
  1283. {
  1284. CHANNEL_t *cp;
  1285. struct r_port *info = tty->driver_data;
  1286. unsigned long flags;
  1287. if (rocket_paranoia_check(info, "rp_hangup"))
  1288. return;
  1289. #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP))
  1290. printk(KERN_INFO "rp_hangup of ttyR%d...\n", info->line);
  1291. #endif
  1292. rp_flush_buffer(tty);
  1293. spin_lock_irqsave(&info->port.lock, flags);
  1294. if (info->port.count)
  1295. atomic_dec(&rp_num_ports_open);
  1296. clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
  1297. spin_unlock_irqrestore(&info->port.lock, flags);
  1298. tty_port_hangup(&info->port);
  1299. cp = &info->channel;
  1300. sDisRxFIFO(cp);
  1301. sDisTransmit(cp);
  1302. sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
  1303. sDisCTSFlowCtl(cp);
  1304. sDisTxSoftFlowCtl(cp);
  1305. sClrTxXOFF(cp);
  1306. tty_port_set_initialized(&info->port, 0);
  1307. wake_up_interruptible(&info->port.open_wait);
  1308. }
  1309. /*
  1310. * Exception handler - write char routine. The RocketPort driver uses a
  1311. * double-buffering strategy, with the twist that if the in-memory CPU
  1312. * buffer is empty, and there's space in the transmit FIFO, the
  1313. * writing routines will write directly to transmit FIFO.
  1314. * Write buffer and counters protected by spinlocks
  1315. */
  1316. static int rp_put_char(struct tty_struct *tty, unsigned char ch)
  1317. {
  1318. struct r_port *info = tty->driver_data;
  1319. CHANNEL_t *cp;
  1320. unsigned long flags;
  1321. if (rocket_paranoia_check(info, "rp_put_char"))
  1322. return 0;
  1323. /*
  1324. * Grab the port write mutex, locking out other processes that try to
  1325. * write to this port
  1326. */
  1327. mutex_lock(&info->write_mtx);
  1328. #ifdef ROCKET_DEBUG_WRITE
  1329. printk(KERN_INFO "rp_put_char %c...\n", ch);
  1330. #endif
  1331. spin_lock_irqsave(&info->slock, flags);
  1332. cp = &info->channel;
  1333. if (!tty->stopped && info->xmit_fifo_room == 0)
  1334. info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
  1335. if (tty->stopped || info->xmit_fifo_room == 0 || info->xmit_cnt != 0) {
  1336. info->xmit_buf[info->xmit_head++] = ch;
  1337. info->xmit_head &= XMIT_BUF_SIZE - 1;
  1338. info->xmit_cnt++;
  1339. set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
  1340. } else {
  1341. sOutB(sGetTxRxDataIO(cp), ch);
  1342. info->xmit_fifo_room--;
  1343. }
  1344. spin_unlock_irqrestore(&info->slock, flags);
  1345. mutex_unlock(&info->write_mtx);
  1346. return 1;
  1347. }
  1348. /*
  1349. * Exception handler - write routine, called when user app writes to the device.
  1350. * A per port write mutex is used to protect from another process writing to
  1351. * this port at the same time. This other process could be running on the other CPU
  1352. * or get control of the CPU if the copy_from_user() blocks due to a page fault (swapped out).
  1353. * Spinlocks protect the info xmit members.
  1354. */
  1355. static int rp_write(struct tty_struct *tty,
  1356. const unsigned char *buf, int count)
  1357. {
  1358. struct r_port *info = tty->driver_data;
  1359. CHANNEL_t *cp;
  1360. const unsigned char *b;
  1361. int c, retval = 0;
  1362. unsigned long flags;
  1363. if (count <= 0 || rocket_paranoia_check(info, "rp_write"))
  1364. return 0;
  1365. if (mutex_lock_interruptible(&info->write_mtx))
  1366. return -ERESTARTSYS;
  1367. #ifdef ROCKET_DEBUG_WRITE
  1368. printk(KERN_INFO "rp_write %d chars...\n", count);
  1369. #endif
  1370. cp = &info->channel;
  1371. if (!tty->stopped && info->xmit_fifo_room < count)
  1372. info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
  1373. /*
  1374. * If the write queue for the port is empty, and there is FIFO space, stuff bytes
  1375. * into FIFO. Use the write queue for temp storage.
  1376. */
  1377. if (!tty->stopped && info->xmit_cnt == 0 && info->xmit_fifo_room > 0) {
  1378. c = min(count, info->xmit_fifo_room);
  1379. b = buf;
  1380. /* Push data into FIFO, 2 bytes at a time */
  1381. sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) b, c / 2);
  1382. /* If there is a byte remaining, write it */
  1383. if (c & 1)
  1384. sOutB(sGetTxRxDataIO(cp), b[c - 1]);
  1385. retval += c;
  1386. buf += c;
  1387. count -= c;
  1388. spin_lock_irqsave(&info->slock, flags);
  1389. info->xmit_fifo_room -= c;
  1390. spin_unlock_irqrestore(&info->slock, flags);
  1391. }
  1392. /* If count is zero, we wrote it all and are done */
  1393. if (!count)
  1394. goto end;
  1395. /* Write remaining data into the port's xmit_buf */
  1396. while (1) {
  1397. /* Hung up ? */
  1398. if (!tty_port_active(&info->port))
  1399. goto end;
  1400. c = min(count, XMIT_BUF_SIZE - info->xmit_cnt - 1);
  1401. c = min(c, XMIT_BUF_SIZE - info->xmit_head);
  1402. if (c <= 0)
  1403. break;
  1404. b = buf;
  1405. memcpy(info->xmit_buf + info->xmit_head, b, c);
  1406. spin_lock_irqsave(&info->slock, flags);
  1407. info->xmit_head =
  1408. (info->xmit_head + c) & (XMIT_BUF_SIZE - 1);
  1409. info->xmit_cnt += c;
  1410. spin_unlock_irqrestore(&info->slock, flags);
  1411. buf += c;
  1412. count -= c;
  1413. retval += c;
  1414. }
  1415. if ((retval > 0) && !tty->stopped)
  1416. set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
  1417. end:
  1418. if (info->xmit_cnt < WAKEUP_CHARS) {
  1419. tty_wakeup(tty);
  1420. #ifdef ROCKETPORT_HAVE_POLL_WAIT
  1421. wake_up_interruptible(&tty->poll_wait);
  1422. #endif
  1423. }
  1424. mutex_unlock(&info->write_mtx);
  1425. return retval;
  1426. }
  1427. /*
  1428. * Return the number of characters that can be sent. We estimate
  1429. * only using the in-memory transmit buffer only, and ignore the
  1430. * potential space in the transmit FIFO.
  1431. */
  1432. static int rp_write_room(struct tty_struct *tty)
  1433. {
  1434. struct r_port *info = tty->driver_data;
  1435. int ret;
  1436. if (rocket_paranoia_check(info, "rp_write_room"))
  1437. return 0;
  1438. ret = XMIT_BUF_SIZE - info->xmit_cnt - 1;
  1439. if (ret < 0)
  1440. ret = 0;
  1441. #ifdef ROCKET_DEBUG_WRITE
  1442. printk(KERN_INFO "rp_write_room returns %d...\n", ret);
  1443. #endif
  1444. return ret;
  1445. }
  1446. /*
  1447. * Return the number of characters in the buffer. Again, this only
  1448. * counts those characters in the in-memory transmit buffer.
  1449. */
  1450. static int rp_chars_in_buffer(struct tty_struct *tty)
  1451. {
  1452. struct r_port *info = tty->driver_data;
  1453. if (rocket_paranoia_check(info, "rp_chars_in_buffer"))
  1454. return 0;
  1455. #ifdef ROCKET_DEBUG_WRITE
  1456. printk(KERN_INFO "rp_chars_in_buffer returns %d...\n", info->xmit_cnt);
  1457. #endif
  1458. return info->xmit_cnt;
  1459. }
  1460. /*
  1461. * Flushes the TX fifo for a port, deletes data in the xmit_buf stored in the
  1462. * r_port struct for the port. Note that spinlock are used to protect info members,
  1463. * do not call this function if the spinlock is already held.
  1464. */
  1465. static void rp_flush_buffer(struct tty_struct *tty)
  1466. {
  1467. struct r_port *info = tty->driver_data;
  1468. CHANNEL_t *cp;
  1469. unsigned long flags;
  1470. if (rocket_paranoia_check(info, "rp_flush_buffer"))
  1471. return;
  1472. spin_lock_irqsave(&info->slock, flags);
  1473. info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
  1474. spin_unlock_irqrestore(&info->slock, flags);
  1475. #ifdef ROCKETPORT_HAVE_POLL_WAIT
  1476. wake_up_interruptible(&tty->poll_wait);
  1477. #endif
  1478. tty_wakeup(tty);
  1479. cp = &info->channel;
  1480. sFlushTxFIFO(cp);
  1481. }
  1482. #ifdef CONFIG_PCI
  1483. static const struct pci_device_id rocket_pci_ids[] = {
  1484. { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4QUAD) },
  1485. { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8OCTA) },
  1486. { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP8OCTA) },
  1487. { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8INTF) },
  1488. { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP8INTF) },
  1489. { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8J) },
  1490. { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4J) },
  1491. { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8SNI) },
  1492. { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP16SNI) },
  1493. { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP16INTF) },
  1494. { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP16INTF) },
  1495. { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_CRP16INTF) },
  1496. { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP32INTF) },
  1497. { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP32INTF) },
  1498. { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RPP4) },
  1499. { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RPP8) },
  1500. { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP2_232) },
  1501. { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP2_422) },
  1502. { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP6M) },
  1503. { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4M) },
  1504. { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_UPCI_RM3_8PORT) },
  1505. { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_UPCI_RM3_4PORT) },
  1506. { }
  1507. };
  1508. MODULE_DEVICE_TABLE(pci, rocket_pci_ids);
  1509. /* Resets the speaker controller on RocketModem II and III devices */
  1510. static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model)
  1511. {
  1512. ByteIO_t addr;
  1513. /* RocketModem II speaker control is at the 8th port location of offset 0x40 */
  1514. if ((model == MODEL_RP4M) || (model == MODEL_RP6M)) {
  1515. addr = CtlP->AiopIO[0] + 0x4F;
  1516. sOutB(addr, 0);
  1517. }
  1518. /* RocketModem III speaker control is at the 1st port location of offset 0x80 */
  1519. if ((model == MODEL_UPCI_RM3_8PORT)
  1520. || (model == MODEL_UPCI_RM3_4PORT)) {
  1521. addr = CtlP->AiopIO[0] + 0x88;
  1522. sOutB(addr, 0);
  1523. }
  1524. }
  1525. /***************************************************************************
  1526. Function: sPCIInitController
  1527. Purpose: Initialization of controller global registers and controller
  1528. structure.
  1529. Call: sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize,
  1530. IRQNum,Frequency,PeriodicOnly)
  1531. CONTROLLER_T *CtlP; Ptr to controller structure
  1532. int CtlNum; Controller number
  1533. ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
  1534. This list must be in the order the AIOPs will be found on the
  1535. controller. Once an AIOP in the list is not found, it is
  1536. assumed that there are no more AIOPs on the controller.
  1537. int AiopIOListSize; Number of addresses in AiopIOList
  1538. int IRQNum; Interrupt Request number. Can be any of the following:
  1539. 0: Disable global interrupts
  1540. 3: IRQ 3
  1541. 4: IRQ 4
  1542. 5: IRQ 5
  1543. 9: IRQ 9
  1544. 10: IRQ 10
  1545. 11: IRQ 11
  1546. 12: IRQ 12
  1547. 15: IRQ 15
  1548. Byte_t Frequency: A flag identifying the frequency
  1549. of the periodic interrupt, can be any one of the following:
  1550. FREQ_DIS - periodic interrupt disabled
  1551. FREQ_137HZ - 137 Hertz
  1552. FREQ_69HZ - 69 Hertz
  1553. FREQ_34HZ - 34 Hertz
  1554. FREQ_17HZ - 17 Hertz
  1555. FREQ_9HZ - 9 Hertz
  1556. FREQ_4HZ - 4 Hertz
  1557. If IRQNum is set to 0 the Frequency parameter is
  1558. overidden, it is forced to a value of FREQ_DIS.
  1559. int PeriodicOnly: 1 if all interrupts except the periodic
  1560. interrupt are to be blocked.
  1561. 0 is both the periodic interrupt and
  1562. other channel interrupts are allowed.
  1563. If IRQNum is set to 0 the PeriodicOnly parameter is
  1564. overidden, it is forced to a value of 0.
  1565. Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
  1566. initialization failed.
  1567. Comments:
  1568. If periodic interrupts are to be disabled but AIOP interrupts
  1569. are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
  1570. If interrupts are to be completely disabled set IRQNum to 0.
  1571. Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
  1572. invalid combination.
  1573. This function performs initialization of global interrupt modes,
  1574. but it does not actually enable global interrupts. To enable
  1575. and disable global interrupts use functions sEnGlobalInt() and
  1576. sDisGlobalInt(). Enabling of global interrupts is normally not
  1577. done until all other initializations are complete.
  1578. Even if interrupts are globally enabled, they must also be
  1579. individually enabled for each channel that is to generate
  1580. interrupts.
  1581. Warnings: No range checking on any of the parameters is done.
  1582. No context switches are allowed while executing this function.
  1583. After this function all AIOPs on the controller are disabled,
  1584. they can be enabled with sEnAiop().
  1585. */
  1586. static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
  1587. ByteIO_t * AiopIOList, int AiopIOListSize,
  1588. WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
  1589. int PeriodicOnly, int altChanRingIndicator,
  1590. int UPCIRingInd)
  1591. {
  1592. int i;
  1593. ByteIO_t io;
  1594. CtlP->AltChanRingIndicator = altChanRingIndicator;
  1595. CtlP->UPCIRingInd = UPCIRingInd;
  1596. CtlP->CtlNum = CtlNum;
  1597. CtlP->CtlID = CTLID_0001; /* controller release 1 */
  1598. CtlP->BusType = isPCI; /* controller release 1 */
  1599. if (ConfigIO) {
  1600. CtlP->isUPCI = 1;
  1601. CtlP->PCIIO = ConfigIO + _PCI_9030_INT_CTRL;
  1602. CtlP->PCIIO2 = ConfigIO + _PCI_9030_GPIO_CTRL;
  1603. CtlP->AiopIntrBits = upci_aiop_intr_bits;
  1604. } else {
  1605. CtlP->isUPCI = 0;
  1606. CtlP->PCIIO =
  1607. (WordIO_t) ((ByteIO_t) AiopIOList[0] + _PCI_INT_FUNC);
  1608. CtlP->AiopIntrBits = aiop_intr_bits;
  1609. }
  1610. sPCIControllerEOI(CtlP); /* clear EOI if warm init */
  1611. /* Init AIOPs */
  1612. CtlP->NumAiop = 0;
  1613. for (i = 0; i < AiopIOListSize; i++) {
  1614. io = AiopIOList[i];
  1615. CtlP->AiopIO[i] = (WordIO_t) io;
  1616. CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
  1617. CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
  1618. if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
  1619. break; /* done looking for AIOPs */
  1620. CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
  1621. sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
  1622. sOutB(io + _INDX_DATA, sClockPrescale);
  1623. CtlP->NumAiop++; /* bump count of AIOPs */
  1624. }
  1625. if (CtlP->NumAiop == 0)
  1626. return (-1);
  1627. else
  1628. return (CtlP->NumAiop);
  1629. }
  1630. /*
  1631. * Called when a PCI card is found. Retrieves and stores model information,
  1632. * init's aiopic and serial port hardware.
  1633. * Inputs: i is the board number (0-n)
  1634. */
  1635. static __init int register_PCI(int i, struct pci_dev *dev)
  1636. {
  1637. int num_aiops, aiop, max_num_aiops, chan;
  1638. unsigned int aiopio[MAX_AIOPS_PER_BOARD];
  1639. CONTROLLER_t *ctlp;
  1640. int fast_clock = 0;
  1641. int altChanRingIndicator = 0;
  1642. int ports_per_aiop = 8;
  1643. WordIO_t ConfigIO = 0;
  1644. ByteIO_t UPCIRingInd = 0;
  1645. if (!dev || !pci_match_id(rocket_pci_ids, dev) ||
  1646. pci_enable_device(dev) || i >= NUM_BOARDS)
  1647. return 0;
  1648. rcktpt_io_addr[i] = pci_resource_start(dev, 0);
  1649. rcktpt_type[i] = ROCKET_TYPE_NORMAL;
  1650. rocketModel[i].loadrm2 = 0;
  1651. rocketModel[i].startingPortNumber = nextLineNumber;
  1652. /* Depending on the model, set up some config variables */
  1653. switch (dev->device) {
  1654. case PCI_DEVICE_ID_RP4QUAD:
  1655. max_num_aiops = 1;
  1656. ports_per_aiop = 4;
  1657. rocketModel[i].model = MODEL_RP4QUAD;
  1658. strcpy(rocketModel[i].modelString, "RocketPort 4 port w/quad cable");
  1659. rocketModel[i].numPorts = 4;
  1660. break;
  1661. case PCI_DEVICE_ID_RP8OCTA:
  1662. max_num_aiops = 1;
  1663. rocketModel[i].model = MODEL_RP8OCTA;
  1664. strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable");
  1665. rocketModel[i].numPorts = 8;
  1666. break;
  1667. case PCI_DEVICE_ID_URP8OCTA:
  1668. max_num_aiops = 1;
  1669. rocketModel[i].model = MODEL_UPCI_RP8OCTA;
  1670. strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable");
  1671. rocketModel[i].numPorts = 8;
  1672. break;
  1673. case PCI_DEVICE_ID_RP8INTF:
  1674. max_num_aiops = 1;
  1675. rocketModel[i].model = MODEL_RP8INTF;
  1676. strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F");
  1677. rocketModel[i].numPorts = 8;
  1678. break;
  1679. case PCI_DEVICE_ID_URP8INTF:
  1680. max_num_aiops = 1;
  1681. rocketModel[i].model = MODEL_UPCI_RP8INTF;
  1682. strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F");
  1683. rocketModel[i].numPorts = 8;
  1684. break;
  1685. case PCI_DEVICE_ID_RP8J:
  1686. max_num_aiops = 1;
  1687. rocketModel[i].model = MODEL_RP8J;
  1688. strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors");
  1689. rocketModel[i].numPorts = 8;
  1690. break;
  1691. case PCI_DEVICE_ID_RP4J:
  1692. max_num_aiops = 1;
  1693. ports_per_aiop = 4;
  1694. rocketModel[i].model = MODEL_RP4J;
  1695. strcpy(rocketModel[i].modelString, "RocketPort 4 port w/RJ45 connectors");
  1696. rocketModel[i].numPorts = 4;
  1697. break;
  1698. case PCI_DEVICE_ID_RP8SNI:
  1699. max_num_aiops = 1;
  1700. rocketModel[i].model = MODEL_RP8SNI;
  1701. strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78");
  1702. rocketModel[i].numPorts = 8;
  1703. break;
  1704. case PCI_DEVICE_ID_RP16SNI:
  1705. max_num_aiops = 2;
  1706. rocketModel[i].model = MODEL_RP16SNI;
  1707. strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78");
  1708. rocketModel[i].numPorts = 16;
  1709. break;
  1710. case PCI_DEVICE_ID_RP16INTF:
  1711. max_num_aiops = 2;
  1712. rocketModel[i].model = MODEL_RP16INTF;
  1713. strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F");
  1714. rocketModel[i].numPorts = 16;
  1715. break;
  1716. case PCI_DEVICE_ID_URP16INTF:
  1717. max_num_aiops = 2;
  1718. rocketModel[i].model = MODEL_UPCI_RP16INTF;
  1719. strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F");
  1720. rocketModel[i].numPorts = 16;
  1721. break;
  1722. case PCI_DEVICE_ID_CRP16INTF:
  1723. max_num_aiops = 2;
  1724. rocketModel[i].model = MODEL_CPCI_RP16INTF;
  1725. strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F");
  1726. rocketModel[i].numPorts = 16;
  1727. break;
  1728. case PCI_DEVICE_ID_RP32INTF:
  1729. max_num_aiops = 4;
  1730. rocketModel[i].model = MODEL_RP32INTF;
  1731. strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F");
  1732. rocketModel[i].numPorts = 32;
  1733. break;
  1734. case PCI_DEVICE_ID_URP32INTF:
  1735. max_num_aiops = 4;
  1736. rocketModel[i].model = MODEL_UPCI_RP32INTF;
  1737. strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F");
  1738. rocketModel[i].numPorts = 32;
  1739. break;
  1740. case PCI_DEVICE_ID_RPP4:
  1741. max_num_aiops = 1;
  1742. ports_per_aiop = 4;
  1743. altChanRingIndicator++;
  1744. fast_clock++;
  1745. rocketModel[i].model = MODEL_RPP4;
  1746. strcpy(rocketModel[i].modelString, "RocketPort Plus 4 port");
  1747. rocketModel[i].numPorts = 4;
  1748. break;
  1749. case PCI_DEVICE_ID_RPP8:
  1750. max_num_aiops = 2;
  1751. ports_per_aiop = 4;
  1752. altChanRingIndicator++;
  1753. fast_clock++;
  1754. rocketModel[i].model = MODEL_RPP8;
  1755. strcpy(rocketModel[i].modelString, "RocketPort Plus 8 port");
  1756. rocketModel[i].numPorts = 8;
  1757. break;
  1758. case PCI_DEVICE_ID_RP2_232:
  1759. max_num_aiops = 1;
  1760. ports_per_aiop = 2;
  1761. altChanRingIndicator++;
  1762. fast_clock++;
  1763. rocketModel[i].model = MODEL_RP2_232;
  1764. strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS232");
  1765. rocketModel[i].numPorts = 2;
  1766. break;
  1767. case PCI_DEVICE_ID_RP2_422:
  1768. max_num_aiops = 1;
  1769. ports_per_aiop = 2;
  1770. altChanRingIndicator++;
  1771. fast_clock++;
  1772. rocketModel[i].model = MODEL_RP2_422;
  1773. strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS422");
  1774. rocketModel[i].numPorts = 2;
  1775. break;
  1776. case PCI_DEVICE_ID_RP6M:
  1777. max_num_aiops = 1;
  1778. ports_per_aiop = 6;
  1779. /* If revision is 1, the rocketmodem flash must be loaded.
  1780. * If it is 2 it is a "socketed" version. */
  1781. if (dev->revision == 1) {
  1782. rcktpt_type[i] = ROCKET_TYPE_MODEMII;
  1783. rocketModel[i].loadrm2 = 1;
  1784. } else {
  1785. rcktpt_type[i] = ROCKET_TYPE_MODEM;
  1786. }
  1787. rocketModel[i].model = MODEL_RP6M;
  1788. strcpy(rocketModel[i].modelString, "RocketModem 6 port");
  1789. rocketModel[i].numPorts = 6;
  1790. break;
  1791. case PCI_DEVICE_ID_RP4M:
  1792. max_num_aiops = 1;
  1793. ports_per_aiop = 4;
  1794. if (dev->revision == 1) {
  1795. rcktpt_type[i] = ROCKET_TYPE_MODEMII;
  1796. rocketModel[i].loadrm2 = 1;
  1797. } else {
  1798. rcktpt_type[i] = ROCKET_TYPE_MODEM;
  1799. }
  1800. rocketModel[i].model = MODEL_RP4M;
  1801. strcpy(rocketModel[i].modelString, "RocketModem 4 port");
  1802. rocketModel[i].numPorts = 4;
  1803. break;
  1804. default:
  1805. max_num_aiops = 0;
  1806. break;
  1807. }
  1808. /*
  1809. * Check for UPCI boards.
  1810. */
  1811. switch (dev->device) {
  1812. case PCI_DEVICE_ID_URP32INTF:
  1813. case PCI_DEVICE_ID_URP8INTF:
  1814. case PCI_DEVICE_ID_URP16INTF:
  1815. case PCI_DEVICE_ID_CRP16INTF:
  1816. case PCI_DEVICE_ID_URP8OCTA:
  1817. rcktpt_io_addr[i] = pci_resource_start(dev, 2);
  1818. ConfigIO = pci_resource_start(dev, 1);
  1819. if (dev->device == PCI_DEVICE_ID_URP8OCTA) {
  1820. UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
  1821. /*
  1822. * Check for octa or quad cable.
  1823. */
  1824. if (!
  1825. (sInW(ConfigIO + _PCI_9030_GPIO_CTRL) &
  1826. PCI_GPIO_CTRL_8PORT)) {
  1827. ports_per_aiop = 4;
  1828. rocketModel[i].numPorts = 4;
  1829. }
  1830. }
  1831. break;
  1832. case PCI_DEVICE_ID_UPCI_RM3_8PORT:
  1833. max_num_aiops = 1;
  1834. rocketModel[i].model = MODEL_UPCI_RM3_8PORT;
  1835. strcpy(rocketModel[i].modelString, "RocketModem III 8 port");
  1836. rocketModel[i].numPorts = 8;
  1837. rcktpt_io_addr[i] = pci_resource_start(dev, 2);
  1838. UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
  1839. ConfigIO = pci_resource_start(dev, 1);
  1840. rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
  1841. break;
  1842. case PCI_DEVICE_ID_UPCI_RM3_4PORT:
  1843. max_num_aiops = 1;
  1844. rocketModel[i].model = MODEL_UPCI_RM3_4PORT;
  1845. strcpy(rocketModel[i].modelString, "RocketModem III 4 port");
  1846. rocketModel[i].numPorts = 4;
  1847. rcktpt_io_addr[i] = pci_resource_start(dev, 2);
  1848. UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
  1849. ConfigIO = pci_resource_start(dev, 1);
  1850. rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
  1851. break;
  1852. default:
  1853. break;
  1854. }
  1855. if (fast_clock) {
  1856. sClockPrescale = 0x12; /* mod 2 (divide by 3) */
  1857. rp_baud_base[i] = 921600;
  1858. } else {
  1859. /*
  1860. * If support_low_speed is set, use the slow clock
  1861. * prescale, which supports 50 bps
  1862. */
  1863. if (support_low_speed) {
  1864. /* mod 9 (divide by 10) prescale */
  1865. sClockPrescale = 0x19;
  1866. rp_baud_base[i] = 230400;
  1867. } else {
  1868. /* mod 4 (divide by 5) prescale */
  1869. sClockPrescale = 0x14;
  1870. rp_baud_base[i] = 460800;
  1871. }
  1872. }
  1873. for (aiop = 0; aiop < max_num_aiops; aiop++)
  1874. aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x40);
  1875. ctlp = sCtlNumToCtlPtr(i);
  1876. num_aiops = sPCIInitController(ctlp, i, aiopio, max_num_aiops, ConfigIO, 0, FREQ_DIS, 0, altChanRingIndicator, UPCIRingInd);
  1877. for (aiop = 0; aiop < max_num_aiops; aiop++)
  1878. ctlp->AiopNumChan[aiop] = ports_per_aiop;
  1879. dev_info(&dev->dev, "comtrol PCI controller #%d found at "
  1880. "address %04lx, %d AIOP(s) (%s), creating ttyR%d - %ld\n",
  1881. i, rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString,
  1882. rocketModel[i].startingPortNumber,
  1883. rocketModel[i].startingPortNumber + rocketModel[i].numPorts-1);
  1884. if (num_aiops <= 0) {
  1885. rcktpt_io_addr[i] = 0;
  1886. return (0);
  1887. }
  1888. is_PCI[i] = 1;
  1889. /* Reset the AIOPIC, init the serial ports */
  1890. for (aiop = 0; aiop < num_aiops; aiop++) {
  1891. sResetAiopByNum(ctlp, aiop);
  1892. for (chan = 0; chan < ports_per_aiop; chan++)
  1893. init_r_port(i, aiop, chan, dev);
  1894. }
  1895. /* Rocket modems must be reset */
  1896. if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) ||
  1897. (rcktpt_type[i] == ROCKET_TYPE_MODEMII) ||
  1898. (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) {
  1899. for (chan = 0; chan < ports_per_aiop; chan++)
  1900. sPCIModemReset(ctlp, chan, 1);
  1901. msleep(500);
  1902. for (chan = 0; chan < ports_per_aiop; chan++)
  1903. sPCIModemReset(ctlp, chan, 0);
  1904. msleep(500);
  1905. rmSpeakerReset(ctlp, rocketModel[i].model);
  1906. }
  1907. return (1);
  1908. }
  1909. /*
  1910. * Probes for PCI cards, inits them if found
  1911. * Input: board_found = number of ISA boards already found, or the
  1912. * starting board number
  1913. * Returns: Number of PCI boards found
  1914. */
  1915. static int __init init_PCI(int boards_found)
  1916. {
  1917. struct pci_dev *dev = NULL;
  1918. int count = 0;
  1919. /* Work through the PCI device list, pulling out ours */
  1920. while ((dev = pci_get_device(PCI_VENDOR_ID_RP, PCI_ANY_ID, dev))) {
  1921. if (register_PCI(count + boards_found, dev))
  1922. count++;
  1923. }
  1924. return (count);
  1925. }
  1926. #endif /* CONFIG_PCI */
  1927. /*
  1928. * Probes for ISA cards
  1929. * Input: i = the board number to look for
  1930. * Returns: 1 if board found, 0 else
  1931. */
  1932. static int __init init_ISA(int i)
  1933. {
  1934. int num_aiops, num_chan = 0, total_num_chan = 0;
  1935. int aiop, chan;
  1936. unsigned int aiopio[MAX_AIOPS_PER_BOARD];
  1937. CONTROLLER_t *ctlp;
  1938. char *type_string;
  1939. /* If io_addr is zero, no board configured */
  1940. if (rcktpt_io_addr[i] == 0)
  1941. return (0);
  1942. /* Reserve the IO region */
  1943. if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) {
  1944. printk(KERN_ERR "Unable to reserve IO region for configured "
  1945. "ISA RocketPort at address 0x%lx, board not "
  1946. "installed...\n", rcktpt_io_addr[i]);
  1947. rcktpt_io_addr[i] = 0;
  1948. return (0);
  1949. }
  1950. ctlp = sCtlNumToCtlPtr(i);
  1951. ctlp->boardType = rcktpt_type[i];
  1952. switch (rcktpt_type[i]) {
  1953. case ROCKET_TYPE_PC104:
  1954. type_string = "(PC104)";
  1955. break;
  1956. case ROCKET_TYPE_MODEM:
  1957. type_string = "(RocketModem)";
  1958. break;
  1959. case ROCKET_TYPE_MODEMII:
  1960. type_string = "(RocketModem II)";
  1961. break;
  1962. default:
  1963. type_string = "";
  1964. break;
  1965. }
  1966. /*
  1967. * If support_low_speed is set, use the slow clock prescale,
  1968. * which supports 50 bps
  1969. */
  1970. if (support_low_speed) {
  1971. sClockPrescale = 0x19; /* mod 9 (divide by 10) prescale */
  1972. rp_baud_base[i] = 230400;
  1973. } else {
  1974. sClockPrescale = 0x14; /* mod 4 (divide by 5) prescale */
  1975. rp_baud_base[i] = 460800;
  1976. }
  1977. for (aiop = 0; aiop < MAX_AIOPS_PER_BOARD; aiop++)
  1978. aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x400);
  1979. num_aiops = sInitController(ctlp, i, controller + (i * 0x400), aiopio, MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0);
  1980. if (ctlp->boardType == ROCKET_TYPE_PC104) {
  1981. sEnAiop(ctlp, 2); /* only one AIOPIC, but these */
  1982. sEnAiop(ctlp, 3); /* CSels used for other stuff */
  1983. }
  1984. /* If something went wrong initing the AIOP's release the ISA IO memory */
  1985. if (num_aiops <= 0) {
  1986. release_region(rcktpt_io_addr[i], 64);
  1987. rcktpt_io_addr[i] = 0;
  1988. return (0);
  1989. }
  1990. rocketModel[i].startingPortNumber = nextLineNumber;
  1991. for (aiop = 0; aiop < num_aiops; aiop++) {
  1992. sResetAiopByNum(ctlp, aiop);
  1993. sEnAiop(ctlp, aiop);
  1994. num_chan = sGetAiopNumChan(ctlp, aiop);
  1995. total_num_chan += num_chan;
  1996. for (chan = 0; chan < num_chan; chan++)
  1997. init_r_port(i, aiop, chan, NULL);
  1998. }
  1999. is_PCI[i] = 0;
  2000. if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII)) {
  2001. num_chan = sGetAiopNumChan(ctlp, 0);
  2002. total_num_chan = num_chan;
  2003. for (chan = 0; chan < num_chan; chan++)
  2004. sModemReset(ctlp, chan, 1);
  2005. msleep(500);
  2006. for (chan = 0; chan < num_chan; chan++)
  2007. sModemReset(ctlp, chan, 0);
  2008. msleep(500);
  2009. strcpy(rocketModel[i].modelString, "RocketModem ISA");
  2010. } else {
  2011. strcpy(rocketModel[i].modelString, "RocketPort ISA");
  2012. }
  2013. rocketModel[i].numPorts = total_num_chan;
  2014. rocketModel[i].model = MODEL_ISA;
  2015. printk(KERN_INFO "RocketPort ISA card #%d found at 0x%lx - %d AIOPs %s\n",
  2016. i, rcktpt_io_addr[i], num_aiops, type_string);
  2017. printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
  2018. rocketModel[i].modelString,
  2019. rocketModel[i].startingPortNumber,
  2020. rocketModel[i].startingPortNumber +
  2021. rocketModel[i].numPorts - 1);
  2022. return (1);
  2023. }
  2024. static const struct tty_operations rocket_ops = {
  2025. .open = rp_open,
  2026. .close = rp_close,
  2027. .write = rp_write,
  2028. .put_char = rp_put_char,
  2029. .write_room = rp_write_room,
  2030. .chars_in_buffer = rp_chars_in_buffer,
  2031. .flush_buffer = rp_flush_buffer,
  2032. .ioctl = rp_ioctl,
  2033. .throttle = rp_throttle,
  2034. .unthrottle = rp_unthrottle,
  2035. .set_termios = rp_set_termios,
  2036. .stop = rp_stop,
  2037. .start = rp_start,
  2038. .hangup = rp_hangup,
  2039. .break_ctl = rp_break,
  2040. .send_xchar = rp_send_xchar,
  2041. .wait_until_sent = rp_wait_until_sent,
  2042. .tiocmget = rp_tiocmget,
  2043. .tiocmset = rp_tiocmset,
  2044. };
  2045. static const struct tty_port_operations rocket_port_ops = {
  2046. .carrier_raised = carrier_raised,
  2047. .dtr_rts = dtr_rts,
  2048. };
  2049. /*
  2050. * The module "startup" routine; it's run when the module is loaded.
  2051. */
  2052. static int __init rp_init(void)
  2053. {
  2054. int ret = -ENOMEM, pci_boards_found, isa_boards_found, i;
  2055. printk(KERN_INFO "RocketPort device driver module, version %s, %s\n",
  2056. ROCKET_VERSION, ROCKET_DATE);
  2057. rocket_driver = alloc_tty_driver(MAX_RP_PORTS);
  2058. if (!rocket_driver)
  2059. goto err;
  2060. /*
  2061. * If board 1 is non-zero, there is at least one ISA configured. If controller is
  2062. * zero, use the default controller IO address of board1 + 0x40.
  2063. */
  2064. if (board1) {
  2065. if (controller == 0)
  2066. controller = board1 + 0x40;
  2067. } else {
  2068. controller = 0; /* Used as a flag, meaning no ISA boards */
  2069. }
  2070. /* If an ISA card is configured, reserve the 4 byte IO space for the Mudbac controller */
  2071. if (controller && (!request_region(controller, 4, "Comtrol RocketPort"))) {
  2072. printk(KERN_ERR "Unable to reserve IO region for first "
  2073. "configured ISA RocketPort controller 0x%lx. "
  2074. "Driver exiting\n", controller);
  2075. ret = -EBUSY;
  2076. goto err_tty;
  2077. }
  2078. /* Store ISA variable retrieved from command line or .conf file. */
  2079. rcktpt_io_addr[0] = board1;
  2080. rcktpt_io_addr[1] = board2;
  2081. rcktpt_io_addr[2] = board3;
  2082. rcktpt_io_addr[3] = board4;
  2083. rcktpt_type[0] = modem1 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
  2084. rcktpt_type[0] = pc104_1[0] ? ROCKET_TYPE_PC104 : rcktpt_type[0];
  2085. rcktpt_type[1] = modem2 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
  2086. rcktpt_type[1] = pc104_2[0] ? ROCKET_TYPE_PC104 : rcktpt_type[1];
  2087. rcktpt_type[2] = modem3 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
  2088. rcktpt_type[2] = pc104_3[0] ? ROCKET_TYPE_PC104 : rcktpt_type[2];
  2089. rcktpt_type[3] = modem4 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
  2090. rcktpt_type[3] = pc104_4[0] ? ROCKET_TYPE_PC104 : rcktpt_type[3];
  2091. /*
  2092. * Set up the tty driver structure and then register this
  2093. * driver with the tty layer.
  2094. */
  2095. rocket_driver->flags = TTY_DRIVER_DYNAMIC_DEV;
  2096. rocket_driver->name = "ttyR";
  2097. rocket_driver->driver_name = "Comtrol RocketPort";
  2098. rocket_driver->major = TTY_ROCKET_MAJOR;
  2099. rocket_driver->minor_start = 0;
  2100. rocket_driver->type = TTY_DRIVER_TYPE_SERIAL;
  2101. rocket_driver->subtype = SERIAL_TYPE_NORMAL;
  2102. rocket_driver->init_termios = tty_std_termios;
  2103. rocket_driver->init_termios.c_cflag =
  2104. B9600 | CS8 | CREAD | HUPCL | CLOCAL;
  2105. rocket_driver->init_termios.c_ispeed = 9600;
  2106. rocket_driver->init_termios.c_ospeed = 9600;
  2107. #ifdef ROCKET_SOFT_FLOW
  2108. rocket_driver->flags |= TTY_DRIVER_REAL_RAW;
  2109. #endif
  2110. tty_set_operations(rocket_driver, &rocket_ops);
  2111. ret = tty_register_driver(rocket_driver);
  2112. if (ret < 0) {
  2113. printk(KERN_ERR "Couldn't install tty RocketPort driver\n");
  2114. goto err_controller;
  2115. }
  2116. #ifdef ROCKET_DEBUG_OPEN
  2117. printk(KERN_INFO "RocketPort driver is major %d\n", rocket_driver.major);
  2118. #endif
  2119. /*
  2120. * OK, let's probe each of the controllers looking for boards. Any boards found
  2121. * will be initialized here.
  2122. */
  2123. isa_boards_found = 0;
  2124. pci_boards_found = 0;
  2125. for (i = 0; i < NUM_BOARDS; i++) {
  2126. if (init_ISA(i))
  2127. isa_boards_found++;
  2128. }
  2129. #ifdef CONFIG_PCI
  2130. if (isa_boards_found < NUM_BOARDS)
  2131. pci_boards_found = init_PCI(isa_boards_found);
  2132. #endif
  2133. max_board = pci_boards_found + isa_boards_found;
  2134. if (max_board == 0) {
  2135. printk(KERN_ERR "No rocketport ports found; unloading driver\n");
  2136. ret = -ENXIO;
  2137. goto err_ttyu;
  2138. }
  2139. return 0;
  2140. err_ttyu:
  2141. tty_unregister_driver(rocket_driver);
  2142. err_controller:
  2143. if (controller)
  2144. release_region(controller, 4);
  2145. err_tty:
  2146. put_tty_driver(rocket_driver);
  2147. err:
  2148. return ret;
  2149. }
  2150. static void rp_cleanup_module(void)
  2151. {
  2152. int retval;
  2153. int i;
  2154. del_timer_sync(&rocket_timer);
  2155. retval = tty_unregister_driver(rocket_driver);
  2156. if (retval)
  2157. printk(KERN_ERR "Error %d while trying to unregister "
  2158. "rocketport driver\n", -retval);
  2159. for (i = 0; i < MAX_RP_PORTS; i++)
  2160. if (rp_table[i]) {
  2161. tty_unregister_device(rocket_driver, i);
  2162. tty_port_destroy(&rp_table[i]->port);
  2163. kfree(rp_table[i]);
  2164. }
  2165. put_tty_driver(rocket_driver);
  2166. for (i = 0; i < NUM_BOARDS; i++) {
  2167. if (rcktpt_io_addr[i] <= 0 || is_PCI[i])
  2168. continue;
  2169. release_region(rcktpt_io_addr[i], 64);
  2170. }
  2171. if (controller)
  2172. release_region(controller, 4);
  2173. }
  2174. /***************************************************************************
  2175. Function: sInitController
  2176. Purpose: Initialization of controller global registers and controller
  2177. structure.
  2178. Call: sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize,
  2179. IRQNum,Frequency,PeriodicOnly)
  2180. CONTROLLER_T *CtlP; Ptr to controller structure
  2181. int CtlNum; Controller number
  2182. ByteIO_t MudbacIO; Mudbac base I/O address.
  2183. ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
  2184. This list must be in the order the AIOPs will be found on the
  2185. controller. Once an AIOP in the list is not found, it is
  2186. assumed that there are no more AIOPs on the controller.
  2187. int AiopIOListSize; Number of addresses in AiopIOList
  2188. int IRQNum; Interrupt Request number. Can be any of the following:
  2189. 0: Disable global interrupts
  2190. 3: IRQ 3
  2191. 4: IRQ 4
  2192. 5: IRQ 5
  2193. 9: IRQ 9
  2194. 10: IRQ 10
  2195. 11: IRQ 11
  2196. 12: IRQ 12
  2197. 15: IRQ 15
  2198. Byte_t Frequency: A flag identifying the frequency
  2199. of the periodic interrupt, can be any one of the following:
  2200. FREQ_DIS - periodic interrupt disabled
  2201. FREQ_137HZ - 137 Hertz
  2202. FREQ_69HZ - 69 Hertz
  2203. FREQ_34HZ - 34 Hertz
  2204. FREQ_17HZ - 17 Hertz
  2205. FREQ_9HZ - 9 Hertz
  2206. FREQ_4HZ - 4 Hertz
  2207. If IRQNum is set to 0 the Frequency parameter is
  2208. overidden, it is forced to a value of FREQ_DIS.
  2209. int PeriodicOnly: 1 if all interrupts except the periodic
  2210. interrupt are to be blocked.
  2211. 0 is both the periodic interrupt and
  2212. other channel interrupts are allowed.
  2213. If IRQNum is set to 0 the PeriodicOnly parameter is
  2214. overidden, it is forced to a value of 0.
  2215. Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
  2216. initialization failed.
  2217. Comments:
  2218. If periodic interrupts are to be disabled but AIOP interrupts
  2219. are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
  2220. If interrupts are to be completely disabled set IRQNum to 0.
  2221. Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
  2222. invalid combination.
  2223. This function performs initialization of global interrupt modes,
  2224. but it does not actually enable global interrupts. To enable
  2225. and disable global interrupts use functions sEnGlobalInt() and
  2226. sDisGlobalInt(). Enabling of global interrupts is normally not
  2227. done until all other initializations are complete.
  2228. Even if interrupts are globally enabled, they must also be
  2229. individually enabled for each channel that is to generate
  2230. interrupts.
  2231. Warnings: No range checking on any of the parameters is done.
  2232. No context switches are allowed while executing this function.
  2233. After this function all AIOPs on the controller are disabled,
  2234. they can be enabled with sEnAiop().
  2235. */
  2236. static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
  2237. ByteIO_t * AiopIOList, int AiopIOListSize,
  2238. int IRQNum, Byte_t Frequency, int PeriodicOnly)
  2239. {
  2240. int i;
  2241. ByteIO_t io;
  2242. int done;
  2243. CtlP->AiopIntrBits = aiop_intr_bits;
  2244. CtlP->AltChanRingIndicator = 0;
  2245. CtlP->CtlNum = CtlNum;
  2246. CtlP->CtlID = CTLID_0001; /* controller release 1 */
  2247. CtlP->BusType = isISA;
  2248. CtlP->MBaseIO = MudbacIO;
  2249. CtlP->MReg1IO = MudbacIO + 1;
  2250. CtlP->MReg2IO = MudbacIO + 2;
  2251. CtlP->MReg3IO = MudbacIO + 3;
  2252. #if 1
  2253. CtlP->MReg2 = 0; /* interrupt disable */
  2254. CtlP->MReg3 = 0; /* no periodic interrupts */
  2255. #else
  2256. if (sIRQMap[IRQNum] == 0) { /* interrupts globally disabled */
  2257. CtlP->MReg2 = 0; /* interrupt disable */
  2258. CtlP->MReg3 = 0; /* no periodic interrupts */
  2259. } else {
  2260. CtlP->MReg2 = sIRQMap[IRQNum]; /* set IRQ number */
  2261. CtlP->MReg3 = Frequency; /* set frequency */
  2262. if (PeriodicOnly) { /* periodic interrupt only */
  2263. CtlP->MReg3 |= PERIODIC_ONLY;
  2264. }
  2265. }
  2266. #endif
  2267. sOutB(CtlP->MReg2IO, CtlP->MReg2);
  2268. sOutB(CtlP->MReg3IO, CtlP->MReg3);
  2269. sControllerEOI(CtlP); /* clear EOI if warm init */
  2270. /* Init AIOPs */
  2271. CtlP->NumAiop = 0;
  2272. for (i = done = 0; i < AiopIOListSize; i++) {
  2273. io = AiopIOList[i];
  2274. CtlP->AiopIO[i] = (WordIO_t) io;
  2275. CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
  2276. sOutB(CtlP->MReg2IO, CtlP->MReg2 | (i & 0x03)); /* AIOP index */
  2277. sOutB(MudbacIO, (Byte_t) (io >> 6)); /* set up AIOP I/O in MUDBAC */
  2278. if (done)
  2279. continue;
  2280. sEnAiop(CtlP, i); /* enable the AIOP */
  2281. CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
  2282. if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
  2283. done = 1; /* done looking for AIOPs */
  2284. else {
  2285. CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
  2286. sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
  2287. sOutB(io + _INDX_DATA, sClockPrescale);
  2288. CtlP->NumAiop++; /* bump count of AIOPs */
  2289. }
  2290. sDisAiop(CtlP, i); /* disable AIOP */
  2291. }
  2292. if (CtlP->NumAiop == 0)
  2293. return (-1);
  2294. else
  2295. return (CtlP->NumAiop);
  2296. }
  2297. /***************************************************************************
  2298. Function: sReadAiopID
  2299. Purpose: Read the AIOP idenfication number directly from an AIOP.
  2300. Call: sReadAiopID(io)
  2301. ByteIO_t io: AIOP base I/O address
  2302. Return: int: Flag AIOPID_XXXX if a valid AIOP is found, where X
  2303. is replace by an identifying number.
  2304. Flag AIOPID_NULL if no valid AIOP is found
  2305. Warnings: No context switches are allowed while executing this function.
  2306. */
  2307. static int sReadAiopID(ByteIO_t io)
  2308. {
  2309. Byte_t AiopID; /* ID byte from AIOP */
  2310. sOutB(io + _CMD_REG, RESET_ALL); /* reset AIOP */
  2311. sOutB(io + _CMD_REG, 0x0);
  2312. AiopID = sInW(io + _CHN_STAT0) & 0x07;
  2313. if (AiopID == 0x06)
  2314. return (1);
  2315. else /* AIOP does not exist */
  2316. return (-1);
  2317. }
  2318. /***************************************************************************
  2319. Function: sReadAiopNumChan
  2320. Purpose: Read the number of channels available in an AIOP directly from
  2321. an AIOP.
  2322. Call: sReadAiopNumChan(io)
  2323. WordIO_t io: AIOP base I/O address
  2324. Return: int: The number of channels available
  2325. Comments: The number of channels is determined by write/reads from identical
  2326. offsets within the SRAM address spaces for channels 0 and 4.
  2327. If the channel 4 space is mirrored to channel 0 it is a 4 channel
  2328. AIOP, otherwise it is an 8 channel.
  2329. Warnings: No context switches are allowed while executing this function.
  2330. */
  2331. static int sReadAiopNumChan(WordIO_t io)
  2332. {
  2333. Word_t x;
  2334. static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
  2335. /* write to chan 0 SRAM */
  2336. out32((DWordIO_t) io + _INDX_ADDR, R);
  2337. sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */
  2338. x = sInW(io + _INDX_DATA);
  2339. sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
  2340. if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */
  2341. return (8);
  2342. else
  2343. return (4);
  2344. }
  2345. /***************************************************************************
  2346. Function: sInitChan
  2347. Purpose: Initialization of a channel and channel structure
  2348. Call: sInitChan(CtlP,ChP,AiopNum,ChanNum)
  2349. CONTROLLER_T *CtlP; Ptr to controller structure
  2350. CHANNEL_T *ChP; Ptr to channel structure
  2351. int AiopNum; AIOP number within controller
  2352. int ChanNum; Channel number within AIOP
  2353. Return: int: 1 if initialization succeeded, 0 if it fails because channel
  2354. number exceeds number of channels available in AIOP.
  2355. Comments: This function must be called before a channel can be used.
  2356. Warnings: No range checking on any of the parameters is done.
  2357. No context switches are allowed while executing this function.
  2358. */
  2359. static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
  2360. int ChanNum)
  2361. {
  2362. int i;
  2363. WordIO_t AiopIO;
  2364. WordIO_t ChIOOff;
  2365. Byte_t *ChR;
  2366. Word_t ChOff;
  2367. static Byte_t R[4];
  2368. int brd9600;
  2369. if (ChanNum >= CtlP->AiopNumChan[AiopNum])
  2370. return 0; /* exceeds num chans in AIOP */
  2371. /* Channel, AIOP, and controller identifiers */
  2372. ChP->CtlP = CtlP;
  2373. ChP->ChanID = CtlP->AiopID[AiopNum];
  2374. ChP->AiopNum = AiopNum;
  2375. ChP->ChanNum = ChanNum;
  2376. /* Global direct addresses */
  2377. AiopIO = CtlP->AiopIO[AiopNum];
  2378. ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG;
  2379. ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN;
  2380. ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK;
  2381. ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR;
  2382. ChP->IndexData = AiopIO + _INDX_DATA;
  2383. /* Channel direct addresses */
  2384. ChIOOff = AiopIO + ChP->ChanNum * 2;
  2385. ChP->TxRxData = ChIOOff + _TD0;
  2386. ChP->ChanStat = ChIOOff + _CHN_STAT0;
  2387. ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
  2388. ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0;
  2389. /* Initialize the channel from the RData array */
  2390. for (i = 0; i < RDATASIZE; i += 4) {
  2391. R[0] = RData[i];
  2392. R[1] = RData[i + 1] + 0x10 * ChanNum;
  2393. R[2] = RData[i + 2];
  2394. R[3] = RData[i + 3];
  2395. out32(ChP->IndexAddr, R);
  2396. }
  2397. ChR = ChP->R;
  2398. for (i = 0; i < RREGDATASIZE; i += 4) {
  2399. ChR[i] = RRegData[i];
  2400. ChR[i + 1] = RRegData[i + 1] + 0x10 * ChanNum;
  2401. ChR[i + 2] = RRegData[i + 2];
  2402. ChR[i + 3] = RRegData[i + 3];
  2403. }
  2404. /* Indexed registers */
  2405. ChOff = (Word_t) ChanNum *0x1000;
  2406. if (sClockPrescale == 0x14)
  2407. brd9600 = 47;
  2408. else
  2409. brd9600 = 23;
  2410. ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
  2411. ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
  2412. ChP->BaudDiv[2] = (Byte_t) brd9600;
  2413. ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
  2414. out32(ChP->IndexAddr, ChP->BaudDiv);
  2415. ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
  2416. ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
  2417. ChP->TxControl[2] = 0;
  2418. ChP->TxControl[3] = 0;
  2419. out32(ChP->IndexAddr, ChP->TxControl);
  2420. ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
  2421. ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
  2422. ChP->RxControl[2] = 0;
  2423. ChP->RxControl[3] = 0;
  2424. out32(ChP->IndexAddr, ChP->RxControl);
  2425. ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
  2426. ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
  2427. ChP->TxEnables[2] = 0;
  2428. ChP->TxEnables[3] = 0;
  2429. out32(ChP->IndexAddr, ChP->TxEnables);
  2430. ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
  2431. ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
  2432. ChP->TxCompare[2] = 0;
  2433. ChP->TxCompare[3] = 0;
  2434. out32(ChP->IndexAddr, ChP->TxCompare);
  2435. ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
  2436. ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
  2437. ChP->TxReplace1[2] = 0;
  2438. ChP->TxReplace1[3] = 0;
  2439. out32(ChP->IndexAddr, ChP->TxReplace1);
  2440. ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
  2441. ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
  2442. ChP->TxReplace2[2] = 0;
  2443. ChP->TxReplace2[3] = 0;
  2444. out32(ChP->IndexAddr, ChP->TxReplace2);
  2445. ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
  2446. ChP->TxFIFO = ChOff + _TX_FIFO;
  2447. sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT); /* apply reset Tx FIFO count */
  2448. sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Tx FIFO count */
  2449. sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
  2450. sOutW(ChP->IndexData, 0);
  2451. ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
  2452. ChP->RxFIFO = ChOff + _RX_FIFO;
  2453. sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT); /* apply reset Rx FIFO count */
  2454. sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Rx FIFO count */
  2455. sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
  2456. sOutW(ChP->IndexData, 0);
  2457. sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
  2458. sOutW(ChP->IndexData, 0);
  2459. ChP->TxPrioCnt = ChOff + _TXP_CNT;
  2460. sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
  2461. sOutB(ChP->IndexData, 0);
  2462. ChP->TxPrioPtr = ChOff + _TXP_PNTR;
  2463. sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
  2464. sOutB(ChP->IndexData, 0);
  2465. ChP->TxPrioBuf = ChOff + _TXP_BUF;
  2466. sEnRxProcessor(ChP); /* start the Rx processor */
  2467. return 1;
  2468. }
  2469. /***************************************************************************
  2470. Function: sStopRxProcessor
  2471. Purpose: Stop the receive processor from processing a channel.
  2472. Call: sStopRxProcessor(ChP)
  2473. CHANNEL_T *ChP; Ptr to channel structure
  2474. Comments: The receive processor can be started again with sStartRxProcessor().
  2475. This function causes the receive processor to skip over the
  2476. stopped channel. It does not stop it from processing other channels.
  2477. Warnings: No context switches are allowed while executing this function.
  2478. Do not leave the receive processor stopped for more than one
  2479. character time.
  2480. After calling this function a delay of 4 uS is required to ensure
  2481. that the receive processor is no longer processing this channel.
  2482. */
  2483. static void sStopRxProcessor(CHANNEL_T * ChP)
  2484. {
  2485. Byte_t R[4];
  2486. R[0] = ChP->R[0];
  2487. R[1] = ChP->R[1];
  2488. R[2] = 0x0a;
  2489. R[3] = ChP->R[3];
  2490. out32(ChP->IndexAddr, R);
  2491. }
  2492. /***************************************************************************
  2493. Function: sFlushRxFIFO
  2494. Purpose: Flush the Rx FIFO
  2495. Call: sFlushRxFIFO(ChP)
  2496. CHANNEL_T *ChP; Ptr to channel structure
  2497. Return: void
  2498. Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
  2499. while it is being flushed the receive processor is stopped
  2500. and the transmitter is disabled. After these operations a
  2501. 4 uS delay is done before clearing the pointers to allow
  2502. the receive processor to stop. These items are handled inside
  2503. this function.
  2504. Warnings: No context switches are allowed while executing this function.
  2505. */
  2506. static void sFlushRxFIFO(CHANNEL_T * ChP)
  2507. {
  2508. int i;
  2509. Byte_t Ch; /* channel number within AIOP */
  2510. int RxFIFOEnabled; /* 1 if Rx FIFO enabled */
  2511. if (sGetRxCnt(ChP) == 0) /* Rx FIFO empty */
  2512. return; /* don't need to flush */
  2513. RxFIFOEnabled = 0;
  2514. if (ChP->R[0x32] == 0x08) { /* Rx FIFO is enabled */
  2515. RxFIFOEnabled = 1;
  2516. sDisRxFIFO(ChP); /* disable it */
  2517. for (i = 0; i < 2000 / 200; i++) /* delay 2 uS to allow proc to disable FIFO */
  2518. sInB(ChP->IntChan); /* depends on bus i/o timing */
  2519. }
  2520. sGetChanStatus(ChP); /* clear any pending Rx errors in chan stat */
  2521. Ch = (Byte_t) sGetChanNum(ChP);
  2522. sOutB(ChP->Cmd, Ch | RESRXFCNT); /* apply reset Rx FIFO count */
  2523. sOutB(ChP->Cmd, Ch); /* remove reset Rx FIFO count */
  2524. sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
  2525. sOutW(ChP->IndexData, 0);
  2526. sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
  2527. sOutW(ChP->IndexData, 0);
  2528. if (RxFIFOEnabled)
  2529. sEnRxFIFO(ChP); /* enable Rx FIFO */
  2530. }
  2531. /***************************************************************************
  2532. Function: sFlushTxFIFO
  2533. Purpose: Flush the Tx FIFO
  2534. Call: sFlushTxFIFO(ChP)
  2535. CHANNEL_T *ChP; Ptr to channel structure
  2536. Return: void
  2537. Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
  2538. while it is being flushed the receive processor is stopped
  2539. and the transmitter is disabled. After these operations a
  2540. 4 uS delay is done before clearing the pointers to allow
  2541. the receive processor to stop. These items are handled inside
  2542. this function.
  2543. Warnings: No context switches are allowed while executing this function.
  2544. */
  2545. static void sFlushTxFIFO(CHANNEL_T * ChP)
  2546. {
  2547. int i;
  2548. Byte_t Ch; /* channel number within AIOP */
  2549. int TxEnabled; /* 1 if transmitter enabled */
  2550. if (sGetTxCnt(ChP) == 0) /* Tx FIFO empty */
  2551. return; /* don't need to flush */
  2552. TxEnabled = 0;
  2553. if (ChP->TxControl[3] & TX_ENABLE) {
  2554. TxEnabled = 1;
  2555. sDisTransmit(ChP); /* disable transmitter */
  2556. }
  2557. sStopRxProcessor(ChP); /* stop Rx processor */
  2558. for (i = 0; i < 4000 / 200; i++) /* delay 4 uS to allow proc to stop */
  2559. sInB(ChP->IntChan); /* depends on bus i/o timing */
  2560. Ch = (Byte_t) sGetChanNum(ChP);
  2561. sOutB(ChP->Cmd, Ch | RESTXFCNT); /* apply reset Tx FIFO count */
  2562. sOutB(ChP->Cmd, Ch); /* remove reset Tx FIFO count */
  2563. sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
  2564. sOutW(ChP->IndexData, 0);
  2565. if (TxEnabled)
  2566. sEnTransmit(ChP); /* enable transmitter */
  2567. sStartRxProcessor(ChP); /* restart Rx processor */
  2568. }
  2569. /***************************************************************************
  2570. Function: sWriteTxPrioByte
  2571. Purpose: Write a byte of priority transmit data to a channel
  2572. Call: sWriteTxPrioByte(ChP,Data)
  2573. CHANNEL_T *ChP; Ptr to channel structure
  2574. Byte_t Data; The transmit data byte
  2575. Return: int: 1 if the bytes is successfully written, otherwise 0.
  2576. Comments: The priority byte is transmitted before any data in the Tx FIFO.
  2577. Warnings: No context switches are allowed while executing this function.
  2578. */
  2579. static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
  2580. {
  2581. Byte_t DWBuf[4]; /* buffer for double word writes */
  2582. Word_t *WordPtr; /* must be far because Win SS != DS */
  2583. register DWordIO_t IndexAddr;
  2584. if (sGetTxCnt(ChP) > 1) { /* write it to Tx priority buffer */
  2585. IndexAddr = ChP->IndexAddr;
  2586. sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt); /* get priority buffer status */
  2587. if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */
  2588. return (0); /* nothing sent */
  2589. WordPtr = (Word_t *) (&DWBuf[0]);
  2590. *WordPtr = ChP->TxPrioBuf; /* data byte address */
  2591. DWBuf[2] = Data; /* data byte value */
  2592. out32(IndexAddr, DWBuf); /* write it out */
  2593. *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */
  2594. DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */
  2595. DWBuf[3] = 0; /* priority buffer pointer */
  2596. out32(IndexAddr, DWBuf); /* write it out */
  2597. } else { /* write it to Tx FIFO */
  2598. sWriteTxByte(sGetTxRxDataIO(ChP), Data);
  2599. }
  2600. return (1); /* 1 byte sent */
  2601. }
  2602. /***************************************************************************
  2603. Function: sEnInterrupts
  2604. Purpose: Enable one or more interrupts for a channel
  2605. Call: sEnInterrupts(ChP,Flags)
  2606. CHANNEL_T *ChP; Ptr to channel structure
  2607. Word_t Flags: Interrupt enable flags, can be any combination
  2608. of the following flags:
  2609. TXINT_EN: Interrupt on Tx FIFO empty
  2610. RXINT_EN: Interrupt on Rx FIFO at trigger level (see
  2611. sSetRxTrigger())
  2612. SRCINT_EN: Interrupt on SRC (Special Rx Condition)
  2613. MCINT_EN: Interrupt on modem input change
  2614. CHANINT_EN: Allow channel interrupt signal to the AIOP's
  2615. Interrupt Channel Register.
  2616. Return: void
  2617. Comments: If an interrupt enable flag is set in Flags, that interrupt will be
  2618. enabled. If an interrupt enable flag is not set in Flags, that
  2619. interrupt will not be changed. Interrupts can be disabled with
  2620. function sDisInterrupts().
  2621. This function sets the appropriate bit for the channel in the AIOP's
  2622. Interrupt Mask Register if the CHANINT_EN flag is set. This allows
  2623. this channel's bit to be set in the AIOP's Interrupt Channel Register.
  2624. Interrupts must also be globally enabled before channel interrupts
  2625. will be passed on to the host. This is done with function
  2626. sEnGlobalInt().
  2627. In some cases it may be desirable to disable interrupts globally but
  2628. enable channel interrupts. This would allow the global interrupt
  2629. status register to be used to determine which AIOPs need service.
  2630. */
  2631. static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
  2632. {
  2633. Byte_t Mask; /* Interrupt Mask Register */
  2634. ChP->RxControl[2] |=
  2635. ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
  2636. out32(ChP->IndexAddr, ChP->RxControl);
  2637. ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
  2638. out32(ChP->IndexAddr, ChP->TxControl);
  2639. if (Flags & CHANINT_EN) {
  2640. Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
  2641. sOutB(ChP->IntMask, Mask);
  2642. }
  2643. }
  2644. /***************************************************************************
  2645. Function: sDisInterrupts
  2646. Purpose: Disable one or more interrupts for a channel
  2647. Call: sDisInterrupts(ChP,Flags)
  2648. CHANNEL_T *ChP; Ptr to channel structure
  2649. Word_t Flags: Interrupt flags, can be any combination
  2650. of the following flags:
  2651. TXINT_EN: Interrupt on Tx FIFO empty
  2652. RXINT_EN: Interrupt on Rx FIFO at trigger level (see
  2653. sSetRxTrigger())
  2654. SRCINT_EN: Interrupt on SRC (Special Rx Condition)
  2655. MCINT_EN: Interrupt on modem input change
  2656. CHANINT_EN: Disable channel interrupt signal to the
  2657. AIOP's Interrupt Channel Register.
  2658. Return: void
  2659. Comments: If an interrupt flag is set in Flags, that interrupt will be
  2660. disabled. If an interrupt flag is not set in Flags, that
  2661. interrupt will not be changed. Interrupts can be enabled with
  2662. function sEnInterrupts().
  2663. This function clears the appropriate bit for the channel in the AIOP's
  2664. Interrupt Mask Register if the CHANINT_EN flag is set. This blocks
  2665. this channel's bit from being set in the AIOP's Interrupt Channel
  2666. Register.
  2667. */
  2668. static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
  2669. {
  2670. Byte_t Mask; /* Interrupt Mask Register */
  2671. ChP->RxControl[2] &=
  2672. ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
  2673. out32(ChP->IndexAddr, ChP->RxControl);
  2674. ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
  2675. out32(ChP->IndexAddr, ChP->TxControl);
  2676. if (Flags & CHANINT_EN) {
  2677. Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
  2678. sOutB(ChP->IntMask, Mask);
  2679. }
  2680. }
  2681. static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
  2682. {
  2683. sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);
  2684. }
  2685. /*
  2686. * Not an official SSCI function, but how to reset RocketModems.
  2687. * ISA bus version
  2688. */
  2689. static void sModemReset(CONTROLLER_T * CtlP, int chan, int on)
  2690. {
  2691. ByteIO_t addr;
  2692. Byte_t val;
  2693. addr = CtlP->AiopIO[0] + 0x400;
  2694. val = sInB(CtlP->MReg3IO);
  2695. /* if AIOP[1] is not enabled, enable it */
  2696. if ((val & 2) == 0) {
  2697. val = sInB(CtlP->MReg2IO);
  2698. sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03));
  2699. sOutB(CtlP->MBaseIO, (unsigned char) (addr >> 6));
  2700. }
  2701. sEnAiop(CtlP, 1);
  2702. if (!on)
  2703. addr += 8;
  2704. sOutB(addr + chan, 0); /* apply or remove reset */
  2705. sDisAiop(CtlP, 1);
  2706. }
  2707. /*
  2708. * Not an official SSCI function, but how to reset RocketModems.
  2709. * PCI bus version
  2710. */
  2711. static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on)
  2712. {
  2713. ByteIO_t addr;
  2714. addr = CtlP->AiopIO[0] + 0x40; /* 2nd AIOP */
  2715. if (!on)
  2716. addr += 8;
  2717. sOutB(addr + chan, 0); /* apply or remove reset */
  2718. }
  2719. /* Returns the line number given the controller (board), aiop and channel number */
  2720. static unsigned char GetLineNumber(int ctrl, int aiop, int ch)
  2721. {
  2722. return lineNumbers[(ctrl << 5) | (aiop << 3) | ch];
  2723. }
  2724. /*
  2725. * Stores the line number associated with a given controller (board), aiop
  2726. * and channel number.
  2727. * Returns: The line number assigned
  2728. */
  2729. static unsigned char SetLineNumber(int ctrl, int aiop, int ch)
  2730. {
  2731. lineNumbers[(ctrl << 5) | (aiop << 3) | ch] = nextLineNumber++;
  2732. return (nextLineNumber - 1);
  2733. }