mxser.h 4.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. #ifndef _MXSER_H
  3. #define _MXSER_H
  4. /*
  5. * Semi-public control interfaces
  6. */
  7. /*
  8. * MOXA ioctls
  9. */
  10. #define MOXA 0x400
  11. #define MOXA_GETDATACOUNT (MOXA + 23)
  12. #define MOXA_DIAGNOSE (MOXA + 50)
  13. #define MOXA_CHKPORTENABLE (MOXA + 60)
  14. #define MOXA_HighSpeedOn (MOXA + 61)
  15. #define MOXA_GET_MAJOR (MOXA + 63)
  16. #define MOXA_GETMSTATUS (MOXA + 65)
  17. #define MOXA_SET_OP_MODE (MOXA + 66)
  18. #define MOXA_GET_OP_MODE (MOXA + 67)
  19. #define RS232_MODE 0
  20. #define RS485_2WIRE_MODE 1
  21. #define RS422_MODE 2
  22. #define RS485_4WIRE_MODE 3
  23. #define OP_MODE_MASK 3
  24. #define MOXA_SDS_RSTICOUNTER (MOXA + 69)
  25. #define MOXA_ASPP_OQUEUE (MOXA + 70)
  26. #define MOXA_ASPP_MON (MOXA + 73)
  27. #define MOXA_ASPP_LSTATUS (MOXA + 74)
  28. #define MOXA_ASPP_MON_EXT (MOXA + 75)
  29. #define MOXA_SET_BAUD_METHOD (MOXA + 76)
  30. /* --------------------------------------------------- */
  31. #define NPPI_NOTIFY_PARITY 0x01
  32. #define NPPI_NOTIFY_FRAMING 0x02
  33. #define NPPI_NOTIFY_HW_OVERRUN 0x04
  34. #define NPPI_NOTIFY_SW_OVERRUN 0x08
  35. #define NPPI_NOTIFY_BREAK 0x10
  36. #define NPPI_NOTIFY_CTSHOLD 0x01 /* Tx hold by CTS low */
  37. #define NPPI_NOTIFY_DSRHOLD 0x02 /* Tx hold by DSR low */
  38. #define NPPI_NOTIFY_XOFFHOLD 0x08 /* Tx hold by Xoff received */
  39. #define NPPI_NOTIFY_XOFFXENT 0x10 /* Xoff Sent */
  40. /* follow just for Moxa Must chip define. */
  41. /* */
  42. /* when LCR register (offset 0x03) write following value, */
  43. /* the Must chip will enter enchance mode. And write value */
  44. /* on EFR (offset 0x02) bit 6,7 to change bank. */
  45. #define MOXA_MUST_ENTER_ENCHANCE 0xBF
  46. /* when enhance mode enable, access on general bank register */
  47. #define MOXA_MUST_GDL_REGISTER 0x07
  48. #define MOXA_MUST_GDL_MASK 0x7F
  49. #define MOXA_MUST_GDL_HAS_BAD_DATA 0x80
  50. #define MOXA_MUST_LSR_RERR 0x80 /* error in receive FIFO */
  51. /* enchance register bank select and enchance mode setting register */
  52. /* when LCR register equal to 0xBF */
  53. #define MOXA_MUST_EFR_REGISTER 0x02
  54. /* enchance mode enable */
  55. #define MOXA_MUST_EFR_EFRB_ENABLE 0x10
  56. /* enchance reister bank set 0, 1, 2 */
  57. #define MOXA_MUST_EFR_BANK0 0x00
  58. #define MOXA_MUST_EFR_BANK1 0x40
  59. #define MOXA_MUST_EFR_BANK2 0x80
  60. #define MOXA_MUST_EFR_BANK3 0xC0
  61. #define MOXA_MUST_EFR_BANK_MASK 0xC0
  62. /* set XON1 value register, when LCR=0xBF and change to bank0 */
  63. #define MOXA_MUST_XON1_REGISTER 0x04
  64. /* set XON2 value register, when LCR=0xBF and change to bank0 */
  65. #define MOXA_MUST_XON2_REGISTER 0x05
  66. /* set XOFF1 value register, when LCR=0xBF and change to bank0 */
  67. #define MOXA_MUST_XOFF1_REGISTER 0x06
  68. /* set XOFF2 value register, when LCR=0xBF and change to bank0 */
  69. #define MOXA_MUST_XOFF2_REGISTER 0x07
  70. #define MOXA_MUST_RBRTL_REGISTER 0x04
  71. #define MOXA_MUST_RBRTH_REGISTER 0x05
  72. #define MOXA_MUST_RBRTI_REGISTER 0x06
  73. #define MOXA_MUST_THRTL_REGISTER 0x07
  74. #define MOXA_MUST_ENUM_REGISTER 0x04
  75. #define MOXA_MUST_HWID_REGISTER 0x05
  76. #define MOXA_MUST_ECR_REGISTER 0x06
  77. #define MOXA_MUST_CSR_REGISTER 0x07
  78. /* good data mode enable */
  79. #define MOXA_MUST_FCR_GDA_MODE_ENABLE 0x20
  80. /* only good data put into RxFIFO */
  81. #define MOXA_MUST_FCR_GDA_ONLY_ENABLE 0x10
  82. /* enable CTS interrupt */
  83. #define MOXA_MUST_IER_ECTSI 0x80
  84. /* enable RTS interrupt */
  85. #define MOXA_MUST_IER_ERTSI 0x40
  86. /* enable Xon/Xoff interrupt */
  87. #define MOXA_MUST_IER_XINT 0x20
  88. /* enable GDA interrupt */
  89. #define MOXA_MUST_IER_EGDAI 0x10
  90. #define MOXA_MUST_RECV_ISR (UART_IER_RDI | MOXA_MUST_IER_EGDAI)
  91. /* GDA interrupt pending */
  92. #define MOXA_MUST_IIR_GDA 0x1C
  93. #define MOXA_MUST_IIR_RDA 0x04
  94. #define MOXA_MUST_IIR_RTO 0x0C
  95. #define MOXA_MUST_IIR_LSR 0x06
  96. /* received Xon/Xoff or specical interrupt pending */
  97. #define MOXA_MUST_IIR_XSC 0x10
  98. /* RTS/CTS change state interrupt pending */
  99. #define MOXA_MUST_IIR_RTSCTS 0x20
  100. #define MOXA_MUST_IIR_MASK 0x3E
  101. #define MOXA_MUST_MCR_XON_FLAG 0x40
  102. #define MOXA_MUST_MCR_XON_ANY 0x80
  103. #define MOXA_MUST_MCR_TX_XON 0x08
  104. /* software flow control on chip mask value */
  105. #define MOXA_MUST_EFR_SF_MASK 0x0F
  106. /* send Xon1/Xoff1 */
  107. #define MOXA_MUST_EFR_SF_TX1 0x08
  108. /* send Xon2/Xoff2 */
  109. #define MOXA_MUST_EFR_SF_TX2 0x04
  110. /* send Xon1,Xon2/Xoff1,Xoff2 */
  111. #define MOXA_MUST_EFR_SF_TX12 0x0C
  112. /* don't send Xon/Xoff */
  113. #define MOXA_MUST_EFR_SF_TX_NO 0x00
  114. /* Tx software flow control mask */
  115. #define MOXA_MUST_EFR_SF_TX_MASK 0x0C
  116. /* don't receive Xon/Xoff */
  117. #define MOXA_MUST_EFR_SF_RX_NO 0x00
  118. /* receive Xon1/Xoff1 */
  119. #define MOXA_MUST_EFR_SF_RX1 0x02
  120. /* receive Xon2/Xoff2 */
  121. #define MOXA_MUST_EFR_SF_RX2 0x01
  122. /* receive Xon1,Xon2/Xoff1,Xoff2 */
  123. #define MOXA_MUST_EFR_SF_RX12 0x03
  124. /* Rx software flow control mask */
  125. #define MOXA_MUST_EFR_SF_RX_MASK 0x03
  126. #endif