hvc_dcc.c 6.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /* Copyright (c) 2010, 2014 The Linux Foundation. All rights reserved. */
  3. #include <linux/console.h>
  4. #include <linux/init.h>
  5. #include <linux/kfifo.h>
  6. #include <linux/moduleparam.h>
  7. #include <linux/serial.h>
  8. #include <linux/serial_core.h>
  9. #include <linux/spinlock.h>
  10. #include <asm/dcc.h>
  11. #include <asm/processor.h>
  12. #include "hvc_console.h"
  13. /*
  14. * Disable DCC driver at runtime. Want driver enabled for GKI, but some devices
  15. * do not support the registers and crash when driver pokes the registers
  16. */
  17. static bool enable;
  18. module_param(enable, bool, 0444);
  19. /* DCC Status Bits */
  20. #define DCC_STATUS_RX (1 << 30)
  21. #define DCC_STATUS_TX (1 << 29)
  22. static void dcc_uart_console_putchar(struct uart_port *port, int ch)
  23. {
  24. while (__dcc_getstatus() & DCC_STATUS_TX)
  25. cpu_relax();
  26. __dcc_putchar(ch);
  27. }
  28. static void dcc_early_write(struct console *con, const char *s, unsigned n)
  29. {
  30. struct earlycon_device *dev = con->data;
  31. uart_console_write(&dev->port, s, n, dcc_uart_console_putchar);
  32. }
  33. static int __init dcc_early_console_setup(struct earlycon_device *device,
  34. const char *opt)
  35. {
  36. device->con->write = dcc_early_write;
  37. return 0;
  38. }
  39. EARLYCON_DECLARE(dcc, dcc_early_console_setup);
  40. static int hvc_dcc_put_chars(uint32_t vt, const char *buf, int count)
  41. {
  42. int i;
  43. for (i = 0; i < count; i++) {
  44. while (__dcc_getstatus() & DCC_STATUS_TX)
  45. cpu_relax();
  46. __dcc_putchar(buf[i]);
  47. }
  48. return count;
  49. }
  50. static int hvc_dcc_get_chars(uint32_t vt, char *buf, int count)
  51. {
  52. int i;
  53. for (i = 0; i < count; ++i)
  54. if (__dcc_getstatus() & DCC_STATUS_RX)
  55. buf[i] = __dcc_getchar();
  56. else
  57. break;
  58. return i;
  59. }
  60. /*
  61. * Check if the DCC is enabled. If CONFIG_HVC_DCC_SERIALIZE_SMP is enabled,
  62. * then we assume then this function will be called first on core 0. That
  63. * way, dcc_core0_available will be true only if it's available on core 0.
  64. */
  65. static bool hvc_dcc_check(void)
  66. {
  67. unsigned long time = jiffies + (HZ / 10);
  68. #ifdef CONFIG_HVC_DCC_SERIALIZE_SMP
  69. static bool dcc_core0_available;
  70. /*
  71. * If we're not on core 0, but we previously confirmed that DCC is
  72. * active, then just return true.
  73. */
  74. if (smp_processor_id() && dcc_core0_available)
  75. return true;
  76. #endif
  77. /* Write a test character to check if it is handled */
  78. __dcc_putchar('\n');
  79. while (time_is_after_jiffies(time)) {
  80. if (!(__dcc_getstatus() & DCC_STATUS_TX)) {
  81. #ifdef CONFIG_HVC_DCC_SERIALIZE_SMP
  82. dcc_core0_available = true;
  83. #endif
  84. return true;
  85. }
  86. }
  87. return false;
  88. }
  89. #ifdef CONFIG_HVC_DCC_SERIALIZE_SMP
  90. static void dcc_put_work_fn(struct work_struct *work);
  91. static void dcc_get_work_fn(struct work_struct *work);
  92. static DECLARE_WORK(dcc_pwork, dcc_put_work_fn);
  93. static DECLARE_WORK(dcc_gwork, dcc_get_work_fn);
  94. static DEFINE_SPINLOCK(dcc_lock);
  95. static DEFINE_KFIFO(inbuf, unsigned char, 128);
  96. static DEFINE_KFIFO(outbuf, unsigned char, 1024);
  97. /*
  98. * Workqueue function that writes the output FIFO to the DCC on core 0.
  99. */
  100. static void dcc_put_work_fn(struct work_struct *work)
  101. {
  102. unsigned char ch;
  103. unsigned long irqflags;
  104. spin_lock_irqsave(&dcc_lock, irqflags);
  105. /* While there's data in the output FIFO, write it to the DCC */
  106. while (kfifo_get(&outbuf, &ch))
  107. hvc_dcc_put_chars(0, &ch, 1);
  108. /* While we're at it, check for any input characters */
  109. while (!kfifo_is_full(&inbuf)) {
  110. if (!hvc_dcc_get_chars(0, &ch, 1))
  111. break;
  112. kfifo_put(&inbuf, ch);
  113. }
  114. spin_unlock_irqrestore(&dcc_lock, irqflags);
  115. }
  116. /*
  117. * Workqueue function that reads characters from DCC and puts them into the
  118. * input FIFO.
  119. */
  120. static void dcc_get_work_fn(struct work_struct *work)
  121. {
  122. unsigned char ch;
  123. unsigned long irqflags;
  124. /*
  125. * Read characters from DCC and put them into the input FIFO, as
  126. * long as there is room and we have characters to read.
  127. */
  128. spin_lock_irqsave(&dcc_lock, irqflags);
  129. while (!kfifo_is_full(&inbuf)) {
  130. if (!hvc_dcc_get_chars(0, &ch, 1))
  131. break;
  132. kfifo_put(&inbuf, ch);
  133. }
  134. spin_unlock_irqrestore(&dcc_lock, irqflags);
  135. }
  136. /*
  137. * Write characters directly to the DCC if we're on core 0 and the FIFO
  138. * is empty, or write them to the FIFO if we're not.
  139. */
  140. static int hvc_dcc0_put_chars(uint32_t vt, const char *buf,
  141. int count)
  142. {
  143. int len;
  144. unsigned long irqflags;
  145. spin_lock_irqsave(&dcc_lock, irqflags);
  146. if (smp_processor_id() || (!kfifo_is_empty(&outbuf))) {
  147. len = kfifo_in(&outbuf, buf, count);
  148. spin_unlock_irqrestore(&dcc_lock, irqflags);
  149. /*
  150. * We just push data to the output FIFO, so schedule the
  151. * workqueue that will actually write that data to DCC.
  152. */
  153. schedule_work_on(0, &dcc_pwork);
  154. return len;
  155. }
  156. /*
  157. * If we're already on core 0, and the FIFO is empty, then just
  158. * write the data to DCC.
  159. */
  160. len = hvc_dcc_put_chars(vt, buf, count);
  161. spin_unlock_irqrestore(&dcc_lock, irqflags);
  162. return len;
  163. }
  164. /*
  165. * Read characters directly from the DCC if we're on core 0 and the FIFO
  166. * is empty, or read them from the FIFO if we're not.
  167. */
  168. static int hvc_dcc0_get_chars(uint32_t vt, char *buf, int count)
  169. {
  170. int len;
  171. unsigned long irqflags;
  172. spin_lock_irqsave(&dcc_lock, irqflags);
  173. if (smp_processor_id() || (!kfifo_is_empty(&inbuf))) {
  174. len = kfifo_out(&inbuf, buf, count);
  175. spin_unlock_irqrestore(&dcc_lock, irqflags);
  176. /*
  177. * If the FIFO was empty, there may be characters in the DCC
  178. * that we haven't read yet. Schedule a workqueue to fill
  179. * the input FIFO, so that the next time this function is
  180. * called, we'll have data.
  181. */
  182. if (!len)
  183. schedule_work_on(0, &dcc_gwork);
  184. return len;
  185. }
  186. /*
  187. * If we're already on core 0, and the FIFO is empty, then just
  188. * read the data from DCC.
  189. */
  190. len = hvc_dcc_get_chars(vt, buf, count);
  191. spin_unlock_irqrestore(&dcc_lock, irqflags);
  192. return len;
  193. }
  194. static const struct hv_ops hvc_dcc_get_put_ops = {
  195. .get_chars = hvc_dcc0_get_chars,
  196. .put_chars = hvc_dcc0_put_chars,
  197. };
  198. #else
  199. static const struct hv_ops hvc_dcc_get_put_ops = {
  200. .get_chars = hvc_dcc_get_chars,
  201. .put_chars = hvc_dcc_put_chars,
  202. };
  203. #endif
  204. static int __init hvc_dcc_console_init(void)
  205. {
  206. int ret;
  207. if (!enable || !hvc_dcc_check())
  208. return -ENODEV;
  209. /* Returns -1 if error */
  210. ret = hvc_instantiate(0, 0, &hvc_dcc_get_put_ops);
  211. return ret < 0 ? -ENODEV : 0;
  212. }
  213. console_initcall(hvc_dcc_console_init);
  214. static int __init hvc_dcc_init(void)
  215. {
  216. struct hvc_struct *p;
  217. if (!enable || !hvc_dcc_check())
  218. return -ENODEV;
  219. p = hvc_alloc(0, 0, &hvc_dcc_get_put_ops, 128);
  220. return PTR_ERR_OR_ZERO(p);
  221. }
  222. device_initcall(hvc_dcc_init);