tb_regs.h 13 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Thunderbolt driver - Port/Switch config area registers
  4. *
  5. * Every thunderbolt device consists (logically) of a switch with multiple
  6. * ports. Every port contains up to four config regions (HOPS, PORT, SWITCH,
  7. * COUNTERS) which are used to configure the device.
  8. *
  9. * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
  10. * Copyright (C) 2018, Intel Corporation
  11. */
  12. #ifndef _TB_REGS
  13. #define _TB_REGS
  14. #include <linux/types.h>
  15. #define TB_ROUTE_SHIFT 8 /* number of bits in a port entry of a route */
  16. /*
  17. * TODO: should be 63? But we do not know how to receive frames larger than 256
  18. * bytes at the frame level. (header + checksum = 16, 60*4 = 240)
  19. */
  20. #define TB_MAX_CONFIG_RW_LENGTH 60
  21. enum tb_switch_cap {
  22. TB_SWITCH_CAP_TMU = 0x03,
  23. TB_SWITCH_CAP_VSE = 0x05,
  24. };
  25. enum tb_switch_vse_cap {
  26. TB_VSE_CAP_PLUG_EVENTS = 0x01, /* also EEPROM */
  27. TB_VSE_CAP_TIME2 = 0x03,
  28. TB_VSE_CAP_IECS = 0x04,
  29. TB_VSE_CAP_LINK_CONTROLLER = 0x06, /* also IECS */
  30. };
  31. enum tb_port_cap {
  32. TB_PORT_CAP_PHY = 0x01,
  33. TB_PORT_CAP_POWER = 0x02,
  34. TB_PORT_CAP_TIME1 = 0x03,
  35. TB_PORT_CAP_ADAP = 0x04,
  36. TB_PORT_CAP_VSE = 0x05,
  37. TB_PORT_CAP_USB4 = 0x06,
  38. };
  39. enum tb_port_state {
  40. TB_PORT_DISABLED = 0, /* tb_cap_phy.disable == 1 */
  41. TB_PORT_CONNECTING = 1, /* retry */
  42. TB_PORT_UP = 2,
  43. TB_PORT_UNPLUGGED = 7,
  44. };
  45. /* capability headers */
  46. struct tb_cap_basic {
  47. u8 next;
  48. /* enum tb_cap cap:8; prevent "narrower than values of its type" */
  49. u8 cap; /* if cap == 0x05 then we have a extended capability */
  50. } __packed;
  51. /**
  52. * struct tb_cap_extended_short - Switch extended short capability
  53. * @next: Pointer to the next capability. If @next and @length are zero
  54. * then we have a long cap.
  55. * @cap: Base capability ID (see &enum tb_switch_cap)
  56. * @vsec_id: Vendor specific capability ID (see &enum switch_vse_cap)
  57. * @length: Length of this capability
  58. */
  59. struct tb_cap_extended_short {
  60. u8 next;
  61. u8 cap;
  62. u8 vsec_id;
  63. u8 length;
  64. } __packed;
  65. /**
  66. * struct tb_cap_extended_long - Switch extended long capability
  67. * @zero1: This field should be zero
  68. * @cap: Base capability ID (see &enum tb_switch_cap)
  69. * @vsec_id: Vendor specific capability ID (see &enum switch_vse_cap)
  70. * @zero2: This field should be zero
  71. * @next: Pointer to the next capability
  72. * @length: Length of this capability
  73. */
  74. struct tb_cap_extended_long {
  75. u8 zero1;
  76. u8 cap;
  77. u8 vsec_id;
  78. u8 zero2;
  79. u16 next;
  80. u16 length;
  81. } __packed;
  82. /**
  83. * struct tb_cap_any - Structure capable of hold every capability
  84. * @basic: Basic capability
  85. * @extended_short: Vendor specific capability
  86. * @extended_long: Vendor specific extended capability
  87. */
  88. struct tb_cap_any {
  89. union {
  90. struct tb_cap_basic basic;
  91. struct tb_cap_extended_short extended_short;
  92. struct tb_cap_extended_long extended_long;
  93. };
  94. } __packed;
  95. /* capabilities */
  96. struct tb_cap_link_controller {
  97. struct tb_cap_extended_long cap_header;
  98. u32 count:4; /* number of link controllers */
  99. u32 unknown1:4;
  100. u32 base_offset:8; /*
  101. * offset (into this capability) of the configuration
  102. * area of the first link controller
  103. */
  104. u32 length:12; /* link controller configuration area length */
  105. u32 unknown2:4; /* TODO check that length is correct */
  106. } __packed;
  107. struct tb_cap_phy {
  108. struct tb_cap_basic cap_header;
  109. u32 unknown1:16;
  110. u32 unknown2:14;
  111. bool disable:1;
  112. u32 unknown3:11;
  113. enum tb_port_state state:4;
  114. u32 unknown4:2;
  115. } __packed;
  116. struct tb_eeprom_ctl {
  117. bool clock:1; /* send pulse to transfer one bit */
  118. bool access_low:1; /* set to 0 before access */
  119. bool data_out:1; /* to eeprom */
  120. bool data_in:1; /* from eeprom */
  121. bool access_high:1; /* set to 1 before access */
  122. bool not_present:1; /* should be 0 */
  123. bool unknown1:1;
  124. bool present:1; /* should be 1 */
  125. u32 unknown2:24;
  126. } __packed;
  127. struct tb_cap_plug_events {
  128. struct tb_cap_extended_short cap_header;
  129. u32 __unknown1:2;
  130. u32 plug_events:5;
  131. u32 __unknown2:25;
  132. u32 __unknown3;
  133. u32 __unknown4;
  134. struct tb_eeprom_ctl eeprom_ctl;
  135. u32 __unknown5[7];
  136. u32 drom_offset; /* 32 bit register, but eeprom addresses are 16 bit */
  137. } __packed;
  138. /* device headers */
  139. /* Present on port 0 in TB_CFG_SWITCH at address zero. */
  140. struct tb_regs_switch_header {
  141. /* DWORD 0 */
  142. u16 vendor_id;
  143. u16 device_id;
  144. /* DWORD 1 */
  145. u32 first_cap_offset:8;
  146. u32 upstream_port_number:6;
  147. u32 max_port_number:6;
  148. u32 depth:3;
  149. u32 __unknown1:1;
  150. u32 revision:8;
  151. /* DWORD 2 */
  152. u32 route_lo;
  153. /* DWORD 3 */
  154. u32 route_hi:31;
  155. bool enabled:1;
  156. /* DWORD 4 */
  157. u32 plug_events_delay:8; /*
  158. * RW, pause between plug events in
  159. * milliseconds. Writing 0x00 is interpreted
  160. * as 255ms.
  161. */
  162. u32 cmuv:8;
  163. u32 __unknown4:8;
  164. u32 thunderbolt_version:8;
  165. } __packed;
  166. /* USB4 version 1.0 */
  167. #define USB4_VERSION_1_0 0x20
  168. #define ROUTER_CS_1 0x01
  169. #define ROUTER_CS_4 0x04
  170. #define ROUTER_CS_5 0x05
  171. #define ROUTER_CS_5_SLP BIT(0)
  172. #define ROUTER_CS_5_WOP BIT(1)
  173. #define ROUTER_CS_5_WOU BIT(2)
  174. #define ROUTER_CS_5_C3S BIT(23)
  175. #define ROUTER_CS_5_PTO BIT(24)
  176. #define ROUTER_CS_5_UTO BIT(25)
  177. #define ROUTER_CS_5_HCO BIT(26)
  178. #define ROUTER_CS_5_CV BIT(31)
  179. #define ROUTER_CS_6 0x06
  180. #define ROUTER_CS_6_SLPR BIT(0)
  181. #define ROUTER_CS_6_TNS BIT(1)
  182. #define ROUTER_CS_6_WOPS BIT(2)
  183. #define ROUTER_CS_6_WOUS BIT(3)
  184. #define ROUTER_CS_6_HCI BIT(18)
  185. #define ROUTER_CS_6_CR BIT(25)
  186. #define ROUTER_CS_7 0x07
  187. #define ROUTER_CS_9 0x09
  188. #define ROUTER_CS_25 0x19
  189. #define ROUTER_CS_26 0x1a
  190. #define ROUTER_CS_26_STATUS_MASK GENMASK(29, 24)
  191. #define ROUTER_CS_26_STATUS_SHIFT 24
  192. #define ROUTER_CS_26_ONS BIT(30)
  193. #define ROUTER_CS_26_OV BIT(31)
  194. /* Router TMU configuration */
  195. #define TMU_RTR_CS_0 0x00
  196. #define TMU_RTR_CS_0_TD BIT(27)
  197. #define TMU_RTR_CS_0_UCAP BIT(30)
  198. #define TMU_RTR_CS_1 0x01
  199. #define TMU_RTR_CS_1_LOCAL_TIME_NS_MASK GENMASK(31, 16)
  200. #define TMU_RTR_CS_1_LOCAL_TIME_NS_SHIFT 16
  201. #define TMU_RTR_CS_2 0x02
  202. #define TMU_RTR_CS_3 0x03
  203. #define TMU_RTR_CS_3_LOCAL_TIME_NS_MASK GENMASK(15, 0)
  204. #define TMU_RTR_CS_3_TS_PACKET_INTERVAL_MASK GENMASK(31, 16)
  205. #define TMU_RTR_CS_3_TS_PACKET_INTERVAL_SHIFT 16
  206. #define TMU_RTR_CS_22 0x16
  207. #define TMU_RTR_CS_24 0x18
  208. enum tb_port_type {
  209. TB_TYPE_INACTIVE = 0x000000,
  210. TB_TYPE_PORT = 0x000001,
  211. TB_TYPE_NHI = 0x000002,
  212. /* TB_TYPE_ETHERNET = 0x020000, lower order bits are not known */
  213. /* TB_TYPE_SATA = 0x080000, lower order bits are not known */
  214. TB_TYPE_DP_HDMI_IN = 0x0e0101,
  215. TB_TYPE_DP_HDMI_OUT = 0x0e0102,
  216. TB_TYPE_PCIE_DOWN = 0x100101,
  217. TB_TYPE_PCIE_UP = 0x100102,
  218. TB_TYPE_USB3_DOWN = 0x200101,
  219. TB_TYPE_USB3_UP = 0x200102,
  220. };
  221. /* Present on every port in TB_CF_PORT at address zero. */
  222. struct tb_regs_port_header {
  223. /* DWORD 0 */
  224. u16 vendor_id;
  225. u16 device_id;
  226. /* DWORD 1 */
  227. u32 first_cap_offset:8;
  228. u32 max_counters:11;
  229. u32 counters_support:1;
  230. u32 __unknown1:4;
  231. u32 revision:8;
  232. /* DWORD 2 */
  233. enum tb_port_type type:24;
  234. u32 thunderbolt_version:8;
  235. /* DWORD 3 */
  236. u32 __unknown2:20;
  237. u32 port_number:6;
  238. u32 __unknown3:6;
  239. /* DWORD 4 */
  240. u32 nfc_credits;
  241. /* DWORD 5 */
  242. u32 max_in_hop_id:11;
  243. u32 max_out_hop_id:11;
  244. u32 __unknown4:10;
  245. /* DWORD 6 */
  246. u32 __unknown5;
  247. /* DWORD 7 */
  248. u32 __unknown6;
  249. } __packed;
  250. /* Basic adapter configuration registers */
  251. #define ADP_CS_4 0x04
  252. #define ADP_CS_4_NFC_BUFFERS_MASK GENMASK(9, 0)
  253. #define ADP_CS_4_TOTAL_BUFFERS_MASK GENMASK(29, 20)
  254. #define ADP_CS_4_TOTAL_BUFFERS_SHIFT 20
  255. #define ADP_CS_4_LCK BIT(31)
  256. #define ADP_CS_5 0x05
  257. #define ADP_CS_5_LCA_MASK GENMASK(28, 22)
  258. #define ADP_CS_5_LCA_SHIFT 22
  259. /* TMU adapter registers */
  260. #define TMU_ADP_CS_3 0x03
  261. #define TMU_ADP_CS_3_UDM BIT(29)
  262. /* Lane adapter registers */
  263. #define LANE_ADP_CS_0 0x00
  264. #define LANE_ADP_CS_0_SUPPORTED_WIDTH_MASK GENMASK(25, 20)
  265. #define LANE_ADP_CS_0_SUPPORTED_WIDTH_SHIFT 20
  266. #define LANE_ADP_CS_1 0x01
  267. #define LANE_ADP_CS_1_TARGET_WIDTH_MASK GENMASK(9, 4)
  268. #define LANE_ADP_CS_1_TARGET_WIDTH_SHIFT 4
  269. #define LANE_ADP_CS_1_TARGET_WIDTH_SINGLE 0x1
  270. #define LANE_ADP_CS_1_TARGET_WIDTH_DUAL 0x3
  271. #define LANE_ADP_CS_1_LD BIT(14)
  272. #define LANE_ADP_CS_1_LB BIT(15)
  273. #define LANE_ADP_CS_1_CURRENT_SPEED_MASK GENMASK(19, 16)
  274. #define LANE_ADP_CS_1_CURRENT_SPEED_SHIFT 16
  275. #define LANE_ADP_CS_1_CURRENT_SPEED_GEN2 0x8
  276. #define LANE_ADP_CS_1_CURRENT_SPEED_GEN3 0x4
  277. #define LANE_ADP_CS_1_CURRENT_WIDTH_MASK GENMASK(25, 20)
  278. #define LANE_ADP_CS_1_CURRENT_WIDTH_SHIFT 20
  279. /* USB4 port registers */
  280. #define PORT_CS_1 0x01
  281. #define PORT_CS_1_LENGTH_SHIFT 8
  282. #define PORT_CS_1_TARGET_MASK GENMASK(18, 16)
  283. #define PORT_CS_1_TARGET_SHIFT 16
  284. #define PORT_CS_1_RETIMER_INDEX_SHIFT 20
  285. #define PORT_CS_1_WNR_WRITE BIT(24)
  286. #define PORT_CS_1_NR BIT(25)
  287. #define PORT_CS_1_RC BIT(26)
  288. #define PORT_CS_1_PND BIT(31)
  289. #define PORT_CS_2 0x02
  290. #define PORT_CS_18 0x12
  291. #define PORT_CS_18_BE BIT(8)
  292. #define PORT_CS_18_TCM BIT(9)
  293. #define PORT_CS_18_WOU4S BIT(18)
  294. #define PORT_CS_19 0x13
  295. #define PORT_CS_19_PC BIT(3)
  296. #define PORT_CS_19_PID BIT(4)
  297. #define PORT_CS_19_WOC BIT(16)
  298. #define PORT_CS_19_WOD BIT(17)
  299. #define PORT_CS_19_WOU4 BIT(18)
  300. /* Display Port adapter registers */
  301. #define ADP_DP_CS_0 0x00
  302. #define ADP_DP_CS_0_VIDEO_HOPID_MASK GENMASK(26, 16)
  303. #define ADP_DP_CS_0_VIDEO_HOPID_SHIFT 16
  304. #define ADP_DP_CS_0_AE BIT(30)
  305. #define ADP_DP_CS_0_VE BIT(31)
  306. #define ADP_DP_CS_1_AUX_TX_HOPID_MASK GENMASK(10, 0)
  307. #define ADP_DP_CS_1_AUX_RX_HOPID_MASK GENMASK(21, 11)
  308. #define ADP_DP_CS_1_AUX_RX_HOPID_SHIFT 11
  309. #define ADP_DP_CS_2 0x02
  310. #define ADP_DP_CS_2_HDP BIT(6)
  311. #define ADP_DP_CS_3 0x03
  312. #define ADP_DP_CS_3_HDPC BIT(9)
  313. #define DP_LOCAL_CAP 0x04
  314. #define DP_REMOTE_CAP 0x05
  315. #define DP_STATUS_CTRL 0x06
  316. #define DP_STATUS_CTRL_CMHS BIT(25)
  317. #define DP_STATUS_CTRL_UF BIT(26)
  318. #define DP_COMMON_CAP 0x07
  319. /*
  320. * DP_COMMON_CAP offsets work also for DP_LOCAL_CAP and DP_REMOTE_CAP
  321. * with exception of DPRX done.
  322. */
  323. #define DP_COMMON_CAP_RATE_MASK GENMASK(11, 8)
  324. #define DP_COMMON_CAP_RATE_SHIFT 8
  325. #define DP_COMMON_CAP_RATE_RBR 0x0
  326. #define DP_COMMON_CAP_RATE_HBR 0x1
  327. #define DP_COMMON_CAP_RATE_HBR2 0x2
  328. #define DP_COMMON_CAP_RATE_HBR3 0x3
  329. #define DP_COMMON_CAP_LANES_MASK GENMASK(14, 12)
  330. #define DP_COMMON_CAP_LANES_SHIFT 12
  331. #define DP_COMMON_CAP_1_LANE 0x0
  332. #define DP_COMMON_CAP_2_LANES 0x1
  333. #define DP_COMMON_CAP_4_LANES 0x2
  334. #define DP_COMMON_CAP_DPRX_DONE BIT(31)
  335. /* PCIe adapter registers */
  336. #define ADP_PCIE_CS_0 0x00
  337. #define ADP_PCIE_CS_0_PE BIT(31)
  338. /* USB adapter registers */
  339. #define ADP_USB3_CS_0 0x00
  340. #define ADP_USB3_CS_0_V BIT(30)
  341. #define ADP_USB3_CS_0_PE BIT(31)
  342. #define ADP_USB3_CS_1 0x01
  343. #define ADP_USB3_CS_1_CUBW_MASK GENMASK(11, 0)
  344. #define ADP_USB3_CS_1_CDBW_MASK GENMASK(23, 12)
  345. #define ADP_USB3_CS_1_CDBW_SHIFT 12
  346. #define ADP_USB3_CS_1_HCA BIT(31)
  347. #define ADP_USB3_CS_2 0x02
  348. #define ADP_USB3_CS_2_AUBW_MASK GENMASK(11, 0)
  349. #define ADP_USB3_CS_2_ADBW_MASK GENMASK(23, 12)
  350. #define ADP_USB3_CS_2_ADBW_SHIFT 12
  351. #define ADP_USB3_CS_2_CMR BIT(31)
  352. #define ADP_USB3_CS_3 0x03
  353. #define ADP_USB3_CS_3_SCALE_MASK GENMASK(5, 0)
  354. #define ADP_USB3_CS_4 0x04
  355. #define ADP_USB3_CS_4_ALR_MASK GENMASK(6, 0)
  356. #define ADP_USB3_CS_4_ALR_20G 0x1
  357. #define ADP_USB3_CS_4_ULV BIT(7)
  358. #define ADP_USB3_CS_4_MSLR_MASK GENMASK(18, 12)
  359. #define ADP_USB3_CS_4_MSLR_SHIFT 12
  360. #define ADP_USB3_CS_4_MSLR_20G 0x1
  361. /* Hop register from TB_CFG_HOPS. 8 byte per entry. */
  362. struct tb_regs_hop {
  363. /* DWORD 0 */
  364. u32 next_hop:11; /*
  365. * hop to take after sending the packet through
  366. * out_port (on the incoming port of the next switch)
  367. */
  368. u32 out_port:6; /* next port of the path (on the same switch) */
  369. u32 initial_credits:8;
  370. u32 unknown1:6; /* set to zero */
  371. bool enable:1;
  372. /* DWORD 1 */
  373. u32 weight:4;
  374. u32 unknown2:4; /* set to zero */
  375. u32 priority:3;
  376. bool drop_packages:1;
  377. u32 counter:11; /* index into TB_CFG_COUNTERS on this port */
  378. bool counter_enable:1;
  379. bool ingress_fc:1;
  380. bool egress_fc:1;
  381. bool ingress_shared_buffer:1;
  382. bool egress_shared_buffer:1;
  383. bool pending:1;
  384. u32 unknown3:3; /* set to zero */
  385. } __packed;
  386. /* Common link controller registers */
  387. #define TB_LC_DESC 0x02
  388. #define TB_LC_DESC_NLC_MASK GENMASK(3, 0)
  389. #define TB_LC_DESC_SIZE_SHIFT 8
  390. #define TB_LC_DESC_SIZE_MASK GENMASK(15, 8)
  391. #define TB_LC_DESC_PORT_SIZE_SHIFT 16
  392. #define TB_LC_DESC_PORT_SIZE_MASK GENMASK(27, 16)
  393. #define TB_LC_FUSE 0x03
  394. #define TB_LC_SNK_ALLOCATION 0x10
  395. #define TB_LC_SNK_ALLOCATION_SNK0_MASK GENMASK(3, 0)
  396. #define TB_LC_SNK_ALLOCATION_SNK0_CM 0x1
  397. #define TB_LC_SNK_ALLOCATION_SNK1_SHIFT 4
  398. #define TB_LC_SNK_ALLOCATION_SNK1_MASK GENMASK(7, 4)
  399. #define TB_LC_SNK_ALLOCATION_SNK1_CM 0x1
  400. #define TB_LC_POWER 0x740
  401. /* Link controller registers */
  402. #define TB_LC_PORT_ATTR 0x8d
  403. #define TB_LC_PORT_ATTR_BE BIT(12)
  404. #define TB_LC_SX_CTRL 0x96
  405. #define TB_LC_SX_CTRL_WOC BIT(1)
  406. #define TB_LC_SX_CTRL_WOD BIT(2)
  407. #define TB_LC_SX_CTRL_WOU4 BIT(5)
  408. #define TB_LC_SX_CTRL_WOP BIT(6)
  409. #define TB_LC_SX_CTRL_L1C BIT(16)
  410. #define TB_LC_SX_CTRL_L1D BIT(17)
  411. #define TB_LC_SX_CTRL_L2C BIT(20)
  412. #define TB_LC_SX_CTRL_L2D BIT(21)
  413. #define TB_LC_SX_CTRL_UPSTREAM BIT(30)
  414. #define TB_LC_SX_CTRL_SLP BIT(31)
  415. #endif