nhi_ops.c 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * NHI specific operations
  4. *
  5. * Copyright (C) 2019, Intel Corporation
  6. * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
  7. */
  8. #include <linux/delay.h>
  9. #include <linux/suspend.h>
  10. #include "nhi.h"
  11. #include "nhi_regs.h"
  12. #include "tb.h"
  13. /* Ice Lake specific NHI operations */
  14. #define ICL_LC_MAILBOX_TIMEOUT 500 /* ms */
  15. static int check_for_device(struct device *dev, void *data)
  16. {
  17. return tb_is_switch(dev);
  18. }
  19. static bool icl_nhi_is_device_connected(struct tb_nhi *nhi)
  20. {
  21. struct tb *tb = pci_get_drvdata(nhi->pdev);
  22. int ret;
  23. ret = device_for_each_child(&tb->root_switch->dev, NULL,
  24. check_for_device);
  25. return ret > 0;
  26. }
  27. static int icl_nhi_force_power(struct tb_nhi *nhi, bool power)
  28. {
  29. u32 vs_cap;
  30. /*
  31. * The Thunderbolt host controller is present always in Ice Lake
  32. * but the firmware may not be loaded and running (depending
  33. * whether there is device connected and so on). Each time the
  34. * controller is used we need to "Force Power" it first and wait
  35. * for the firmware to indicate it is up and running. This "Force
  36. * Power" is really not about actually powering on/off the
  37. * controller so it is accessible even if "Force Power" is off.
  38. *
  39. * The actual power management happens inside shared ACPI power
  40. * resources using standard ACPI methods.
  41. */
  42. pci_read_config_dword(nhi->pdev, VS_CAP_22, &vs_cap);
  43. if (power) {
  44. vs_cap &= ~VS_CAP_22_DMA_DELAY_MASK;
  45. vs_cap |= 0x22 << VS_CAP_22_DMA_DELAY_SHIFT;
  46. vs_cap |= VS_CAP_22_FORCE_POWER;
  47. } else {
  48. vs_cap &= ~VS_CAP_22_FORCE_POWER;
  49. }
  50. pci_write_config_dword(nhi->pdev, VS_CAP_22, vs_cap);
  51. if (power) {
  52. unsigned int retries = 350;
  53. u32 val;
  54. /* Wait until the firmware tells it is up and running */
  55. do {
  56. pci_read_config_dword(nhi->pdev, VS_CAP_9, &val);
  57. if (val & VS_CAP_9_FW_READY)
  58. return 0;
  59. usleep_range(3000, 3100);
  60. } while (--retries);
  61. return -ETIMEDOUT;
  62. }
  63. return 0;
  64. }
  65. static void icl_nhi_lc_mailbox_cmd(struct tb_nhi *nhi, enum icl_lc_mailbox_cmd cmd)
  66. {
  67. u32 data;
  68. data = (cmd << VS_CAP_19_CMD_SHIFT) & VS_CAP_19_CMD_MASK;
  69. pci_write_config_dword(nhi->pdev, VS_CAP_19, data | VS_CAP_19_VALID);
  70. }
  71. static int icl_nhi_lc_mailbox_cmd_complete(struct tb_nhi *nhi, int timeout)
  72. {
  73. unsigned long end;
  74. u32 data;
  75. if (!timeout)
  76. goto clear;
  77. end = jiffies + msecs_to_jiffies(timeout);
  78. do {
  79. pci_read_config_dword(nhi->pdev, VS_CAP_18, &data);
  80. if (data & VS_CAP_18_DONE)
  81. goto clear;
  82. usleep_range(1000, 1100);
  83. } while (time_before(jiffies, end));
  84. return -ETIMEDOUT;
  85. clear:
  86. /* Clear the valid bit */
  87. pci_write_config_dword(nhi->pdev, VS_CAP_19, 0);
  88. return 0;
  89. }
  90. static void icl_nhi_set_ltr(struct tb_nhi *nhi)
  91. {
  92. u32 max_ltr, ltr;
  93. pci_read_config_dword(nhi->pdev, VS_CAP_16, &max_ltr);
  94. max_ltr &= 0xffff;
  95. /* Program the same value for both snoop and no-snoop */
  96. ltr = max_ltr << 16 | max_ltr;
  97. pci_write_config_dword(nhi->pdev, VS_CAP_15, ltr);
  98. }
  99. static int icl_nhi_suspend(struct tb_nhi *nhi)
  100. {
  101. struct tb *tb = pci_get_drvdata(nhi->pdev);
  102. int ret;
  103. if (icl_nhi_is_device_connected(nhi))
  104. return 0;
  105. if (tb_switch_is_icm(tb->root_switch)) {
  106. /*
  107. * If there is no device connected we need to perform
  108. * both: a handshake through LC mailbox and force power
  109. * down before entering D3.
  110. */
  111. icl_nhi_lc_mailbox_cmd(nhi, ICL_LC_PREPARE_FOR_RESET);
  112. ret = icl_nhi_lc_mailbox_cmd_complete(nhi, ICL_LC_MAILBOX_TIMEOUT);
  113. if (ret)
  114. return ret;
  115. }
  116. return icl_nhi_force_power(nhi, false);
  117. }
  118. static int icl_nhi_suspend_noirq(struct tb_nhi *nhi, bool wakeup)
  119. {
  120. struct tb *tb = pci_get_drvdata(nhi->pdev);
  121. enum icl_lc_mailbox_cmd cmd;
  122. if (!pm_suspend_via_firmware())
  123. return icl_nhi_suspend(nhi);
  124. if (!tb_switch_is_icm(tb->root_switch))
  125. return 0;
  126. cmd = wakeup ? ICL_LC_GO2SX : ICL_LC_GO2SX_NO_WAKE;
  127. icl_nhi_lc_mailbox_cmd(nhi, cmd);
  128. return icl_nhi_lc_mailbox_cmd_complete(nhi, ICL_LC_MAILBOX_TIMEOUT);
  129. }
  130. static int icl_nhi_resume(struct tb_nhi *nhi)
  131. {
  132. int ret;
  133. ret = icl_nhi_force_power(nhi, true);
  134. if (ret)
  135. return ret;
  136. icl_nhi_set_ltr(nhi);
  137. return 0;
  138. }
  139. static void icl_nhi_shutdown(struct tb_nhi *nhi)
  140. {
  141. icl_nhi_force_power(nhi, false);
  142. }
  143. const struct tb_nhi_ops icl_nhi_ops = {
  144. .init = icl_nhi_resume,
  145. .suspend_noirq = icl_nhi_suspend_noirq,
  146. .resume_noirq = icl_nhi_resume,
  147. .runtime_suspend = icl_nhi_suspend,
  148. .runtime_resume = icl_nhi_resume,
  149. .shutdown = icl_nhi_shutdown,
  150. };