nhi.h 2.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Thunderbolt driver - NHI driver
  4. *
  5. * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
  6. * Copyright (C) 2018, Intel Corporation
  7. */
  8. #ifndef DSL3510_H_
  9. #define DSL3510_H_
  10. #include <linux/thunderbolt.h>
  11. enum nhi_fw_mode {
  12. NHI_FW_SAFE_MODE,
  13. NHI_FW_AUTH_MODE,
  14. NHI_FW_EP_MODE,
  15. NHI_FW_CM_MODE,
  16. };
  17. enum nhi_mailbox_cmd {
  18. NHI_MAILBOX_SAVE_DEVS = 0x05,
  19. NHI_MAILBOX_DISCONNECT_PCIE_PATHS = 0x06,
  20. NHI_MAILBOX_DRV_UNLOADS = 0x07,
  21. NHI_MAILBOX_DISCONNECT_PA = 0x10,
  22. NHI_MAILBOX_DISCONNECT_PB = 0x11,
  23. NHI_MAILBOX_ALLOW_ALL_DEVS = 0x23,
  24. };
  25. int nhi_mailbox_cmd(struct tb_nhi *nhi, enum nhi_mailbox_cmd cmd, u32 data);
  26. enum nhi_fw_mode nhi_mailbox_mode(struct tb_nhi *nhi);
  27. /**
  28. * struct tb_nhi_ops - NHI specific optional operations
  29. * @init: NHI specific initialization
  30. * @suspend_noirq: NHI specific suspend_noirq hook
  31. * @resume_noirq: NHI specific resume_noirq hook
  32. * @runtime_suspend: NHI specific runtime_suspend hook
  33. * @runtime_resume: NHI specific runtime_resume hook
  34. * @shutdown: NHI specific shutdown
  35. */
  36. struct tb_nhi_ops {
  37. int (*init)(struct tb_nhi *nhi);
  38. int (*suspend_noirq)(struct tb_nhi *nhi, bool wakeup);
  39. int (*resume_noirq)(struct tb_nhi *nhi);
  40. int (*runtime_suspend)(struct tb_nhi *nhi);
  41. int (*runtime_resume)(struct tb_nhi *nhi);
  42. void (*shutdown)(struct tb_nhi *nhi);
  43. };
  44. extern const struct tb_nhi_ops icl_nhi_ops;
  45. /*
  46. * PCI IDs used in this driver from Win Ridge forward. There is no
  47. * need for the PCI quirk anymore as we will use ICM also on Apple
  48. * hardware.
  49. */
  50. #define PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_NHI 0x157d
  51. #define PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_BRIDGE 0x157e
  52. #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI 0x15bf
  53. #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_BRIDGE 0x15c0
  54. #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI 0x15d2
  55. #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_BRIDGE 0x15d3
  56. #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI 0x15d9
  57. #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_BRIDGE 0x15da
  58. #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI 0x15dc
  59. #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI 0x15dd
  60. #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI 0x15de
  61. #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_BRIDGE 0x15e7
  62. #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_NHI 0x15e8
  63. #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_BRIDGE 0x15ea
  64. #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_NHI 0x15eb
  65. #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_BRIDGE 0x15ef
  66. #define PCI_DEVICE_ID_INTEL_ICL_NHI1 0x8a0d
  67. #define PCI_DEVICE_ID_INTEL_ICL_NHI0 0x8a17
  68. #define PCI_DEVICE_ID_INTEL_TGL_NHI0 0x9a1b
  69. #define PCI_DEVICE_ID_INTEL_TGL_NHI1 0x9a1d
  70. #define PCI_DEVICE_ID_INTEL_TGL_H_NHI0 0x9a1f
  71. #define PCI_DEVICE_ID_INTEL_TGL_H_NHI1 0x9a21
  72. #define PCI_CLASS_SERIAL_USB_USB4 0x0c0340
  73. #endif