tegra132-soctherm.c 7.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
  4. *
  5. * This software is licensed under the terms of the GNU General Public
  6. * License version 2, as published by the Free Software Foundation, and
  7. * may be copied, distributed, and modified under those terms.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. */
  15. #include <linux/module.h>
  16. #include <linux/platform_device.h>
  17. #include <dt-bindings/thermal/tegra124-soctherm.h>
  18. #include "soctherm.h"
  19. #define TEGRA132_THERMTRIP_ANY_EN_MASK (0x1 << 28)
  20. #define TEGRA132_THERMTRIP_MEM_EN_MASK (0x1 << 27)
  21. #define TEGRA132_THERMTRIP_GPU_EN_MASK (0x1 << 26)
  22. #define TEGRA132_THERMTRIP_CPU_EN_MASK (0x1 << 25)
  23. #define TEGRA132_THERMTRIP_TSENSE_EN_MASK (0x1 << 24)
  24. #define TEGRA132_THERMTRIP_GPUMEM_THRESH_MASK (0xff << 16)
  25. #define TEGRA132_THERMTRIP_CPU_THRESH_MASK (0xff << 8)
  26. #define TEGRA132_THERMTRIP_TSENSE_THRESH_MASK 0xff
  27. #define TEGRA132_THERMCTL_LVL0_UP_THRESH_MASK (0xff << 17)
  28. #define TEGRA132_THERMCTL_LVL0_DN_THRESH_MASK (0xff << 9)
  29. #define TEGRA132_THRESH_GRAIN 1000
  30. #define TEGRA132_BPTT 8
  31. static const struct tegra_tsensor_configuration tegra132_tsensor_config = {
  32. .tall = 16300,
  33. .tiddq_en = 1,
  34. .ten_count = 1,
  35. .tsample = 120,
  36. .tsample_ate = 480,
  37. };
  38. static const struct tegra_tsensor_group tegra132_tsensor_group_cpu = {
  39. .id = TEGRA124_SOCTHERM_SENSOR_CPU,
  40. .name = "cpu",
  41. .sensor_temp_offset = SENSOR_TEMP1,
  42. .sensor_temp_mask = SENSOR_TEMP1_CPU_TEMP_MASK,
  43. .pdiv = 8,
  44. .pdiv_ate = 8,
  45. .pdiv_mask = SENSOR_PDIV_CPU_MASK,
  46. .pllx_hotspot_diff = 10,
  47. .pllx_hotspot_mask = SENSOR_HOTSPOT_CPU_MASK,
  48. .thermtrip_any_en_mask = TEGRA132_THERMTRIP_ANY_EN_MASK,
  49. .thermtrip_enable_mask = TEGRA132_THERMTRIP_CPU_EN_MASK,
  50. .thermtrip_threshold_mask = TEGRA132_THERMTRIP_CPU_THRESH_MASK,
  51. .thermctl_isr_mask = THERM_IRQ_CPU_MASK,
  52. .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_CPU,
  53. .thermctl_lvl0_up_thresh_mask = TEGRA132_THERMCTL_LVL0_UP_THRESH_MASK,
  54. .thermctl_lvl0_dn_thresh_mask = TEGRA132_THERMCTL_LVL0_DN_THRESH_MASK,
  55. };
  56. static const struct tegra_tsensor_group tegra132_tsensor_group_gpu = {
  57. .id = TEGRA124_SOCTHERM_SENSOR_GPU,
  58. .name = "gpu",
  59. .sensor_temp_offset = SENSOR_TEMP1,
  60. .sensor_temp_mask = SENSOR_TEMP1_GPU_TEMP_MASK,
  61. .pdiv = 8,
  62. .pdiv_ate = 8,
  63. .pdiv_mask = SENSOR_PDIV_GPU_MASK,
  64. .pllx_hotspot_diff = 5,
  65. .pllx_hotspot_mask = SENSOR_HOTSPOT_GPU_MASK,
  66. .thermtrip_any_en_mask = TEGRA132_THERMTRIP_ANY_EN_MASK,
  67. .thermtrip_enable_mask = TEGRA132_THERMTRIP_GPU_EN_MASK,
  68. .thermtrip_threshold_mask = TEGRA132_THERMTRIP_GPUMEM_THRESH_MASK,
  69. .thermctl_isr_mask = THERM_IRQ_GPU_MASK,
  70. .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_GPU,
  71. .thermctl_lvl0_up_thresh_mask = TEGRA132_THERMCTL_LVL0_UP_THRESH_MASK,
  72. .thermctl_lvl0_dn_thresh_mask = TEGRA132_THERMCTL_LVL0_DN_THRESH_MASK,
  73. };
  74. static const struct tegra_tsensor_group tegra132_tsensor_group_pll = {
  75. .id = TEGRA124_SOCTHERM_SENSOR_PLLX,
  76. .name = "pll",
  77. .sensor_temp_offset = SENSOR_TEMP2,
  78. .sensor_temp_mask = SENSOR_TEMP2_PLLX_TEMP_MASK,
  79. .pdiv = 8,
  80. .pdiv_ate = 8,
  81. .pdiv_mask = SENSOR_PDIV_PLLX_MASK,
  82. .thermtrip_any_en_mask = TEGRA132_THERMTRIP_ANY_EN_MASK,
  83. .thermtrip_enable_mask = TEGRA132_THERMTRIP_TSENSE_EN_MASK,
  84. .thermtrip_threshold_mask = TEGRA132_THERMTRIP_TSENSE_THRESH_MASK,
  85. .thermctl_isr_mask = THERM_IRQ_TSENSE_MASK,
  86. .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_TSENSE,
  87. .thermctl_lvl0_up_thresh_mask = TEGRA132_THERMCTL_LVL0_UP_THRESH_MASK,
  88. .thermctl_lvl0_dn_thresh_mask = TEGRA132_THERMCTL_LVL0_DN_THRESH_MASK,
  89. };
  90. static const struct tegra_tsensor_group tegra132_tsensor_group_mem = {
  91. .id = TEGRA124_SOCTHERM_SENSOR_MEM,
  92. .name = "mem",
  93. .sensor_temp_offset = SENSOR_TEMP2,
  94. .sensor_temp_mask = SENSOR_TEMP2_MEM_TEMP_MASK,
  95. .pdiv = 8,
  96. .pdiv_ate = 8,
  97. .pdiv_mask = SENSOR_PDIV_MEM_MASK,
  98. .pllx_hotspot_diff = 0,
  99. .pllx_hotspot_mask = SENSOR_HOTSPOT_MEM_MASK,
  100. .thermtrip_any_en_mask = TEGRA132_THERMTRIP_ANY_EN_MASK,
  101. .thermtrip_enable_mask = TEGRA132_THERMTRIP_MEM_EN_MASK,
  102. .thermtrip_threshold_mask = TEGRA132_THERMTRIP_GPUMEM_THRESH_MASK,
  103. .thermctl_isr_mask = THERM_IRQ_MEM_MASK,
  104. .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_MEM,
  105. .thermctl_lvl0_up_thresh_mask = TEGRA132_THERMCTL_LVL0_UP_THRESH_MASK,
  106. .thermctl_lvl0_dn_thresh_mask = TEGRA132_THERMCTL_LVL0_DN_THRESH_MASK,
  107. };
  108. static const struct tegra_tsensor_group *tegra132_tsensor_groups[] = {
  109. &tegra132_tsensor_group_cpu,
  110. &tegra132_tsensor_group_gpu,
  111. &tegra132_tsensor_group_pll,
  112. &tegra132_tsensor_group_mem,
  113. };
  114. static struct tegra_tsensor tegra132_tsensors[] = {
  115. {
  116. .name = "cpu0",
  117. .base = 0xc0,
  118. .config = &tegra132_tsensor_config,
  119. .calib_fuse_offset = 0x098,
  120. .fuse_corr_alpha = 1126600,
  121. .fuse_corr_beta = -9433500,
  122. .group = &tegra132_tsensor_group_cpu,
  123. }, {
  124. .name = "cpu1",
  125. .base = 0xe0,
  126. .config = &tegra132_tsensor_config,
  127. .calib_fuse_offset = 0x084,
  128. .fuse_corr_alpha = 1110800,
  129. .fuse_corr_beta = -7383000,
  130. .group = &tegra132_tsensor_group_cpu,
  131. }, {
  132. .name = "cpu2",
  133. .base = 0x100,
  134. .config = &tegra132_tsensor_config,
  135. .calib_fuse_offset = 0x088,
  136. .fuse_corr_alpha = 1113800,
  137. .fuse_corr_beta = -6215200,
  138. .group = &tegra132_tsensor_group_cpu,
  139. }, {
  140. .name = "cpu3",
  141. .base = 0x120,
  142. .config = &tegra132_tsensor_config,
  143. .calib_fuse_offset = 0x12c,
  144. .fuse_corr_alpha = 1129600,
  145. .fuse_corr_beta = -8196100,
  146. .group = &tegra132_tsensor_group_cpu,
  147. }, {
  148. .name = "mem0",
  149. .base = 0x140,
  150. .config = &tegra132_tsensor_config,
  151. .calib_fuse_offset = 0x158,
  152. .fuse_corr_alpha = 1132900,
  153. .fuse_corr_beta = -6755300,
  154. .group = &tegra132_tsensor_group_mem,
  155. }, {
  156. .name = "mem1",
  157. .base = 0x160,
  158. .config = &tegra132_tsensor_config,
  159. .calib_fuse_offset = 0x15c,
  160. .fuse_corr_alpha = 1142300,
  161. .fuse_corr_beta = -7374200,
  162. .group = &tegra132_tsensor_group_mem,
  163. }, {
  164. .name = "gpu",
  165. .base = 0x180,
  166. .config = &tegra132_tsensor_config,
  167. .calib_fuse_offset = 0x154,
  168. .fuse_corr_alpha = 1125100,
  169. .fuse_corr_beta = -6350400,
  170. .group = &tegra132_tsensor_group_gpu,
  171. }, {
  172. .name = "pllx",
  173. .base = 0x1a0,
  174. .config = &tegra132_tsensor_config,
  175. .calib_fuse_offset = 0x160,
  176. .fuse_corr_alpha = 1118100,
  177. .fuse_corr_beta = -8208800,
  178. .group = &tegra132_tsensor_group_pll,
  179. },
  180. };
  181. /*
  182. * Mask/shift bits in FUSE_TSENSOR_COMMON and
  183. * FUSE_TSENSOR_COMMON, which are described in
  184. * tegra_soctherm_fuse.c
  185. */
  186. static const struct tegra_soctherm_fuse tegra132_soctherm_fuse = {
  187. .fuse_base_cp_mask = 0x3ff,
  188. .fuse_base_cp_shift = 0,
  189. .fuse_base_ft_mask = 0x7ff << 10,
  190. .fuse_base_ft_shift = 10,
  191. .fuse_shift_ft_mask = 0x1f << 21,
  192. .fuse_shift_ft_shift = 21,
  193. .fuse_spare_realignment = 0x1fc,
  194. };
  195. const struct tegra_soctherm_soc tegra132_soctherm = {
  196. .tsensors = tegra132_tsensors,
  197. .num_tsensors = ARRAY_SIZE(tegra132_tsensors),
  198. .ttgs = tegra132_tsensor_groups,
  199. .num_ttgs = ARRAY_SIZE(tegra132_tsensor_groups),
  200. .tfuse = &tegra132_soctherm_fuse,
  201. .thresh_grain = TEGRA132_THRESH_GRAIN,
  202. .bptt = TEGRA132_BPTT,
  203. .use_ccroc = true,
  204. };