soctherm.h 4.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
  4. *
  5. * This software is licensed under the terms of the GNU General Public
  6. * License version 2, as published by the Free Software Foundation, and
  7. * may be copied, distributed, and modified under those terms.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. */
  15. #ifndef __DRIVERS_THERMAL_TEGRA_SOCTHERM_H
  16. #define __DRIVERS_THERMAL_TEGRA_SOCTHERM_H
  17. #define THERMCTL_LEVEL0_GROUP_CPU 0x0
  18. #define THERMCTL_LEVEL0_GROUP_GPU 0x4
  19. #define THERMCTL_LEVEL0_GROUP_MEM 0x8
  20. #define THERMCTL_LEVEL0_GROUP_TSENSE 0xc
  21. #define SENSOR_CONFIG2 8
  22. #define SENSOR_CONFIG2_THERMA_MASK (0xffff << 16)
  23. #define SENSOR_CONFIG2_THERMA_SHIFT 16
  24. #define SENSOR_CONFIG2_THERMB_MASK 0xffff
  25. #define SENSOR_CONFIG2_THERMB_SHIFT 0
  26. #define THERMCTL_THERMTRIP_CTL 0x80
  27. /* BITs are defined in device file */
  28. #define THERMCTL_INTR_ENABLE 0x88
  29. #define THERMCTL_INTR_DISABLE 0x8c
  30. #define TH_INTR_UP_DN_EN 0x3
  31. #define THERM_IRQ_MEM_MASK (TH_INTR_UP_DN_EN << 24)
  32. #define THERM_IRQ_GPU_MASK (TH_INTR_UP_DN_EN << 16)
  33. #define THERM_IRQ_CPU_MASK (TH_INTR_UP_DN_EN << 8)
  34. #define THERM_IRQ_TSENSE_MASK (TH_INTR_UP_DN_EN << 0)
  35. #define SENSOR_PDIV 0x1c0
  36. #define SENSOR_PDIV_CPU_MASK (0xf << 12)
  37. #define SENSOR_PDIV_GPU_MASK (0xf << 8)
  38. #define SENSOR_PDIV_MEM_MASK (0xf << 4)
  39. #define SENSOR_PDIV_PLLX_MASK (0xf << 0)
  40. #define SENSOR_HOTSPOT_OFF 0x1c4
  41. #define SENSOR_HOTSPOT_CPU_MASK (0xff << 16)
  42. #define SENSOR_HOTSPOT_GPU_MASK (0xff << 8)
  43. #define SENSOR_HOTSPOT_MEM_MASK (0xff << 0)
  44. #define SENSOR_TEMP1 0x1c8
  45. #define SENSOR_TEMP1_CPU_TEMP_MASK (0xffff << 16)
  46. #define SENSOR_TEMP1_GPU_TEMP_MASK 0xffff
  47. #define SENSOR_TEMP2 0x1cc
  48. #define SENSOR_TEMP2_MEM_TEMP_MASK (0xffff << 16)
  49. #define SENSOR_TEMP2_PLLX_TEMP_MASK 0xffff
  50. /**
  51. * struct tegra_tsensor_group - SOC_THERM sensor group data
  52. * @name: short name of the temperature sensor group
  53. * @id: numeric ID of the temperature sensor group
  54. * @sensor_temp_offset: offset of the SENSOR_TEMP* register
  55. * @sensor_temp_mask: bit mask for this sensor group in SENSOR_TEMP* register
  56. * @pdiv: the sensor count post-divider to use during runtime
  57. * @pdiv_ate: the sensor count post-divider used during automated test
  58. * @pdiv_mask: register bitfield mask for the PDIV field for this sensor
  59. * @pllx_hotspot_diff: hotspot offset from the PLLX sensor, must be 0 for
  60. PLLX sensor group
  61. * @pllx_hotspot_mask: register bitfield mask for the HOTSPOT field
  62. */
  63. struct tegra_tsensor_group {
  64. const char *name;
  65. u8 id;
  66. u16 sensor_temp_offset;
  67. u32 sensor_temp_mask;
  68. u32 pdiv, pdiv_ate, pdiv_mask;
  69. u32 pllx_hotspot_diff, pllx_hotspot_mask;
  70. u32 thermtrip_enable_mask;
  71. u32 thermtrip_any_en_mask;
  72. u32 thermtrip_threshold_mask;
  73. u32 thermctl_isr_mask;
  74. u16 thermctl_lvl0_offset;
  75. u32 thermctl_lvl0_up_thresh_mask;
  76. u32 thermctl_lvl0_dn_thresh_mask;
  77. };
  78. struct tegra_tsensor_configuration {
  79. u32 tall, tiddq_en, ten_count, pdiv, pdiv_ate, tsample, tsample_ate;
  80. };
  81. struct tegra_tsensor {
  82. const char *name;
  83. const u32 base;
  84. const struct tegra_tsensor_configuration *config;
  85. const u32 calib_fuse_offset;
  86. /*
  87. * Correction values used to modify values read from
  88. * calibration fuses
  89. */
  90. const s32 fuse_corr_alpha, fuse_corr_beta;
  91. const struct tegra_tsensor_group *group;
  92. };
  93. struct tsensor_group_thermtrips {
  94. u8 id;
  95. u32 temp;
  96. };
  97. struct tegra_soctherm_fuse {
  98. u32 fuse_base_cp_mask, fuse_base_cp_shift;
  99. u32 fuse_base_ft_mask, fuse_base_ft_shift;
  100. u32 fuse_shift_ft_mask, fuse_shift_ft_shift;
  101. u32 fuse_spare_realignment;
  102. };
  103. struct tsensor_shared_calib {
  104. u32 base_cp, base_ft;
  105. u32 actual_temp_cp, actual_temp_ft;
  106. };
  107. struct tegra_soctherm_soc {
  108. const struct tegra_tsensor *tsensors;
  109. const unsigned int num_tsensors;
  110. const struct tegra_tsensor_group **ttgs;
  111. const unsigned int num_ttgs;
  112. const struct tegra_soctherm_fuse *tfuse;
  113. const int thresh_grain;
  114. const unsigned int bptt;
  115. const bool use_ccroc;
  116. struct tsensor_group_thermtrips *thermtrips;
  117. };
  118. int tegra_calc_shared_calib(const struct tegra_soctherm_fuse *tfuse,
  119. struct tsensor_shared_calib *shared);
  120. int tegra_calc_tsensor_calib(const struct tegra_tsensor *sensor,
  121. const struct tsensor_shared_calib *shared,
  122. u32 *calib);
  123. #ifdef CONFIG_ARCH_TEGRA_124_SOC
  124. extern const struct tegra_soctherm_soc tegra124_soctherm;
  125. #endif
  126. #ifdef CONFIG_ARCH_TEGRA_132_SOC
  127. extern const struct tegra_soctherm_soc tegra132_soctherm;
  128. #endif
  129. #ifdef CONFIG_ARCH_TEGRA_210_SOC
  130. extern const struct tegra_soctherm_soc tegra210_soctherm;
  131. #endif
  132. #endif