soctherm.c 65 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2014 - 2018, NVIDIA CORPORATION. All rights reserved.
  4. *
  5. * Author:
  6. * Mikko Perttunen <mperttunen@nvidia.com>
  7. *
  8. * This software is licensed under the terms of the GNU General Public
  9. * License version 2, as published by the Free Software Foundation, and
  10. * may be copied, distributed, and modified under those terms.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. */
  18. #include <linux/debugfs.h>
  19. #include <linux/bitops.h>
  20. #include <linux/clk.h>
  21. #include <linux/delay.h>
  22. #include <linux/err.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/io.h>
  25. #include <linux/irq.h>
  26. #include <linux/irqdomain.h>
  27. #include <linux/module.h>
  28. #include <linux/of.h>
  29. #include <linux/platform_device.h>
  30. #include <linux/reset.h>
  31. #include <linux/thermal.h>
  32. #include <dt-bindings/thermal/tegra124-soctherm.h>
  33. #include "../thermal_core.h"
  34. #include "soctherm.h"
  35. #define SENSOR_CONFIG0 0
  36. #define SENSOR_CONFIG0_STOP BIT(0)
  37. #define SENSOR_CONFIG0_CPTR_OVER BIT(2)
  38. #define SENSOR_CONFIG0_OVER BIT(3)
  39. #define SENSOR_CONFIG0_TCALC_OVER BIT(4)
  40. #define SENSOR_CONFIG0_TALL_MASK (0xfffff << 8)
  41. #define SENSOR_CONFIG0_TALL_SHIFT 8
  42. #define SENSOR_CONFIG1 4
  43. #define SENSOR_CONFIG1_TSAMPLE_MASK 0x3ff
  44. #define SENSOR_CONFIG1_TSAMPLE_SHIFT 0
  45. #define SENSOR_CONFIG1_TIDDQ_EN_MASK (0x3f << 15)
  46. #define SENSOR_CONFIG1_TIDDQ_EN_SHIFT 15
  47. #define SENSOR_CONFIG1_TEN_COUNT_MASK (0x3f << 24)
  48. #define SENSOR_CONFIG1_TEN_COUNT_SHIFT 24
  49. #define SENSOR_CONFIG1_TEMP_ENABLE BIT(31)
  50. /*
  51. * SENSOR_CONFIG2 is defined in soctherm.h
  52. * because, it will be used by tegra_soctherm_fuse.c
  53. */
  54. #define SENSOR_STATUS0 0xc
  55. #define SENSOR_STATUS0_VALID_MASK BIT(31)
  56. #define SENSOR_STATUS0_CAPTURE_MASK 0xffff
  57. #define SENSOR_STATUS1 0x10
  58. #define SENSOR_STATUS1_TEMP_VALID_MASK BIT(31)
  59. #define SENSOR_STATUS1_TEMP_MASK 0xffff
  60. #define READBACK_VALUE_MASK 0xff00
  61. #define READBACK_VALUE_SHIFT 8
  62. #define READBACK_ADD_HALF BIT(7)
  63. #define READBACK_NEGATE BIT(0)
  64. /*
  65. * THERMCTL_LEVEL0_GROUP_CPU is defined in soctherm.h
  66. * because it will be used by tegraxxx_soctherm.c
  67. */
  68. #define THERMCTL_LVL0_CPU0_EN_MASK BIT(8)
  69. #define THERMCTL_LVL0_CPU0_CPU_THROT_MASK (0x3 << 5)
  70. #define THERMCTL_LVL0_CPU0_CPU_THROT_LIGHT 0x1
  71. #define THERMCTL_LVL0_CPU0_CPU_THROT_HEAVY 0x2
  72. #define THERMCTL_LVL0_CPU0_GPU_THROT_MASK (0x3 << 3)
  73. #define THERMCTL_LVL0_CPU0_GPU_THROT_LIGHT 0x1
  74. #define THERMCTL_LVL0_CPU0_GPU_THROT_HEAVY 0x2
  75. #define THERMCTL_LVL0_CPU0_MEM_THROT_MASK BIT(2)
  76. #define THERMCTL_LVL0_CPU0_STATUS_MASK 0x3
  77. #define THERMCTL_LVL0_UP_STATS 0x10
  78. #define THERMCTL_LVL0_DN_STATS 0x14
  79. #define THERMCTL_INTR_STATUS 0x84
  80. #define TH_INTR_MD0_MASK BIT(25)
  81. #define TH_INTR_MU0_MASK BIT(24)
  82. #define TH_INTR_GD0_MASK BIT(17)
  83. #define TH_INTR_GU0_MASK BIT(16)
  84. #define TH_INTR_CD0_MASK BIT(9)
  85. #define TH_INTR_CU0_MASK BIT(8)
  86. #define TH_INTR_PD0_MASK BIT(1)
  87. #define TH_INTR_PU0_MASK BIT(0)
  88. #define TH_INTR_IGNORE_MASK 0xFCFCFCFC
  89. #define THERMCTL_STATS_CTL 0x94
  90. #define STATS_CTL_CLR_DN 0x8
  91. #define STATS_CTL_EN_DN 0x4
  92. #define STATS_CTL_CLR_UP 0x2
  93. #define STATS_CTL_EN_UP 0x1
  94. #define OC1_CFG 0x310
  95. #define OC1_CFG_LONG_LATENCY_MASK BIT(6)
  96. #define OC1_CFG_HW_RESTORE_MASK BIT(5)
  97. #define OC1_CFG_PWR_GOOD_MASK_MASK BIT(4)
  98. #define OC1_CFG_THROTTLE_MODE_MASK (0x3 << 2)
  99. #define OC1_CFG_ALARM_POLARITY_MASK BIT(1)
  100. #define OC1_CFG_EN_THROTTLE_MASK BIT(0)
  101. #define OC1_CNT_THRESHOLD 0x314
  102. #define OC1_THROTTLE_PERIOD 0x318
  103. #define OC1_ALARM_COUNT 0x31c
  104. #define OC1_FILTER 0x320
  105. #define OC1_STATS 0x3a8
  106. #define OC_INTR_STATUS 0x39c
  107. #define OC_INTR_ENABLE 0x3a0
  108. #define OC_INTR_DISABLE 0x3a4
  109. #define OC_STATS_CTL 0x3c4
  110. #define OC_STATS_CTL_CLR_ALL 0x2
  111. #define OC_STATS_CTL_EN_ALL 0x1
  112. #define OC_INTR_OC1_MASK BIT(0)
  113. #define OC_INTR_OC2_MASK BIT(1)
  114. #define OC_INTR_OC3_MASK BIT(2)
  115. #define OC_INTR_OC4_MASK BIT(3)
  116. #define OC_INTR_OC5_MASK BIT(4)
  117. #define THROT_GLOBAL_CFG 0x400
  118. #define THROT_GLOBAL_ENB_MASK BIT(0)
  119. #define CPU_PSKIP_STATUS 0x418
  120. #define XPU_PSKIP_STATUS_M_MASK (0xff << 12)
  121. #define XPU_PSKIP_STATUS_N_MASK (0xff << 4)
  122. #define XPU_PSKIP_STATUS_SW_OVERRIDE_MASK BIT(1)
  123. #define XPU_PSKIP_STATUS_ENABLED_MASK BIT(0)
  124. #define THROT_PRIORITY_LOCK 0x424
  125. #define THROT_PRIORITY_LOCK_PRIORITY_MASK 0xff
  126. #define THROT_STATUS 0x428
  127. #define THROT_STATUS_BREACH_MASK BIT(12)
  128. #define THROT_STATUS_STATE_MASK (0xff << 4)
  129. #define THROT_STATUS_ENABLED_MASK BIT(0)
  130. #define THROT_PSKIP_CTRL_LITE_CPU 0x430
  131. #define THROT_PSKIP_CTRL_ENABLE_MASK BIT(31)
  132. #define THROT_PSKIP_CTRL_DIVIDEND_MASK (0xff << 8)
  133. #define THROT_PSKIP_CTRL_DIVISOR_MASK 0xff
  134. #define THROT_PSKIP_CTRL_VECT_GPU_MASK (0x7 << 16)
  135. #define THROT_PSKIP_CTRL_VECT_CPU_MASK (0x7 << 8)
  136. #define THROT_PSKIP_CTRL_VECT2_CPU_MASK 0x7
  137. #define THROT_VECT_NONE 0x0 /* 3'b000 */
  138. #define THROT_VECT_LOW 0x1 /* 3'b001 */
  139. #define THROT_VECT_MED 0x3 /* 3'b011 */
  140. #define THROT_VECT_HIGH 0x7 /* 3'b111 */
  141. #define THROT_PSKIP_RAMP_LITE_CPU 0x434
  142. #define THROT_PSKIP_RAMP_SEQ_BYPASS_MODE_MASK BIT(31)
  143. #define THROT_PSKIP_RAMP_DURATION_MASK (0xffff << 8)
  144. #define THROT_PSKIP_RAMP_STEP_MASK 0xff
  145. #define THROT_PRIORITY_LITE 0x444
  146. #define THROT_PRIORITY_LITE_PRIO_MASK 0xff
  147. #define THROT_DELAY_LITE 0x448
  148. #define THROT_DELAY_LITE_DELAY_MASK 0xff
  149. /* car register offsets needed for enabling HW throttling */
  150. #define CAR_SUPER_CCLKG_DIVIDER 0x36c
  151. #define CDIVG_USE_THERM_CONTROLS_MASK BIT(30)
  152. /* ccroc register offsets needed for enabling HW throttling for Tegra132 */
  153. #define CCROC_SUPER_CCLKG_DIVIDER 0x024
  154. #define CCROC_GLOBAL_CFG 0x148
  155. #define CCROC_THROT_PSKIP_RAMP_CPU 0x150
  156. #define CCROC_THROT_PSKIP_RAMP_SEQ_BYPASS_MODE_MASK BIT(31)
  157. #define CCROC_THROT_PSKIP_RAMP_DURATION_MASK (0xffff << 8)
  158. #define CCROC_THROT_PSKIP_RAMP_STEP_MASK 0xff
  159. #define CCROC_THROT_PSKIP_CTRL_CPU 0x154
  160. #define CCROC_THROT_PSKIP_CTRL_ENB_MASK BIT(31)
  161. #define CCROC_THROT_PSKIP_CTRL_DIVIDEND_MASK (0xff << 8)
  162. #define CCROC_THROT_PSKIP_CTRL_DIVISOR_MASK 0xff
  163. /* get val from register(r) mask bits(m) */
  164. #define REG_GET_MASK(r, m) (((r) & (m)) >> (ffs(m) - 1))
  165. /* set val(v) to mask bits(m) of register(r) */
  166. #define REG_SET_MASK(r, m, v) (((r) & ~(m)) | \
  167. (((v) & (m >> (ffs(m) - 1))) << (ffs(m) - 1)))
  168. /* get dividend from the depth */
  169. #define THROT_DEPTH_DIVIDEND(depth) ((256 * (100 - (depth)) / 100) - 1)
  170. /* gk20a nv_therm interface N:3 Mapping. Levels defined in tegra124-soctherm.h
  171. * level vector
  172. * NONE 3'b000
  173. * LOW 3'b001
  174. * MED 3'b011
  175. * HIGH 3'b111
  176. */
  177. #define THROT_LEVEL_TO_DEPTH(level) ((0x1 << (level)) - 1)
  178. /* get THROT_PSKIP_xxx offset per LIGHT/HEAVY throt and CPU/GPU dev */
  179. #define THROT_OFFSET 0x30
  180. #define THROT_PSKIP_CTRL(throt, dev) (THROT_PSKIP_CTRL_LITE_CPU + \
  181. (THROT_OFFSET * throt) + (8 * dev))
  182. #define THROT_PSKIP_RAMP(throt, dev) (THROT_PSKIP_RAMP_LITE_CPU + \
  183. (THROT_OFFSET * throt) + (8 * dev))
  184. /* get THROT_xxx_CTRL offset per LIGHT/HEAVY throt */
  185. #define THROT_PRIORITY_CTRL(throt) (THROT_PRIORITY_LITE + \
  186. (THROT_OFFSET * throt))
  187. #define THROT_DELAY_CTRL(throt) (THROT_DELAY_LITE + \
  188. (THROT_OFFSET * throt))
  189. #define ALARM_OFFSET 0x14
  190. #define ALARM_CFG(throt) (OC1_CFG + \
  191. (ALARM_OFFSET * (throt - THROTTLE_OC1)))
  192. #define ALARM_CNT_THRESHOLD(throt) (OC1_CNT_THRESHOLD + \
  193. (ALARM_OFFSET * (throt - THROTTLE_OC1)))
  194. #define ALARM_THROTTLE_PERIOD(throt) (OC1_THROTTLE_PERIOD + \
  195. (ALARM_OFFSET * (throt - THROTTLE_OC1)))
  196. #define ALARM_ALARM_COUNT(throt) (OC1_ALARM_COUNT + \
  197. (ALARM_OFFSET * (throt - THROTTLE_OC1)))
  198. #define ALARM_FILTER(throt) (OC1_FILTER + \
  199. (ALARM_OFFSET * (throt - THROTTLE_OC1)))
  200. #define ALARM_STATS(throt) (OC1_STATS + \
  201. (4 * (throt - THROTTLE_OC1)))
  202. /* get CCROC_THROT_PSKIP_xxx offset per HIGH/MED/LOW vect*/
  203. #define CCROC_THROT_OFFSET 0x0c
  204. #define CCROC_THROT_PSKIP_CTRL_CPU_REG(vect) (CCROC_THROT_PSKIP_CTRL_CPU + \
  205. (CCROC_THROT_OFFSET * vect))
  206. #define CCROC_THROT_PSKIP_RAMP_CPU_REG(vect) (CCROC_THROT_PSKIP_RAMP_CPU + \
  207. (CCROC_THROT_OFFSET * vect))
  208. /* get THERMCTL_LEVELx offset per CPU/GPU/MEM/TSENSE rg and LEVEL0~3 lv */
  209. #define THERMCTL_LVL_REGS_SIZE 0x20
  210. #define THERMCTL_LVL_REG(rg, lv) ((rg) + ((lv) * THERMCTL_LVL_REGS_SIZE))
  211. #define OC_THROTTLE_MODE_DISABLED 0
  212. #define OC_THROTTLE_MODE_BRIEF 2
  213. static const int min_low_temp = -127000;
  214. static const int max_high_temp = 127000;
  215. enum soctherm_throttle_id {
  216. THROTTLE_LIGHT = 0,
  217. THROTTLE_HEAVY,
  218. THROTTLE_OC1,
  219. THROTTLE_OC2,
  220. THROTTLE_OC3,
  221. THROTTLE_OC4,
  222. THROTTLE_OC5, /* OC5 is reserved */
  223. THROTTLE_SIZE,
  224. };
  225. enum soctherm_oc_irq_id {
  226. TEGRA_SOC_OC_IRQ_1,
  227. TEGRA_SOC_OC_IRQ_2,
  228. TEGRA_SOC_OC_IRQ_3,
  229. TEGRA_SOC_OC_IRQ_4,
  230. TEGRA_SOC_OC_IRQ_5,
  231. TEGRA_SOC_OC_IRQ_MAX,
  232. };
  233. enum soctherm_throttle_dev_id {
  234. THROTTLE_DEV_CPU = 0,
  235. THROTTLE_DEV_GPU,
  236. THROTTLE_DEV_SIZE,
  237. };
  238. static const char *const throt_names[] = {
  239. [THROTTLE_LIGHT] = "light",
  240. [THROTTLE_HEAVY] = "heavy",
  241. [THROTTLE_OC1] = "oc1",
  242. [THROTTLE_OC2] = "oc2",
  243. [THROTTLE_OC3] = "oc3",
  244. [THROTTLE_OC4] = "oc4",
  245. [THROTTLE_OC5] = "oc5",
  246. };
  247. struct tegra_soctherm;
  248. struct tegra_thermctl_zone {
  249. void __iomem *reg;
  250. struct device *dev;
  251. struct tegra_soctherm *ts;
  252. struct thermal_zone_device *tz;
  253. const struct tegra_tsensor_group *sg;
  254. };
  255. struct soctherm_oc_cfg {
  256. u32 active_low;
  257. u32 throt_period;
  258. u32 alarm_cnt_thresh;
  259. u32 alarm_filter;
  260. u32 mode;
  261. bool intr_en;
  262. };
  263. struct soctherm_throt_cfg {
  264. const char *name;
  265. unsigned int id;
  266. u8 priority;
  267. u8 cpu_throt_level;
  268. u32 cpu_throt_depth;
  269. u32 gpu_throt_level;
  270. struct soctherm_oc_cfg oc_cfg;
  271. struct thermal_cooling_device *cdev;
  272. bool init;
  273. };
  274. struct tegra_soctherm {
  275. struct reset_control *reset;
  276. struct clk *clock_tsensor;
  277. struct clk *clock_soctherm;
  278. void __iomem *regs;
  279. void __iomem *clk_regs;
  280. void __iomem *ccroc_regs;
  281. int thermal_irq;
  282. int edp_irq;
  283. u32 *calib;
  284. struct thermal_zone_device **thermctl_tzs;
  285. struct tegra_soctherm_soc *soc;
  286. struct soctherm_throt_cfg throt_cfgs[THROTTLE_SIZE];
  287. struct dentry *debugfs_dir;
  288. struct mutex thermctl_lock;
  289. };
  290. struct soctherm_oc_irq_chip_data {
  291. struct mutex irq_lock; /* serialize OC IRQs */
  292. struct irq_chip irq_chip;
  293. struct irq_domain *domain;
  294. int irq_enable;
  295. };
  296. static struct soctherm_oc_irq_chip_data soc_irq_cdata;
  297. /**
  298. * ccroc_writel() - writes a value to a CCROC register
  299. * @ts: pointer to a struct tegra_soctherm
  300. * @value: the value to write
  301. * @reg: the register offset
  302. *
  303. * Writes @v to @reg. No return value.
  304. */
  305. static inline void ccroc_writel(struct tegra_soctherm *ts, u32 value, u32 reg)
  306. {
  307. writel(value, (ts->ccroc_regs + reg));
  308. }
  309. /**
  310. * ccroc_readl() - reads specified register from CCROC IP block
  311. * @ts: pointer to a struct tegra_soctherm
  312. * @reg: register address to be read
  313. *
  314. * Return: the value of the register
  315. */
  316. static inline u32 ccroc_readl(struct tegra_soctherm *ts, u32 reg)
  317. {
  318. return readl(ts->ccroc_regs + reg);
  319. }
  320. static void enable_tsensor(struct tegra_soctherm *tegra, unsigned int i)
  321. {
  322. const struct tegra_tsensor *sensor = &tegra->soc->tsensors[i];
  323. void __iomem *base = tegra->regs + sensor->base;
  324. unsigned int val;
  325. val = sensor->config->tall << SENSOR_CONFIG0_TALL_SHIFT;
  326. writel(val, base + SENSOR_CONFIG0);
  327. val = (sensor->config->tsample - 1) << SENSOR_CONFIG1_TSAMPLE_SHIFT;
  328. val |= sensor->config->tiddq_en << SENSOR_CONFIG1_TIDDQ_EN_SHIFT;
  329. val |= sensor->config->ten_count << SENSOR_CONFIG1_TEN_COUNT_SHIFT;
  330. val |= SENSOR_CONFIG1_TEMP_ENABLE;
  331. writel(val, base + SENSOR_CONFIG1);
  332. writel(tegra->calib[i], base + SENSOR_CONFIG2);
  333. }
  334. /*
  335. * Translate from soctherm readback format to millicelsius.
  336. * The soctherm readback format in bits is as follows:
  337. * TTTTTTTT H______N
  338. * where T's contain the temperature in Celsius,
  339. * H denotes an addition of 0.5 Celsius and N denotes negation
  340. * of the final value.
  341. */
  342. static int translate_temp(u16 val)
  343. {
  344. int t;
  345. t = ((val & READBACK_VALUE_MASK) >> READBACK_VALUE_SHIFT) * 1000;
  346. if (val & READBACK_ADD_HALF)
  347. t += 500;
  348. if (val & READBACK_NEGATE)
  349. t *= -1;
  350. return t;
  351. }
  352. static int tegra_thermctl_get_temp(void *data, int *out_temp)
  353. {
  354. struct tegra_thermctl_zone *zone = data;
  355. u32 val;
  356. val = readl(zone->reg);
  357. val = REG_GET_MASK(val, zone->sg->sensor_temp_mask);
  358. *out_temp = translate_temp(val);
  359. return 0;
  360. }
  361. /**
  362. * enforce_temp_range() - check and enforce temperature range [min, max]
  363. * @dev: struct device * of the SOC_THERM instance
  364. * @trip_temp: the trip temperature to check
  365. *
  366. * Checks and enforces the permitted temperature range that SOC_THERM
  367. * HW can support This is
  368. * done while taking care of precision.
  369. *
  370. * Return: The precision adjusted capped temperature in millicelsius.
  371. */
  372. static int enforce_temp_range(struct device *dev, int trip_temp)
  373. {
  374. int temp;
  375. temp = clamp_val(trip_temp, min_low_temp, max_high_temp);
  376. if (temp != trip_temp)
  377. dev_info(dev, "soctherm: trip temperature %d forced to %d\n",
  378. trip_temp, temp);
  379. return temp;
  380. }
  381. /**
  382. * thermtrip_program() - Configures the hardware to shut down the
  383. * system if a given sensor group reaches a given temperature
  384. * @dev: ptr to the struct device for the SOC_THERM IP block
  385. * @sg: pointer to the sensor group to set the thermtrip temperature for
  386. * @trip_temp: the temperature in millicelsius to trigger the thermal trip at
  387. *
  388. * Sets the thermal trip threshold of the given sensor group to be the
  389. * @trip_temp. If this threshold is crossed, the hardware will shut
  390. * down.
  391. *
  392. * Note that, although @trip_temp is specified in millicelsius, the
  393. * hardware is programmed in degrees Celsius.
  394. *
  395. * Return: 0 upon success, or %-EINVAL upon failure.
  396. */
  397. static int thermtrip_program(struct device *dev,
  398. const struct tegra_tsensor_group *sg,
  399. int trip_temp)
  400. {
  401. struct tegra_soctherm *ts = dev_get_drvdata(dev);
  402. int temp;
  403. u32 r;
  404. if (!sg || !sg->thermtrip_threshold_mask)
  405. return -EINVAL;
  406. temp = enforce_temp_range(dev, trip_temp) / ts->soc->thresh_grain;
  407. r = readl(ts->regs + THERMCTL_THERMTRIP_CTL);
  408. r = REG_SET_MASK(r, sg->thermtrip_threshold_mask, temp);
  409. r = REG_SET_MASK(r, sg->thermtrip_enable_mask, 1);
  410. r = REG_SET_MASK(r, sg->thermtrip_any_en_mask, 0);
  411. writel(r, ts->regs + THERMCTL_THERMTRIP_CTL);
  412. return 0;
  413. }
  414. /**
  415. * throttrip_program() - Configures the hardware to throttle the
  416. * pulse if a given sensor group reaches a given temperature
  417. * @dev: ptr to the struct device for the SOC_THERM IP block
  418. * @sg: pointer to the sensor group to set the thermtrip temperature for
  419. * @stc: pointer to the throttle need to be triggered
  420. * @trip_temp: the temperature in millicelsius to trigger the thermal trip at
  421. *
  422. * Sets the thermal trip threshold and throttle event of the given sensor
  423. * group. If this threshold is crossed, the hardware will trigger the
  424. * throttle.
  425. *
  426. * Note that, although @trip_temp is specified in millicelsius, the
  427. * hardware is programmed in degrees Celsius.
  428. *
  429. * Return: 0 upon success, or %-EINVAL upon failure.
  430. */
  431. static int throttrip_program(struct device *dev,
  432. const struct tegra_tsensor_group *sg,
  433. struct soctherm_throt_cfg *stc,
  434. int trip_temp)
  435. {
  436. struct tegra_soctherm *ts = dev_get_drvdata(dev);
  437. int temp, cpu_throt, gpu_throt;
  438. unsigned int throt;
  439. u32 r, reg_off;
  440. if (!sg || !stc || !stc->init)
  441. return -EINVAL;
  442. temp = enforce_temp_range(dev, trip_temp) / ts->soc->thresh_grain;
  443. /* Hardcode LIGHT on LEVEL1 and HEAVY on LEVEL2 */
  444. throt = stc->id;
  445. reg_off = THERMCTL_LVL_REG(sg->thermctl_lvl0_offset, throt + 1);
  446. if (throt == THROTTLE_LIGHT) {
  447. cpu_throt = THERMCTL_LVL0_CPU0_CPU_THROT_LIGHT;
  448. gpu_throt = THERMCTL_LVL0_CPU0_GPU_THROT_LIGHT;
  449. } else {
  450. cpu_throt = THERMCTL_LVL0_CPU0_CPU_THROT_HEAVY;
  451. gpu_throt = THERMCTL_LVL0_CPU0_GPU_THROT_HEAVY;
  452. if (throt != THROTTLE_HEAVY)
  453. dev_warn(dev,
  454. "invalid throt id %d - assuming HEAVY",
  455. throt);
  456. }
  457. r = readl(ts->regs + reg_off);
  458. r = REG_SET_MASK(r, sg->thermctl_lvl0_up_thresh_mask, temp);
  459. r = REG_SET_MASK(r, sg->thermctl_lvl0_dn_thresh_mask, temp);
  460. r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_CPU_THROT_MASK, cpu_throt);
  461. r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_GPU_THROT_MASK, gpu_throt);
  462. r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_EN_MASK, 1);
  463. writel(r, ts->regs + reg_off);
  464. return 0;
  465. }
  466. static struct soctherm_throt_cfg *
  467. find_throttle_cfg_by_name(struct tegra_soctherm *ts, const char *name)
  468. {
  469. unsigned int i;
  470. for (i = 0; ts->throt_cfgs[i].name; i++)
  471. if (!strcmp(ts->throt_cfgs[i].name, name))
  472. return &ts->throt_cfgs[i];
  473. return NULL;
  474. }
  475. static int tsensor_group_thermtrip_get(struct tegra_soctherm *ts, int id)
  476. {
  477. int i, temp = min_low_temp;
  478. struct tsensor_group_thermtrips *tt = ts->soc->thermtrips;
  479. if (id >= TEGRA124_SOCTHERM_SENSOR_NUM)
  480. return temp;
  481. if (tt) {
  482. for (i = 0; i < ts->soc->num_ttgs; i++) {
  483. if (tt[i].id == id)
  484. return tt[i].temp;
  485. }
  486. }
  487. return temp;
  488. }
  489. static int tegra_thermctl_set_trip_temp(void *data, int trip, int temp)
  490. {
  491. struct tegra_thermctl_zone *zone = data;
  492. struct thermal_zone_device *tz = zone->tz;
  493. struct tegra_soctherm *ts = zone->ts;
  494. const struct tegra_tsensor_group *sg = zone->sg;
  495. struct device *dev = zone->dev;
  496. enum thermal_trip_type type;
  497. int ret;
  498. if (!tz)
  499. return -EINVAL;
  500. ret = tz->ops->get_trip_type(tz, trip, &type);
  501. if (ret)
  502. return ret;
  503. if (type == THERMAL_TRIP_CRITICAL) {
  504. /*
  505. * If thermtrips property is set in DT,
  506. * doesn't need to program critical type trip to HW,
  507. * if not, program critical trip to HW.
  508. */
  509. if (min_low_temp == tsensor_group_thermtrip_get(ts, sg->id))
  510. return thermtrip_program(dev, sg, temp);
  511. else
  512. return 0;
  513. } else if (type == THERMAL_TRIP_HOT) {
  514. int i;
  515. for (i = 0; i < THROTTLE_SIZE; i++) {
  516. struct thermal_cooling_device *cdev;
  517. struct soctherm_throt_cfg *stc;
  518. if (!ts->throt_cfgs[i].init)
  519. continue;
  520. cdev = ts->throt_cfgs[i].cdev;
  521. if (get_thermal_instance(tz, cdev, trip))
  522. stc = find_throttle_cfg_by_name(ts, cdev->type);
  523. else
  524. continue;
  525. return throttrip_program(dev, sg, stc, temp);
  526. }
  527. }
  528. return 0;
  529. }
  530. static int tegra_thermctl_get_trend(void *data, int trip,
  531. enum thermal_trend *trend)
  532. {
  533. struct tegra_thermctl_zone *zone = data;
  534. struct thermal_zone_device *tz = zone->tz;
  535. int trip_temp, temp, last_temp, ret;
  536. if (!tz)
  537. return -EINVAL;
  538. ret = tz->ops->get_trip_temp(zone->tz, trip, &trip_temp);
  539. if (ret)
  540. return ret;
  541. temp = READ_ONCE(tz->temperature);
  542. last_temp = READ_ONCE(tz->last_temperature);
  543. if (temp > trip_temp) {
  544. if (temp >= last_temp)
  545. *trend = THERMAL_TREND_RAISING;
  546. else
  547. *trend = THERMAL_TREND_STABLE;
  548. } else if (temp < trip_temp) {
  549. *trend = THERMAL_TREND_DROPPING;
  550. } else {
  551. *trend = THERMAL_TREND_STABLE;
  552. }
  553. return 0;
  554. }
  555. static void thermal_irq_enable(struct tegra_thermctl_zone *zn)
  556. {
  557. u32 r;
  558. /* multiple zones could be handling and setting trips at once */
  559. mutex_lock(&zn->ts->thermctl_lock);
  560. r = readl(zn->ts->regs + THERMCTL_INTR_ENABLE);
  561. r = REG_SET_MASK(r, zn->sg->thermctl_isr_mask, TH_INTR_UP_DN_EN);
  562. writel(r, zn->ts->regs + THERMCTL_INTR_ENABLE);
  563. mutex_unlock(&zn->ts->thermctl_lock);
  564. }
  565. static void thermal_irq_disable(struct tegra_thermctl_zone *zn)
  566. {
  567. u32 r;
  568. /* multiple zones could be handling and setting trips at once */
  569. mutex_lock(&zn->ts->thermctl_lock);
  570. r = readl(zn->ts->regs + THERMCTL_INTR_DISABLE);
  571. r = REG_SET_MASK(r, zn->sg->thermctl_isr_mask, 0);
  572. writel(r, zn->ts->regs + THERMCTL_INTR_DISABLE);
  573. mutex_unlock(&zn->ts->thermctl_lock);
  574. }
  575. static int tegra_thermctl_set_trips(void *data, int lo, int hi)
  576. {
  577. struct tegra_thermctl_zone *zone = data;
  578. u32 r;
  579. thermal_irq_disable(zone);
  580. r = readl(zone->ts->regs + zone->sg->thermctl_lvl0_offset);
  581. r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_EN_MASK, 0);
  582. writel(r, zone->ts->regs + zone->sg->thermctl_lvl0_offset);
  583. lo = enforce_temp_range(zone->dev, lo) / zone->ts->soc->thresh_grain;
  584. hi = enforce_temp_range(zone->dev, hi) / zone->ts->soc->thresh_grain;
  585. dev_dbg(zone->dev, "%s hi:%d, lo:%d\n", __func__, hi, lo);
  586. r = REG_SET_MASK(r, zone->sg->thermctl_lvl0_up_thresh_mask, hi);
  587. r = REG_SET_MASK(r, zone->sg->thermctl_lvl0_dn_thresh_mask, lo);
  588. r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_EN_MASK, 1);
  589. writel(r, zone->ts->regs + zone->sg->thermctl_lvl0_offset);
  590. thermal_irq_enable(zone);
  591. return 0;
  592. }
  593. static const struct thermal_zone_of_device_ops tegra_of_thermal_ops = {
  594. .get_temp = tegra_thermctl_get_temp,
  595. .set_trip_temp = tegra_thermctl_set_trip_temp,
  596. .get_trend = tegra_thermctl_get_trend,
  597. .set_trips = tegra_thermctl_set_trips,
  598. };
  599. static int get_hot_temp(struct thermal_zone_device *tz, int *trip, int *temp)
  600. {
  601. int ntrips, i, ret;
  602. enum thermal_trip_type type;
  603. ntrips = of_thermal_get_ntrips(tz);
  604. if (ntrips <= 0)
  605. return -EINVAL;
  606. for (i = 0; i < ntrips; i++) {
  607. ret = tz->ops->get_trip_type(tz, i, &type);
  608. if (ret)
  609. return -EINVAL;
  610. if (type == THERMAL_TRIP_HOT) {
  611. ret = tz->ops->get_trip_temp(tz, i, temp);
  612. if (!ret)
  613. *trip = i;
  614. return ret;
  615. }
  616. }
  617. return -EINVAL;
  618. }
  619. /**
  620. * tegra_soctherm_set_hwtrips() - set HW trip point from DT data
  621. * @dev: struct device * of the SOC_THERM instance
  622. * @sg: pointer to the sensor group to set the thermtrip temperature for
  623. * @tz: struct thermal_zone_device *
  624. *
  625. * Configure the SOC_THERM HW trip points, setting "THERMTRIP"
  626. * "THROTTLE" trip points , using "thermtrips", "critical" or "hot"
  627. * type trip_temp
  628. * from thermal zone.
  629. * After they have been configured, THERMTRIP or THROTTLE will take
  630. * action when the configured SoC thermal sensor group reaches a
  631. * certain temperature.
  632. *
  633. * Return: 0 upon success, or a negative error code on failure.
  634. * "Success" does not mean that trips was enabled; it could also
  635. * mean that no node was found in DT.
  636. * THERMTRIP has been enabled successfully when a message similar to
  637. * this one appears on the serial console:
  638. * "thermtrip: will shut down when sensor group XXX reaches YYYYYY mC"
  639. * THROTTLE has been enabled successfully when a message similar to
  640. * this one appears on the serial console:
  641. * ""throttrip: will throttle when sensor group XXX reaches YYYYYY mC"
  642. */
  643. static int tegra_soctherm_set_hwtrips(struct device *dev,
  644. const struct tegra_tsensor_group *sg,
  645. struct thermal_zone_device *tz)
  646. {
  647. struct tegra_soctherm *ts = dev_get_drvdata(dev);
  648. struct soctherm_throt_cfg *stc;
  649. int i, trip, temperature, ret;
  650. /* Get thermtrips. If missing, try to get critical trips. */
  651. temperature = tsensor_group_thermtrip_get(ts, sg->id);
  652. if (min_low_temp == temperature)
  653. if (tz->ops->get_crit_temp(tz, &temperature))
  654. temperature = max_high_temp;
  655. ret = thermtrip_program(dev, sg, temperature);
  656. if (ret) {
  657. dev_err(dev, "thermtrip: %s: error during enable\n", sg->name);
  658. return ret;
  659. }
  660. dev_info(dev, "thermtrip: will shut down when %s reaches %d mC\n",
  661. sg->name, temperature);
  662. ret = get_hot_temp(tz, &trip, &temperature);
  663. if (ret) {
  664. dev_info(dev, "throttrip: %s: missing hot temperature\n",
  665. sg->name);
  666. return 0;
  667. }
  668. for (i = 0; i < THROTTLE_OC1; i++) {
  669. struct thermal_cooling_device *cdev;
  670. if (!ts->throt_cfgs[i].init)
  671. continue;
  672. cdev = ts->throt_cfgs[i].cdev;
  673. if (get_thermal_instance(tz, cdev, trip))
  674. stc = find_throttle_cfg_by_name(ts, cdev->type);
  675. else
  676. continue;
  677. ret = throttrip_program(dev, sg, stc, temperature);
  678. if (ret) {
  679. dev_err(dev, "throttrip: %s: error during enable\n",
  680. sg->name);
  681. return ret;
  682. }
  683. dev_info(dev,
  684. "throttrip: will throttle when %s reaches %d mC\n",
  685. sg->name, temperature);
  686. break;
  687. }
  688. if (i == THROTTLE_SIZE)
  689. dev_info(dev, "throttrip: %s: missing throttle cdev\n",
  690. sg->name);
  691. return 0;
  692. }
  693. static irqreturn_t soctherm_thermal_isr(int irq, void *dev_id)
  694. {
  695. struct tegra_soctherm *ts = dev_id;
  696. u32 r;
  697. /* Case for no lock:
  698. * Although interrupts are enabled in set_trips, there is still no need
  699. * to lock here because the interrupts are disabled before programming
  700. * new trip points. Hence there cant be a interrupt on the same sensor.
  701. * An interrupt can however occur on a sensor while trips are being
  702. * programmed on a different one. This beign a LEVEL interrupt won't
  703. * cause a new interrupt but this is taken care of by the re-reading of
  704. * the STATUS register in the thread function.
  705. */
  706. r = readl(ts->regs + THERMCTL_INTR_STATUS);
  707. writel(r, ts->regs + THERMCTL_INTR_DISABLE);
  708. return IRQ_WAKE_THREAD;
  709. }
  710. /**
  711. * soctherm_thermal_isr_thread() - Handles a thermal interrupt request
  712. * @irq: The interrupt number being requested; not used
  713. * @dev_id: Opaque pointer to tegra_soctherm;
  714. *
  715. * Clears the interrupt status register if there are expected
  716. * interrupt bits set.
  717. * The interrupt(s) are then handled by updating the corresponding
  718. * thermal zones.
  719. *
  720. * An error is logged if any unexpected interrupt bits are set.
  721. *
  722. * Disabled interrupts are re-enabled.
  723. *
  724. * Return: %IRQ_HANDLED. Interrupt was handled and no further processing
  725. * is needed.
  726. */
  727. static irqreturn_t soctherm_thermal_isr_thread(int irq, void *dev_id)
  728. {
  729. struct tegra_soctherm *ts = dev_id;
  730. struct thermal_zone_device *tz;
  731. u32 st, ex = 0, cp = 0, gp = 0, pl = 0, me = 0;
  732. st = readl(ts->regs + THERMCTL_INTR_STATUS);
  733. /* deliberately clear expected interrupts handled in SW */
  734. cp |= st & TH_INTR_CD0_MASK;
  735. cp |= st & TH_INTR_CU0_MASK;
  736. gp |= st & TH_INTR_GD0_MASK;
  737. gp |= st & TH_INTR_GU0_MASK;
  738. pl |= st & TH_INTR_PD0_MASK;
  739. pl |= st & TH_INTR_PU0_MASK;
  740. me |= st & TH_INTR_MD0_MASK;
  741. me |= st & TH_INTR_MU0_MASK;
  742. ex |= cp | gp | pl | me;
  743. if (ex) {
  744. writel(ex, ts->regs + THERMCTL_INTR_STATUS);
  745. st &= ~ex;
  746. if (cp) {
  747. tz = ts->thermctl_tzs[TEGRA124_SOCTHERM_SENSOR_CPU];
  748. thermal_zone_device_update(tz,
  749. THERMAL_EVENT_UNSPECIFIED);
  750. }
  751. if (gp) {
  752. tz = ts->thermctl_tzs[TEGRA124_SOCTHERM_SENSOR_GPU];
  753. thermal_zone_device_update(tz,
  754. THERMAL_EVENT_UNSPECIFIED);
  755. }
  756. if (pl) {
  757. tz = ts->thermctl_tzs[TEGRA124_SOCTHERM_SENSOR_PLLX];
  758. thermal_zone_device_update(tz,
  759. THERMAL_EVENT_UNSPECIFIED);
  760. }
  761. if (me) {
  762. tz = ts->thermctl_tzs[TEGRA124_SOCTHERM_SENSOR_MEM];
  763. thermal_zone_device_update(tz,
  764. THERMAL_EVENT_UNSPECIFIED);
  765. }
  766. }
  767. /* deliberately ignore expected interrupts NOT handled in SW */
  768. ex |= TH_INTR_IGNORE_MASK;
  769. st &= ~ex;
  770. if (st) {
  771. /* Whine about any other unexpected INTR bits still set */
  772. pr_err("soctherm: Ignored unexpected INTRs 0x%08x\n", st);
  773. writel(st, ts->regs + THERMCTL_INTR_STATUS);
  774. }
  775. return IRQ_HANDLED;
  776. }
  777. /**
  778. * soctherm_oc_intr_enable() - Enables the soctherm over-current interrupt
  779. * @ts: pointer to a struct tegra_soctherm
  780. * @alarm: The soctherm throttle id
  781. * @enable: Flag indicating enable the soctherm over-current
  782. * interrupt or disable it
  783. *
  784. * Enables a specific over-current pins @alarm to raise an interrupt if the flag
  785. * is set and the alarm corresponds to OC1, OC2, OC3, or OC4.
  786. */
  787. static void soctherm_oc_intr_enable(struct tegra_soctherm *ts,
  788. enum soctherm_throttle_id alarm,
  789. bool enable)
  790. {
  791. u32 r;
  792. if (!enable)
  793. return;
  794. r = readl(ts->regs + OC_INTR_ENABLE);
  795. switch (alarm) {
  796. case THROTTLE_OC1:
  797. r = REG_SET_MASK(r, OC_INTR_OC1_MASK, 1);
  798. break;
  799. case THROTTLE_OC2:
  800. r = REG_SET_MASK(r, OC_INTR_OC2_MASK, 1);
  801. break;
  802. case THROTTLE_OC3:
  803. r = REG_SET_MASK(r, OC_INTR_OC3_MASK, 1);
  804. break;
  805. case THROTTLE_OC4:
  806. r = REG_SET_MASK(r, OC_INTR_OC4_MASK, 1);
  807. break;
  808. default:
  809. r = 0;
  810. break;
  811. }
  812. writel(r, ts->regs + OC_INTR_ENABLE);
  813. }
  814. /**
  815. * soctherm_handle_alarm() - Handles soctherm alarms
  816. * @alarm: The soctherm throttle id
  817. *
  818. * "Handles" over-current alarms (OC1, OC2, OC3, and OC4) by printing
  819. * a warning or informative message.
  820. *
  821. * Return: -EINVAL for @alarm = THROTTLE_OC3, otherwise 0 (success).
  822. */
  823. static int soctherm_handle_alarm(enum soctherm_throttle_id alarm)
  824. {
  825. int rv = -EINVAL;
  826. switch (alarm) {
  827. case THROTTLE_OC1:
  828. pr_debug("soctherm: Successfully handled OC1 alarm\n");
  829. rv = 0;
  830. break;
  831. case THROTTLE_OC2:
  832. pr_debug("soctherm: Successfully handled OC2 alarm\n");
  833. rv = 0;
  834. break;
  835. case THROTTLE_OC3:
  836. pr_debug("soctherm: Successfully handled OC3 alarm\n");
  837. rv = 0;
  838. break;
  839. case THROTTLE_OC4:
  840. pr_debug("soctherm: Successfully handled OC4 alarm\n");
  841. rv = 0;
  842. break;
  843. default:
  844. break;
  845. }
  846. if (rv)
  847. pr_err("soctherm: ERROR in handling %s alarm\n",
  848. throt_names[alarm]);
  849. return rv;
  850. }
  851. /**
  852. * soctherm_edp_isr_thread() - log an over-current interrupt request
  853. * @irq: OC irq number. Currently not being used. See description
  854. * @arg: a void pointer for callback, currently not being used
  855. *
  856. * Over-current events are handled in hardware. This function is called to log
  857. * and handle any OC events that happened. Additionally, it checks every
  858. * over-current interrupt registers for registers are set but
  859. * was not expected (i.e. any discrepancy in interrupt status) by the function,
  860. * the discrepancy will logged.
  861. *
  862. * Return: %IRQ_HANDLED
  863. */
  864. static irqreturn_t soctherm_edp_isr_thread(int irq, void *arg)
  865. {
  866. struct tegra_soctherm *ts = arg;
  867. u32 st, ex, oc1, oc2, oc3, oc4;
  868. st = readl(ts->regs + OC_INTR_STATUS);
  869. /* deliberately clear expected interrupts handled in SW */
  870. oc1 = st & OC_INTR_OC1_MASK;
  871. oc2 = st & OC_INTR_OC2_MASK;
  872. oc3 = st & OC_INTR_OC3_MASK;
  873. oc4 = st & OC_INTR_OC4_MASK;
  874. ex = oc1 | oc2 | oc3 | oc4;
  875. pr_err("soctherm: OC ALARM 0x%08x\n", ex);
  876. if (ex) {
  877. writel(st, ts->regs + OC_INTR_STATUS);
  878. st &= ~ex;
  879. if (oc1 && !soctherm_handle_alarm(THROTTLE_OC1))
  880. soctherm_oc_intr_enable(ts, THROTTLE_OC1, true);
  881. if (oc2 && !soctherm_handle_alarm(THROTTLE_OC2))
  882. soctherm_oc_intr_enable(ts, THROTTLE_OC2, true);
  883. if (oc3 && !soctherm_handle_alarm(THROTTLE_OC3))
  884. soctherm_oc_intr_enable(ts, THROTTLE_OC3, true);
  885. if (oc4 && !soctherm_handle_alarm(THROTTLE_OC4))
  886. soctherm_oc_intr_enable(ts, THROTTLE_OC4, true);
  887. if (oc1 && soc_irq_cdata.irq_enable & BIT(0))
  888. handle_nested_irq(
  889. irq_find_mapping(soc_irq_cdata.domain, 0));
  890. if (oc2 && soc_irq_cdata.irq_enable & BIT(1))
  891. handle_nested_irq(
  892. irq_find_mapping(soc_irq_cdata.domain, 1));
  893. if (oc3 && soc_irq_cdata.irq_enable & BIT(2))
  894. handle_nested_irq(
  895. irq_find_mapping(soc_irq_cdata.domain, 2));
  896. if (oc4 && soc_irq_cdata.irq_enable & BIT(3))
  897. handle_nested_irq(
  898. irq_find_mapping(soc_irq_cdata.domain, 3));
  899. }
  900. if (st) {
  901. pr_err("soctherm: Ignored unexpected OC ALARM 0x%08x\n", st);
  902. writel(st, ts->regs + OC_INTR_STATUS);
  903. }
  904. return IRQ_HANDLED;
  905. }
  906. /**
  907. * soctherm_edp_isr() - Disables any active interrupts
  908. * @irq: The interrupt request number
  909. * @arg: Opaque pointer to an argument
  910. *
  911. * Writes to the OC_INTR_DISABLE register the over current interrupt status,
  912. * masking any asserted interrupts. Doing this prevents the same interrupts
  913. * from triggering this isr repeatedly. The thread woken by this isr will
  914. * handle asserted interrupts and subsequently unmask/re-enable them.
  915. *
  916. * The OC_INTR_DISABLE register indicates which OC interrupts
  917. * have been disabled.
  918. *
  919. * Return: %IRQ_WAKE_THREAD, handler requests to wake the handler thread
  920. */
  921. static irqreturn_t soctherm_edp_isr(int irq, void *arg)
  922. {
  923. struct tegra_soctherm *ts = arg;
  924. u32 r;
  925. if (!ts)
  926. return IRQ_NONE;
  927. r = readl(ts->regs + OC_INTR_STATUS);
  928. writel(r, ts->regs + OC_INTR_DISABLE);
  929. return IRQ_WAKE_THREAD;
  930. }
  931. /**
  932. * soctherm_oc_irq_lock() - locks the over-current interrupt request
  933. * @data: Interrupt request data
  934. *
  935. * Looks up the chip data from @data and locks the mutex associated with
  936. * a particular over-current interrupt request.
  937. */
  938. static void soctherm_oc_irq_lock(struct irq_data *data)
  939. {
  940. struct soctherm_oc_irq_chip_data *d = irq_data_get_irq_chip_data(data);
  941. mutex_lock(&d->irq_lock);
  942. }
  943. /**
  944. * soctherm_oc_irq_sync_unlock() - Unlocks the OC interrupt request
  945. * @data: Interrupt request data
  946. *
  947. * Looks up the interrupt request data @data and unlocks the mutex associated
  948. * with a particular over-current interrupt request.
  949. */
  950. static void soctherm_oc_irq_sync_unlock(struct irq_data *data)
  951. {
  952. struct soctherm_oc_irq_chip_data *d = irq_data_get_irq_chip_data(data);
  953. mutex_unlock(&d->irq_lock);
  954. }
  955. /**
  956. * soctherm_oc_irq_enable() - Enables the SOC_THERM over-current interrupt queue
  957. * @data: irq_data structure of the chip
  958. *
  959. * Sets the irq_enable bit of SOC_THERM allowing SOC_THERM
  960. * to respond to over-current interrupts.
  961. *
  962. */
  963. static void soctherm_oc_irq_enable(struct irq_data *data)
  964. {
  965. struct soctherm_oc_irq_chip_data *d = irq_data_get_irq_chip_data(data);
  966. d->irq_enable |= BIT(data->hwirq);
  967. }
  968. /**
  969. * soctherm_oc_irq_disable() - Disables overcurrent interrupt requests
  970. * @data: The interrupt request information
  971. *
  972. * Clears the interrupt request enable bit of the overcurrent
  973. * interrupt request chip data.
  974. *
  975. * Return: Nothing is returned (void)
  976. */
  977. static void soctherm_oc_irq_disable(struct irq_data *data)
  978. {
  979. struct soctherm_oc_irq_chip_data *d = irq_data_get_irq_chip_data(data);
  980. d->irq_enable &= ~BIT(data->hwirq);
  981. }
  982. static int soctherm_oc_irq_set_type(struct irq_data *data, unsigned int type)
  983. {
  984. return 0;
  985. }
  986. /**
  987. * soctherm_oc_irq_map() - SOC_THERM interrupt request domain mapper
  988. * @h: Interrupt request domain
  989. * @virq: Virtual interrupt request number
  990. * @hw: Hardware interrupt request number
  991. *
  992. * Mapping callback function for SOC_THERM's irq_domain. When a SOC_THERM
  993. * interrupt request is called, the irq_domain takes the request's virtual
  994. * request number (much like a virtual memory address) and maps it to a
  995. * physical hardware request number.
  996. *
  997. * When a mapping doesn't already exist for a virtual request number, the
  998. * irq_domain calls this function to associate the virtual request number with
  999. * a hardware request number.
  1000. *
  1001. * Return: 0
  1002. */
  1003. static int soctherm_oc_irq_map(struct irq_domain *h, unsigned int virq,
  1004. irq_hw_number_t hw)
  1005. {
  1006. struct soctherm_oc_irq_chip_data *data = h->host_data;
  1007. irq_set_chip_data(virq, data);
  1008. irq_set_chip(virq, &data->irq_chip);
  1009. irq_set_nested_thread(virq, 1);
  1010. return 0;
  1011. }
  1012. /**
  1013. * soctherm_irq_domain_xlate_twocell() - xlate for soctherm interrupts
  1014. * @d: Interrupt request domain
  1015. * @ctrlr: Controller device tree node
  1016. * @intspec: Array of u32s from DTs "interrupt" property
  1017. * @intsize: Number of values inside the intspec array
  1018. * @out_hwirq: HW IRQ value associated with this interrupt
  1019. * @out_type: The IRQ SENSE type for this interrupt.
  1020. *
  1021. * This Device Tree IRQ specifier translation function will translate a
  1022. * specific "interrupt" as defined by 2 DT values where the cell values map
  1023. * the hwirq number + 1 and linux irq flags. Since the output is the hwirq
  1024. * number, this function will subtract 1 from the value listed in DT.
  1025. *
  1026. * Return: 0
  1027. */
  1028. static int soctherm_irq_domain_xlate_twocell(struct irq_domain *d,
  1029. struct device_node *ctrlr, const u32 *intspec, unsigned int intsize,
  1030. irq_hw_number_t *out_hwirq, unsigned int *out_type)
  1031. {
  1032. if (WARN_ON(intsize < 2))
  1033. return -EINVAL;
  1034. /*
  1035. * The HW value is 1 index less than the DT IRQ values.
  1036. * i.e. OC4 goes to HW index 3.
  1037. */
  1038. *out_hwirq = intspec[0] - 1;
  1039. *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
  1040. return 0;
  1041. }
  1042. static const struct irq_domain_ops soctherm_oc_domain_ops = {
  1043. .map = soctherm_oc_irq_map,
  1044. .xlate = soctherm_irq_domain_xlate_twocell,
  1045. };
  1046. /**
  1047. * soctherm_oc_int_init() - Initial enabling of the over
  1048. * current interrupts
  1049. * @np: The devicetree node for soctherm
  1050. * @num_irqs: The number of new interrupt requests
  1051. *
  1052. * Sets the over current interrupt request chip data
  1053. *
  1054. * Return: 0 on success or if overcurrent interrupts are not enabled,
  1055. * -ENOMEM (out of memory), or irq_base if the function failed to
  1056. * allocate the irqs
  1057. */
  1058. static int soctherm_oc_int_init(struct device_node *np, int num_irqs)
  1059. {
  1060. if (!num_irqs) {
  1061. pr_info("%s(): OC interrupts are not enabled\n", __func__);
  1062. return 0;
  1063. }
  1064. mutex_init(&soc_irq_cdata.irq_lock);
  1065. soc_irq_cdata.irq_enable = 0;
  1066. soc_irq_cdata.irq_chip.name = "soc_therm_oc";
  1067. soc_irq_cdata.irq_chip.irq_bus_lock = soctherm_oc_irq_lock;
  1068. soc_irq_cdata.irq_chip.irq_bus_sync_unlock =
  1069. soctherm_oc_irq_sync_unlock;
  1070. soc_irq_cdata.irq_chip.irq_disable = soctherm_oc_irq_disable;
  1071. soc_irq_cdata.irq_chip.irq_enable = soctherm_oc_irq_enable;
  1072. soc_irq_cdata.irq_chip.irq_set_type = soctherm_oc_irq_set_type;
  1073. soc_irq_cdata.irq_chip.irq_set_wake = NULL;
  1074. soc_irq_cdata.domain = irq_domain_add_linear(np, num_irqs,
  1075. &soctherm_oc_domain_ops,
  1076. &soc_irq_cdata);
  1077. if (!soc_irq_cdata.domain) {
  1078. pr_err("%s: Failed to create IRQ domain\n", __func__);
  1079. return -ENOMEM;
  1080. }
  1081. pr_debug("%s(): OC interrupts enabled successful\n", __func__);
  1082. return 0;
  1083. }
  1084. #ifdef CONFIG_DEBUG_FS
  1085. static int regs_show(struct seq_file *s, void *data)
  1086. {
  1087. struct platform_device *pdev = s->private;
  1088. struct tegra_soctherm *ts = platform_get_drvdata(pdev);
  1089. const struct tegra_tsensor *tsensors = ts->soc->tsensors;
  1090. const struct tegra_tsensor_group **ttgs = ts->soc->ttgs;
  1091. u32 r, state;
  1092. int i, level;
  1093. seq_puts(s, "-----TSENSE (convert HW)-----\n");
  1094. for (i = 0; i < ts->soc->num_tsensors; i++) {
  1095. r = readl(ts->regs + tsensors[i].base + SENSOR_CONFIG1);
  1096. state = REG_GET_MASK(r, SENSOR_CONFIG1_TEMP_ENABLE);
  1097. seq_printf(s, "%s: ", tsensors[i].name);
  1098. seq_printf(s, "En(%d) ", state);
  1099. if (!state) {
  1100. seq_puts(s, "\n");
  1101. continue;
  1102. }
  1103. state = REG_GET_MASK(r, SENSOR_CONFIG1_TIDDQ_EN_MASK);
  1104. seq_printf(s, "tiddq(%d) ", state);
  1105. state = REG_GET_MASK(r, SENSOR_CONFIG1_TEN_COUNT_MASK);
  1106. seq_printf(s, "ten_count(%d) ", state);
  1107. state = REG_GET_MASK(r, SENSOR_CONFIG1_TSAMPLE_MASK);
  1108. seq_printf(s, "tsample(%d) ", state + 1);
  1109. r = readl(ts->regs + tsensors[i].base + SENSOR_STATUS1);
  1110. state = REG_GET_MASK(r, SENSOR_STATUS1_TEMP_VALID_MASK);
  1111. seq_printf(s, "Temp(%d/", state);
  1112. state = REG_GET_MASK(r, SENSOR_STATUS1_TEMP_MASK);
  1113. seq_printf(s, "%d) ", translate_temp(state));
  1114. r = readl(ts->regs + tsensors[i].base + SENSOR_STATUS0);
  1115. state = REG_GET_MASK(r, SENSOR_STATUS0_VALID_MASK);
  1116. seq_printf(s, "Capture(%d/", state);
  1117. state = REG_GET_MASK(r, SENSOR_STATUS0_CAPTURE_MASK);
  1118. seq_printf(s, "%d) ", state);
  1119. r = readl(ts->regs + tsensors[i].base + SENSOR_CONFIG0);
  1120. state = REG_GET_MASK(r, SENSOR_CONFIG0_STOP);
  1121. seq_printf(s, "Stop(%d) ", state);
  1122. state = REG_GET_MASK(r, SENSOR_CONFIG0_TALL_MASK);
  1123. seq_printf(s, "Tall(%d) ", state);
  1124. state = REG_GET_MASK(r, SENSOR_CONFIG0_TCALC_OVER);
  1125. seq_printf(s, "Over(%d/", state);
  1126. state = REG_GET_MASK(r, SENSOR_CONFIG0_OVER);
  1127. seq_printf(s, "%d/", state);
  1128. state = REG_GET_MASK(r, SENSOR_CONFIG0_CPTR_OVER);
  1129. seq_printf(s, "%d) ", state);
  1130. r = readl(ts->regs + tsensors[i].base + SENSOR_CONFIG2);
  1131. state = REG_GET_MASK(r, SENSOR_CONFIG2_THERMA_MASK);
  1132. seq_printf(s, "Therm_A/B(%d/", state);
  1133. state = REG_GET_MASK(r, SENSOR_CONFIG2_THERMB_MASK);
  1134. seq_printf(s, "%d)\n", (s16)state);
  1135. }
  1136. r = readl(ts->regs + SENSOR_PDIV);
  1137. seq_printf(s, "PDIV: 0x%x\n", r);
  1138. r = readl(ts->regs + SENSOR_HOTSPOT_OFF);
  1139. seq_printf(s, "HOTSPOT: 0x%x\n", r);
  1140. seq_puts(s, "\n");
  1141. seq_puts(s, "-----SOC_THERM-----\n");
  1142. r = readl(ts->regs + SENSOR_TEMP1);
  1143. state = REG_GET_MASK(r, SENSOR_TEMP1_CPU_TEMP_MASK);
  1144. seq_printf(s, "Temperatures: CPU(%d) ", translate_temp(state));
  1145. state = REG_GET_MASK(r, SENSOR_TEMP1_GPU_TEMP_MASK);
  1146. seq_printf(s, " GPU(%d) ", translate_temp(state));
  1147. r = readl(ts->regs + SENSOR_TEMP2);
  1148. state = REG_GET_MASK(r, SENSOR_TEMP2_PLLX_TEMP_MASK);
  1149. seq_printf(s, " PLLX(%d) ", translate_temp(state));
  1150. state = REG_GET_MASK(r, SENSOR_TEMP2_MEM_TEMP_MASK);
  1151. seq_printf(s, " MEM(%d)\n", translate_temp(state));
  1152. for (i = 0; i < ts->soc->num_ttgs; i++) {
  1153. seq_printf(s, "%s:\n", ttgs[i]->name);
  1154. for (level = 0; level < 4; level++) {
  1155. s32 v;
  1156. u32 mask;
  1157. u16 off = ttgs[i]->thermctl_lvl0_offset;
  1158. r = readl(ts->regs + THERMCTL_LVL_REG(off, level));
  1159. mask = ttgs[i]->thermctl_lvl0_up_thresh_mask;
  1160. state = REG_GET_MASK(r, mask);
  1161. v = sign_extend32(state, ts->soc->bptt - 1);
  1162. v *= ts->soc->thresh_grain;
  1163. seq_printf(s, " %d: Up/Dn(%d /", level, v);
  1164. mask = ttgs[i]->thermctl_lvl0_dn_thresh_mask;
  1165. state = REG_GET_MASK(r, mask);
  1166. v = sign_extend32(state, ts->soc->bptt - 1);
  1167. v *= ts->soc->thresh_grain;
  1168. seq_printf(s, "%d ) ", v);
  1169. mask = THERMCTL_LVL0_CPU0_EN_MASK;
  1170. state = REG_GET_MASK(r, mask);
  1171. seq_printf(s, "En(%d) ", state);
  1172. mask = THERMCTL_LVL0_CPU0_CPU_THROT_MASK;
  1173. state = REG_GET_MASK(r, mask);
  1174. seq_puts(s, "CPU Throt");
  1175. if (!state)
  1176. seq_printf(s, "(%s) ", "none");
  1177. else if (state == THERMCTL_LVL0_CPU0_CPU_THROT_LIGHT)
  1178. seq_printf(s, "(%s) ", "L");
  1179. else if (state == THERMCTL_LVL0_CPU0_CPU_THROT_HEAVY)
  1180. seq_printf(s, "(%s) ", "H");
  1181. else
  1182. seq_printf(s, "(%s) ", "H+L");
  1183. mask = THERMCTL_LVL0_CPU0_GPU_THROT_MASK;
  1184. state = REG_GET_MASK(r, mask);
  1185. seq_puts(s, "GPU Throt");
  1186. if (!state)
  1187. seq_printf(s, "(%s) ", "none");
  1188. else if (state == THERMCTL_LVL0_CPU0_GPU_THROT_LIGHT)
  1189. seq_printf(s, "(%s) ", "L");
  1190. else if (state == THERMCTL_LVL0_CPU0_GPU_THROT_HEAVY)
  1191. seq_printf(s, "(%s) ", "H");
  1192. else
  1193. seq_printf(s, "(%s) ", "H+L");
  1194. mask = THERMCTL_LVL0_CPU0_STATUS_MASK;
  1195. state = REG_GET_MASK(r, mask);
  1196. seq_printf(s, "Status(%s)\n",
  1197. state == 0 ? "LO" :
  1198. state == 1 ? "In" :
  1199. state == 2 ? "Res" : "HI");
  1200. }
  1201. }
  1202. r = readl(ts->regs + THERMCTL_STATS_CTL);
  1203. seq_printf(s, "STATS: Up(%s) Dn(%s)\n",
  1204. r & STATS_CTL_EN_UP ? "En" : "--",
  1205. r & STATS_CTL_EN_DN ? "En" : "--");
  1206. for (level = 0; level < 4; level++) {
  1207. u16 off;
  1208. off = THERMCTL_LVL0_UP_STATS;
  1209. r = readl(ts->regs + THERMCTL_LVL_REG(off, level));
  1210. seq_printf(s, " Level_%d Up(%d) ", level, r);
  1211. off = THERMCTL_LVL0_DN_STATS;
  1212. r = readl(ts->regs + THERMCTL_LVL_REG(off, level));
  1213. seq_printf(s, "Dn(%d)\n", r);
  1214. }
  1215. r = readl(ts->regs + THERMCTL_THERMTRIP_CTL);
  1216. state = REG_GET_MASK(r, ttgs[0]->thermtrip_any_en_mask);
  1217. seq_printf(s, "Thermtrip Any En(%d)\n", state);
  1218. for (i = 0; i < ts->soc->num_ttgs; i++) {
  1219. state = REG_GET_MASK(r, ttgs[i]->thermtrip_enable_mask);
  1220. seq_printf(s, " %s En(%d) ", ttgs[i]->name, state);
  1221. state = REG_GET_MASK(r, ttgs[i]->thermtrip_threshold_mask);
  1222. state *= ts->soc->thresh_grain;
  1223. seq_printf(s, "Thresh(%d)\n", state);
  1224. }
  1225. r = readl(ts->regs + THROT_GLOBAL_CFG);
  1226. seq_puts(s, "\n");
  1227. seq_printf(s, "GLOBAL THROTTLE CONFIG: 0x%08x\n", r);
  1228. seq_puts(s, "---------------------------------------------------\n");
  1229. r = readl(ts->regs + THROT_STATUS);
  1230. state = REG_GET_MASK(r, THROT_STATUS_BREACH_MASK);
  1231. seq_printf(s, "THROT STATUS: breach(%d) ", state);
  1232. state = REG_GET_MASK(r, THROT_STATUS_STATE_MASK);
  1233. seq_printf(s, "state(%d) ", state);
  1234. state = REG_GET_MASK(r, THROT_STATUS_ENABLED_MASK);
  1235. seq_printf(s, "enabled(%d)\n", state);
  1236. r = readl(ts->regs + CPU_PSKIP_STATUS);
  1237. if (ts->soc->use_ccroc) {
  1238. state = REG_GET_MASK(r, XPU_PSKIP_STATUS_ENABLED_MASK);
  1239. seq_printf(s, "CPU PSKIP STATUS: enabled(%d)\n", state);
  1240. } else {
  1241. state = REG_GET_MASK(r, XPU_PSKIP_STATUS_M_MASK);
  1242. seq_printf(s, "CPU PSKIP STATUS: M(%d) ", state);
  1243. state = REG_GET_MASK(r, XPU_PSKIP_STATUS_N_MASK);
  1244. seq_printf(s, "N(%d) ", state);
  1245. state = REG_GET_MASK(r, XPU_PSKIP_STATUS_ENABLED_MASK);
  1246. seq_printf(s, "enabled(%d)\n", state);
  1247. }
  1248. return 0;
  1249. }
  1250. DEFINE_SHOW_ATTRIBUTE(regs);
  1251. static void soctherm_debug_init(struct platform_device *pdev)
  1252. {
  1253. struct tegra_soctherm *tegra = platform_get_drvdata(pdev);
  1254. struct dentry *root;
  1255. root = debugfs_create_dir("soctherm", NULL);
  1256. tegra->debugfs_dir = root;
  1257. debugfs_create_file("reg_contents", 0644, root, pdev, &regs_fops);
  1258. }
  1259. #else
  1260. static inline void soctherm_debug_init(struct platform_device *pdev) {}
  1261. #endif
  1262. static int soctherm_clk_enable(struct platform_device *pdev, bool enable)
  1263. {
  1264. struct tegra_soctherm *tegra = platform_get_drvdata(pdev);
  1265. int err;
  1266. if (!tegra->clock_soctherm || !tegra->clock_tsensor)
  1267. return -EINVAL;
  1268. reset_control_assert(tegra->reset);
  1269. if (enable) {
  1270. err = clk_prepare_enable(tegra->clock_soctherm);
  1271. if (err) {
  1272. reset_control_deassert(tegra->reset);
  1273. return err;
  1274. }
  1275. err = clk_prepare_enable(tegra->clock_tsensor);
  1276. if (err) {
  1277. clk_disable_unprepare(tegra->clock_soctherm);
  1278. reset_control_deassert(tegra->reset);
  1279. return err;
  1280. }
  1281. } else {
  1282. clk_disable_unprepare(tegra->clock_tsensor);
  1283. clk_disable_unprepare(tegra->clock_soctherm);
  1284. }
  1285. reset_control_deassert(tegra->reset);
  1286. return 0;
  1287. }
  1288. static int throt_get_cdev_max_state(struct thermal_cooling_device *cdev,
  1289. unsigned long *max_state)
  1290. {
  1291. *max_state = 1;
  1292. return 0;
  1293. }
  1294. static int throt_get_cdev_cur_state(struct thermal_cooling_device *cdev,
  1295. unsigned long *cur_state)
  1296. {
  1297. struct tegra_soctherm *ts = cdev->devdata;
  1298. u32 r;
  1299. r = readl(ts->regs + THROT_STATUS);
  1300. if (REG_GET_MASK(r, THROT_STATUS_STATE_MASK))
  1301. *cur_state = 1;
  1302. else
  1303. *cur_state = 0;
  1304. return 0;
  1305. }
  1306. static int throt_set_cdev_state(struct thermal_cooling_device *cdev,
  1307. unsigned long cur_state)
  1308. {
  1309. return 0;
  1310. }
  1311. static const struct thermal_cooling_device_ops throt_cooling_ops = {
  1312. .get_max_state = throt_get_cdev_max_state,
  1313. .get_cur_state = throt_get_cdev_cur_state,
  1314. .set_cur_state = throt_set_cdev_state,
  1315. };
  1316. static int soctherm_thermtrips_parse(struct platform_device *pdev)
  1317. {
  1318. struct device *dev = &pdev->dev;
  1319. struct tegra_soctherm *ts = dev_get_drvdata(dev);
  1320. struct tsensor_group_thermtrips *tt = ts->soc->thermtrips;
  1321. const int max_num_prop = ts->soc->num_ttgs * 2;
  1322. u32 *tlb;
  1323. int i, j, n, ret;
  1324. if (!tt)
  1325. return -ENOMEM;
  1326. n = of_property_count_u32_elems(dev->of_node, "nvidia,thermtrips");
  1327. if (n <= 0) {
  1328. dev_info(dev,
  1329. "missing thermtrips, will use critical trips as shut down temp\n");
  1330. return n;
  1331. }
  1332. n = min(max_num_prop, n);
  1333. tlb = devm_kcalloc(&pdev->dev, max_num_prop, sizeof(u32), GFP_KERNEL);
  1334. if (!tlb)
  1335. return -ENOMEM;
  1336. ret = of_property_read_u32_array(dev->of_node, "nvidia,thermtrips",
  1337. tlb, n);
  1338. if (ret) {
  1339. dev_err(dev, "invalid num ele: thermtrips:%d\n", ret);
  1340. return ret;
  1341. }
  1342. i = 0;
  1343. for (j = 0; j < n; j = j + 2) {
  1344. if (tlb[j] >= TEGRA124_SOCTHERM_SENSOR_NUM)
  1345. continue;
  1346. tt[i].id = tlb[j];
  1347. tt[i].temp = tlb[j + 1];
  1348. i++;
  1349. }
  1350. return 0;
  1351. }
  1352. static void soctherm_oc_cfg_parse(struct device *dev,
  1353. struct device_node *np_oc,
  1354. struct soctherm_throt_cfg *stc)
  1355. {
  1356. u32 val;
  1357. if (of_property_read_bool(np_oc, "nvidia,polarity-active-low"))
  1358. stc->oc_cfg.active_low = 1;
  1359. else
  1360. stc->oc_cfg.active_low = 0;
  1361. if (!of_property_read_u32(np_oc, "nvidia,count-threshold", &val)) {
  1362. stc->oc_cfg.intr_en = 1;
  1363. stc->oc_cfg.alarm_cnt_thresh = val;
  1364. }
  1365. if (!of_property_read_u32(np_oc, "nvidia,throttle-period-us", &val))
  1366. stc->oc_cfg.throt_period = val;
  1367. if (!of_property_read_u32(np_oc, "nvidia,alarm-filter", &val))
  1368. stc->oc_cfg.alarm_filter = val;
  1369. /* BRIEF throttling by default, do not support STICKY */
  1370. stc->oc_cfg.mode = OC_THROTTLE_MODE_BRIEF;
  1371. }
  1372. static int soctherm_throt_cfg_parse(struct device *dev,
  1373. struct device_node *np,
  1374. struct soctherm_throt_cfg *stc)
  1375. {
  1376. struct tegra_soctherm *ts = dev_get_drvdata(dev);
  1377. int ret;
  1378. u32 val;
  1379. ret = of_property_read_u32(np, "nvidia,priority", &val);
  1380. if (ret) {
  1381. dev_err(dev, "throttle-cfg: %s: invalid priority\n", stc->name);
  1382. return -EINVAL;
  1383. }
  1384. stc->priority = val;
  1385. ret = of_property_read_u32(np, ts->soc->use_ccroc ?
  1386. "nvidia,cpu-throt-level" :
  1387. "nvidia,cpu-throt-percent", &val);
  1388. if (!ret) {
  1389. if (ts->soc->use_ccroc &&
  1390. val <= TEGRA_SOCTHERM_THROT_LEVEL_HIGH)
  1391. stc->cpu_throt_level = val;
  1392. else if (!ts->soc->use_ccroc && val <= 100)
  1393. stc->cpu_throt_depth = val;
  1394. else
  1395. goto err;
  1396. } else {
  1397. goto err;
  1398. }
  1399. ret = of_property_read_u32(np, "nvidia,gpu-throt-level", &val);
  1400. if (!ret && val <= TEGRA_SOCTHERM_THROT_LEVEL_HIGH)
  1401. stc->gpu_throt_level = val;
  1402. else
  1403. goto err;
  1404. return 0;
  1405. err:
  1406. dev_err(dev, "throttle-cfg: %s: no throt prop or invalid prop\n",
  1407. stc->name);
  1408. return -EINVAL;
  1409. }
  1410. /**
  1411. * soctherm_init_hw_throt_cdev() - Parse the HW throttle configurations
  1412. * and register them as cooling devices.
  1413. * @pdev: Pointer to platform_device struct
  1414. */
  1415. static void soctherm_init_hw_throt_cdev(struct platform_device *pdev)
  1416. {
  1417. struct device *dev = &pdev->dev;
  1418. struct tegra_soctherm *ts = dev_get_drvdata(dev);
  1419. struct device_node *np_stc, *np_stcc;
  1420. const char *name;
  1421. int i;
  1422. for (i = 0; i < THROTTLE_SIZE; i++) {
  1423. ts->throt_cfgs[i].name = throt_names[i];
  1424. ts->throt_cfgs[i].id = i;
  1425. ts->throt_cfgs[i].init = false;
  1426. }
  1427. np_stc = of_get_child_by_name(dev->of_node, "throttle-cfgs");
  1428. if (!np_stc) {
  1429. dev_info(dev,
  1430. "throttle-cfg: no throttle-cfgs - not enabling\n");
  1431. return;
  1432. }
  1433. for_each_child_of_node(np_stc, np_stcc) {
  1434. struct soctherm_throt_cfg *stc;
  1435. struct thermal_cooling_device *tcd;
  1436. int err;
  1437. name = np_stcc->name;
  1438. stc = find_throttle_cfg_by_name(ts, name);
  1439. if (!stc) {
  1440. dev_err(dev,
  1441. "throttle-cfg: could not find %s\n", name);
  1442. continue;
  1443. }
  1444. if (stc->init) {
  1445. dev_err(dev, "throttle-cfg: %s: redefined!\n", name);
  1446. of_node_put(np_stcc);
  1447. break;
  1448. }
  1449. err = soctherm_throt_cfg_parse(dev, np_stcc, stc);
  1450. if (err)
  1451. continue;
  1452. if (stc->id >= THROTTLE_OC1) {
  1453. soctherm_oc_cfg_parse(dev, np_stcc, stc);
  1454. stc->init = true;
  1455. } else {
  1456. tcd = thermal_of_cooling_device_register(np_stcc,
  1457. (char *)name, ts,
  1458. &throt_cooling_ops);
  1459. if (IS_ERR_OR_NULL(tcd)) {
  1460. dev_err(dev,
  1461. "throttle-cfg: %s: failed to register cooling device\n",
  1462. name);
  1463. continue;
  1464. }
  1465. stc->cdev = tcd;
  1466. stc->init = true;
  1467. }
  1468. }
  1469. of_node_put(np_stc);
  1470. }
  1471. /**
  1472. * throttlectl_cpu_level_cfg() - programs CCROC NV_THERM level config
  1473. * @ts: pointer to a struct tegra_soctherm
  1474. * @level: describing the level LOW/MED/HIGH of throttling
  1475. *
  1476. * It's necessary to set up the CPU-local CCROC NV_THERM instance with
  1477. * the M/N values desired for each level. This function does this.
  1478. *
  1479. * This function pre-programs the CCROC NV_THERM levels in terms of
  1480. * pre-configured "Low", "Medium" or "Heavy" throttle levels which are
  1481. * mapped to THROT_LEVEL_LOW, THROT_LEVEL_MED and THROT_LEVEL_HVY.
  1482. */
  1483. static void throttlectl_cpu_level_cfg(struct tegra_soctherm *ts, int level)
  1484. {
  1485. u8 depth, dividend;
  1486. u32 r;
  1487. switch (level) {
  1488. case TEGRA_SOCTHERM_THROT_LEVEL_LOW:
  1489. depth = 50;
  1490. break;
  1491. case TEGRA_SOCTHERM_THROT_LEVEL_MED:
  1492. depth = 75;
  1493. break;
  1494. case TEGRA_SOCTHERM_THROT_LEVEL_HIGH:
  1495. depth = 80;
  1496. break;
  1497. case TEGRA_SOCTHERM_THROT_LEVEL_NONE:
  1498. return;
  1499. default:
  1500. return;
  1501. }
  1502. dividend = THROT_DEPTH_DIVIDEND(depth);
  1503. /* setup PSKIP in ccroc nv_therm registers */
  1504. r = ccroc_readl(ts, CCROC_THROT_PSKIP_RAMP_CPU_REG(level));
  1505. r = REG_SET_MASK(r, CCROC_THROT_PSKIP_RAMP_DURATION_MASK, 0xff);
  1506. r = REG_SET_MASK(r, CCROC_THROT_PSKIP_RAMP_STEP_MASK, 0xf);
  1507. ccroc_writel(ts, r, CCROC_THROT_PSKIP_RAMP_CPU_REG(level));
  1508. r = ccroc_readl(ts, CCROC_THROT_PSKIP_CTRL_CPU_REG(level));
  1509. r = REG_SET_MASK(r, CCROC_THROT_PSKIP_CTRL_ENB_MASK, 1);
  1510. r = REG_SET_MASK(r, CCROC_THROT_PSKIP_CTRL_DIVIDEND_MASK, dividend);
  1511. r = REG_SET_MASK(r, CCROC_THROT_PSKIP_CTRL_DIVISOR_MASK, 0xff);
  1512. ccroc_writel(ts, r, CCROC_THROT_PSKIP_CTRL_CPU_REG(level));
  1513. }
  1514. /**
  1515. * throttlectl_cpu_level_select() - program CPU pulse skipper config
  1516. * @ts: pointer to a struct tegra_soctherm
  1517. * @throt: the LIGHT/HEAVY of throttle event id
  1518. *
  1519. * Pulse skippers are used to throttle clock frequencies. This
  1520. * function programs the pulse skippers based on @throt and platform
  1521. * data. This function is used on SoCs which have CPU-local pulse
  1522. * skipper control, such as T13x. It programs soctherm's interface to
  1523. * Denver:CCROC NV_THERM in terms of Low, Medium and HIGH throttling
  1524. * vectors. PSKIP_BYPASS mode is set as required per HW spec.
  1525. */
  1526. static void throttlectl_cpu_level_select(struct tegra_soctherm *ts,
  1527. enum soctherm_throttle_id throt)
  1528. {
  1529. u32 r, throt_vect;
  1530. /* Denver:CCROC NV_THERM interface N:3 Mapping */
  1531. switch (ts->throt_cfgs[throt].cpu_throt_level) {
  1532. case TEGRA_SOCTHERM_THROT_LEVEL_LOW:
  1533. throt_vect = THROT_VECT_LOW;
  1534. break;
  1535. case TEGRA_SOCTHERM_THROT_LEVEL_MED:
  1536. throt_vect = THROT_VECT_MED;
  1537. break;
  1538. case TEGRA_SOCTHERM_THROT_LEVEL_HIGH:
  1539. throt_vect = THROT_VECT_HIGH;
  1540. break;
  1541. default:
  1542. throt_vect = THROT_VECT_NONE;
  1543. break;
  1544. }
  1545. r = readl(ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU));
  1546. r = REG_SET_MASK(r, THROT_PSKIP_CTRL_ENABLE_MASK, 1);
  1547. r = REG_SET_MASK(r, THROT_PSKIP_CTRL_VECT_CPU_MASK, throt_vect);
  1548. r = REG_SET_MASK(r, THROT_PSKIP_CTRL_VECT2_CPU_MASK, throt_vect);
  1549. writel(r, ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU));
  1550. /* bypass sequencer in soc_therm as it is programmed in ccroc */
  1551. r = REG_SET_MASK(0, THROT_PSKIP_RAMP_SEQ_BYPASS_MODE_MASK, 1);
  1552. writel(r, ts->regs + THROT_PSKIP_RAMP(throt, THROTTLE_DEV_CPU));
  1553. }
  1554. /**
  1555. * throttlectl_cpu_mn() - program CPU pulse skipper configuration
  1556. * @ts: pointer to a struct tegra_soctherm
  1557. * @throt: the LIGHT/HEAVY of throttle event id
  1558. *
  1559. * Pulse skippers are used to throttle clock frequencies. This
  1560. * function programs the pulse skippers based on @throt and platform
  1561. * data. This function is used for CPUs that have "remote" pulse
  1562. * skipper control, e.g., the CPU pulse skipper is controlled by the
  1563. * SOC_THERM IP block. (SOC_THERM is located outside the CPU
  1564. * complex.)
  1565. */
  1566. static void throttlectl_cpu_mn(struct tegra_soctherm *ts,
  1567. enum soctherm_throttle_id throt)
  1568. {
  1569. u32 r;
  1570. int depth;
  1571. u8 dividend;
  1572. depth = ts->throt_cfgs[throt].cpu_throt_depth;
  1573. dividend = THROT_DEPTH_DIVIDEND(depth);
  1574. r = readl(ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU));
  1575. r = REG_SET_MASK(r, THROT_PSKIP_CTRL_ENABLE_MASK, 1);
  1576. r = REG_SET_MASK(r, THROT_PSKIP_CTRL_DIVIDEND_MASK, dividend);
  1577. r = REG_SET_MASK(r, THROT_PSKIP_CTRL_DIVISOR_MASK, 0xff);
  1578. writel(r, ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU));
  1579. r = readl(ts->regs + THROT_PSKIP_RAMP(throt, THROTTLE_DEV_CPU));
  1580. r = REG_SET_MASK(r, THROT_PSKIP_RAMP_DURATION_MASK, 0xff);
  1581. r = REG_SET_MASK(r, THROT_PSKIP_RAMP_STEP_MASK, 0xf);
  1582. writel(r, ts->regs + THROT_PSKIP_RAMP(throt, THROTTLE_DEV_CPU));
  1583. }
  1584. /**
  1585. * throttlectl_gpu_level_select() - selects throttling level for GPU
  1586. * @ts: pointer to a struct tegra_soctherm
  1587. * @throt: the LIGHT/HEAVY of throttle event id
  1588. *
  1589. * This function programs soctherm's interface to GK20a NV_THERM to select
  1590. * pre-configured "Low", "Medium" or "Heavy" throttle levels.
  1591. *
  1592. * Return: boolean true if HW was programmed
  1593. */
  1594. static void throttlectl_gpu_level_select(struct tegra_soctherm *ts,
  1595. enum soctherm_throttle_id throt)
  1596. {
  1597. u32 r, level, throt_vect;
  1598. level = ts->throt_cfgs[throt].gpu_throt_level;
  1599. throt_vect = THROT_LEVEL_TO_DEPTH(level);
  1600. r = readl(ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_GPU));
  1601. r = REG_SET_MASK(r, THROT_PSKIP_CTRL_ENABLE_MASK, 1);
  1602. r = REG_SET_MASK(r, THROT_PSKIP_CTRL_VECT_GPU_MASK, throt_vect);
  1603. writel(r, ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_GPU));
  1604. }
  1605. static int soctherm_oc_cfg_program(struct tegra_soctherm *ts,
  1606. enum soctherm_throttle_id throt)
  1607. {
  1608. u32 r;
  1609. struct soctherm_oc_cfg *oc = &ts->throt_cfgs[throt].oc_cfg;
  1610. if (oc->mode == OC_THROTTLE_MODE_DISABLED)
  1611. return -EINVAL;
  1612. r = REG_SET_MASK(0, OC1_CFG_HW_RESTORE_MASK, 1);
  1613. r = REG_SET_MASK(r, OC1_CFG_THROTTLE_MODE_MASK, oc->mode);
  1614. r = REG_SET_MASK(r, OC1_CFG_ALARM_POLARITY_MASK, oc->active_low);
  1615. r = REG_SET_MASK(r, OC1_CFG_EN_THROTTLE_MASK, 1);
  1616. writel(r, ts->regs + ALARM_CFG(throt));
  1617. writel(oc->throt_period, ts->regs + ALARM_THROTTLE_PERIOD(throt));
  1618. writel(oc->alarm_cnt_thresh, ts->regs + ALARM_CNT_THRESHOLD(throt));
  1619. writel(oc->alarm_filter, ts->regs + ALARM_FILTER(throt));
  1620. soctherm_oc_intr_enable(ts, throt, oc->intr_en);
  1621. return 0;
  1622. }
  1623. /**
  1624. * soctherm_throttle_program() - programs pulse skippers' configuration
  1625. * @ts: pointer to a struct tegra_soctherm
  1626. * @throt: the LIGHT/HEAVY of the throttle event id.
  1627. *
  1628. * Pulse skippers are used to throttle clock frequencies.
  1629. * This function programs the pulse skippers.
  1630. */
  1631. static void soctherm_throttle_program(struct tegra_soctherm *ts,
  1632. enum soctherm_throttle_id throt)
  1633. {
  1634. u32 r;
  1635. struct soctherm_throt_cfg stc = ts->throt_cfgs[throt];
  1636. if (!stc.init)
  1637. return;
  1638. if ((throt >= THROTTLE_OC1) && (soctherm_oc_cfg_program(ts, throt)))
  1639. return;
  1640. /* Setup PSKIP parameters */
  1641. if (ts->soc->use_ccroc)
  1642. throttlectl_cpu_level_select(ts, throt);
  1643. else
  1644. throttlectl_cpu_mn(ts, throt);
  1645. throttlectl_gpu_level_select(ts, throt);
  1646. r = REG_SET_MASK(0, THROT_PRIORITY_LITE_PRIO_MASK, stc.priority);
  1647. writel(r, ts->regs + THROT_PRIORITY_CTRL(throt));
  1648. r = REG_SET_MASK(0, THROT_DELAY_LITE_DELAY_MASK, 0);
  1649. writel(r, ts->regs + THROT_DELAY_CTRL(throt));
  1650. r = readl(ts->regs + THROT_PRIORITY_LOCK);
  1651. r = REG_GET_MASK(r, THROT_PRIORITY_LOCK_PRIORITY_MASK);
  1652. if (r >= stc.priority)
  1653. return;
  1654. r = REG_SET_MASK(0, THROT_PRIORITY_LOCK_PRIORITY_MASK,
  1655. stc.priority);
  1656. writel(r, ts->regs + THROT_PRIORITY_LOCK);
  1657. }
  1658. static void tegra_soctherm_throttle(struct device *dev)
  1659. {
  1660. struct tegra_soctherm *ts = dev_get_drvdata(dev);
  1661. u32 v;
  1662. int i;
  1663. /* configure LOW, MED and HIGH levels for CCROC NV_THERM */
  1664. if (ts->soc->use_ccroc) {
  1665. throttlectl_cpu_level_cfg(ts, TEGRA_SOCTHERM_THROT_LEVEL_LOW);
  1666. throttlectl_cpu_level_cfg(ts, TEGRA_SOCTHERM_THROT_LEVEL_MED);
  1667. throttlectl_cpu_level_cfg(ts, TEGRA_SOCTHERM_THROT_LEVEL_HIGH);
  1668. }
  1669. /* Thermal HW throttle programming */
  1670. for (i = 0; i < THROTTLE_SIZE; i++)
  1671. soctherm_throttle_program(ts, i);
  1672. v = REG_SET_MASK(0, THROT_GLOBAL_ENB_MASK, 1);
  1673. if (ts->soc->use_ccroc) {
  1674. ccroc_writel(ts, v, CCROC_GLOBAL_CFG);
  1675. v = ccroc_readl(ts, CCROC_SUPER_CCLKG_DIVIDER);
  1676. v = REG_SET_MASK(v, CDIVG_USE_THERM_CONTROLS_MASK, 1);
  1677. ccroc_writel(ts, v, CCROC_SUPER_CCLKG_DIVIDER);
  1678. } else {
  1679. writel(v, ts->regs + THROT_GLOBAL_CFG);
  1680. v = readl(ts->clk_regs + CAR_SUPER_CCLKG_DIVIDER);
  1681. v = REG_SET_MASK(v, CDIVG_USE_THERM_CONTROLS_MASK, 1);
  1682. writel(v, ts->clk_regs + CAR_SUPER_CCLKG_DIVIDER);
  1683. }
  1684. /* initialize stats collection */
  1685. v = STATS_CTL_CLR_DN | STATS_CTL_EN_DN |
  1686. STATS_CTL_CLR_UP | STATS_CTL_EN_UP;
  1687. writel(v, ts->regs + THERMCTL_STATS_CTL);
  1688. }
  1689. static int soctherm_interrupts_init(struct platform_device *pdev,
  1690. struct tegra_soctherm *tegra)
  1691. {
  1692. struct device_node *np = pdev->dev.of_node;
  1693. int ret;
  1694. ret = soctherm_oc_int_init(np, TEGRA_SOC_OC_IRQ_MAX);
  1695. if (ret < 0) {
  1696. dev_err(&pdev->dev, "soctherm_oc_int_init failed\n");
  1697. return ret;
  1698. }
  1699. tegra->thermal_irq = platform_get_irq(pdev, 0);
  1700. if (tegra->thermal_irq < 0) {
  1701. dev_dbg(&pdev->dev, "get 'thermal_irq' failed.\n");
  1702. return 0;
  1703. }
  1704. tegra->edp_irq = platform_get_irq(pdev, 1);
  1705. if (tegra->edp_irq < 0) {
  1706. dev_dbg(&pdev->dev, "get 'edp_irq' failed.\n");
  1707. return 0;
  1708. }
  1709. ret = devm_request_threaded_irq(&pdev->dev,
  1710. tegra->thermal_irq,
  1711. soctherm_thermal_isr,
  1712. soctherm_thermal_isr_thread,
  1713. IRQF_ONESHOT,
  1714. dev_name(&pdev->dev),
  1715. tegra);
  1716. if (ret < 0) {
  1717. dev_err(&pdev->dev, "request_irq 'thermal_irq' failed.\n");
  1718. return ret;
  1719. }
  1720. ret = devm_request_threaded_irq(&pdev->dev,
  1721. tegra->edp_irq,
  1722. soctherm_edp_isr,
  1723. soctherm_edp_isr_thread,
  1724. IRQF_ONESHOT,
  1725. "soctherm_edp",
  1726. tegra);
  1727. if (ret < 0) {
  1728. dev_err(&pdev->dev, "request_irq 'edp_irq' failed.\n");
  1729. return ret;
  1730. }
  1731. return 0;
  1732. }
  1733. static void soctherm_init(struct platform_device *pdev)
  1734. {
  1735. struct tegra_soctherm *tegra = platform_get_drvdata(pdev);
  1736. const struct tegra_tsensor_group **ttgs = tegra->soc->ttgs;
  1737. int i;
  1738. u32 pdiv, hotspot;
  1739. /* Initialize raw sensors */
  1740. for (i = 0; i < tegra->soc->num_tsensors; ++i)
  1741. enable_tsensor(tegra, i);
  1742. /* program pdiv and hotspot offsets per THERM */
  1743. pdiv = readl(tegra->regs + SENSOR_PDIV);
  1744. hotspot = readl(tegra->regs + SENSOR_HOTSPOT_OFF);
  1745. for (i = 0; i < tegra->soc->num_ttgs; ++i) {
  1746. pdiv = REG_SET_MASK(pdiv, ttgs[i]->pdiv_mask,
  1747. ttgs[i]->pdiv);
  1748. /* hotspot offset from PLLX, doesn't need to configure PLLX */
  1749. if (ttgs[i]->id == TEGRA124_SOCTHERM_SENSOR_PLLX)
  1750. continue;
  1751. hotspot = REG_SET_MASK(hotspot,
  1752. ttgs[i]->pllx_hotspot_mask,
  1753. ttgs[i]->pllx_hotspot_diff);
  1754. }
  1755. writel(pdiv, tegra->regs + SENSOR_PDIV);
  1756. writel(hotspot, tegra->regs + SENSOR_HOTSPOT_OFF);
  1757. /* Configure hw throttle */
  1758. tegra_soctherm_throttle(&pdev->dev);
  1759. }
  1760. static const struct of_device_id tegra_soctherm_of_match[] = {
  1761. #ifdef CONFIG_ARCH_TEGRA_124_SOC
  1762. {
  1763. .compatible = "nvidia,tegra124-soctherm",
  1764. .data = &tegra124_soctherm,
  1765. },
  1766. #endif
  1767. #ifdef CONFIG_ARCH_TEGRA_132_SOC
  1768. {
  1769. .compatible = "nvidia,tegra132-soctherm",
  1770. .data = &tegra132_soctherm,
  1771. },
  1772. #endif
  1773. #ifdef CONFIG_ARCH_TEGRA_210_SOC
  1774. {
  1775. .compatible = "nvidia,tegra210-soctherm",
  1776. .data = &tegra210_soctherm,
  1777. },
  1778. #endif
  1779. { },
  1780. };
  1781. MODULE_DEVICE_TABLE(of, tegra_soctherm_of_match);
  1782. static int tegra_soctherm_probe(struct platform_device *pdev)
  1783. {
  1784. const struct of_device_id *match;
  1785. struct tegra_soctherm *tegra;
  1786. struct thermal_zone_device *z;
  1787. struct tsensor_shared_calib shared_calib;
  1788. struct resource *res;
  1789. struct tegra_soctherm_soc *soc;
  1790. unsigned int i;
  1791. int err;
  1792. match = of_match_node(tegra_soctherm_of_match, pdev->dev.of_node);
  1793. if (!match)
  1794. return -ENODEV;
  1795. soc = (struct tegra_soctherm_soc *)match->data;
  1796. if (soc->num_ttgs > TEGRA124_SOCTHERM_SENSOR_NUM)
  1797. return -EINVAL;
  1798. tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
  1799. if (!tegra)
  1800. return -ENOMEM;
  1801. mutex_init(&tegra->thermctl_lock);
  1802. dev_set_drvdata(&pdev->dev, tegra);
  1803. tegra->soc = soc;
  1804. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  1805. "soctherm-reg");
  1806. tegra->regs = devm_ioremap_resource(&pdev->dev, res);
  1807. if (IS_ERR(tegra->regs)) {
  1808. dev_err(&pdev->dev, "can't get soctherm registers");
  1809. return PTR_ERR(tegra->regs);
  1810. }
  1811. if (!tegra->soc->use_ccroc) {
  1812. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  1813. "car-reg");
  1814. tegra->clk_regs = devm_ioremap_resource(&pdev->dev, res);
  1815. if (IS_ERR(tegra->clk_regs)) {
  1816. dev_err(&pdev->dev, "can't get car clk registers");
  1817. return PTR_ERR(tegra->clk_regs);
  1818. }
  1819. } else {
  1820. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  1821. "ccroc-reg");
  1822. tegra->ccroc_regs = devm_ioremap_resource(&pdev->dev, res);
  1823. if (IS_ERR(tegra->ccroc_regs)) {
  1824. dev_err(&pdev->dev, "can't get ccroc registers");
  1825. return PTR_ERR(tegra->ccroc_regs);
  1826. }
  1827. }
  1828. tegra->reset = devm_reset_control_get(&pdev->dev, "soctherm");
  1829. if (IS_ERR(tegra->reset)) {
  1830. dev_err(&pdev->dev, "can't get soctherm reset\n");
  1831. return PTR_ERR(tegra->reset);
  1832. }
  1833. tegra->clock_tsensor = devm_clk_get(&pdev->dev, "tsensor");
  1834. if (IS_ERR(tegra->clock_tsensor)) {
  1835. dev_err(&pdev->dev, "can't get tsensor clock\n");
  1836. return PTR_ERR(tegra->clock_tsensor);
  1837. }
  1838. tegra->clock_soctherm = devm_clk_get(&pdev->dev, "soctherm");
  1839. if (IS_ERR(tegra->clock_soctherm)) {
  1840. dev_err(&pdev->dev, "can't get soctherm clock\n");
  1841. return PTR_ERR(tegra->clock_soctherm);
  1842. }
  1843. tegra->calib = devm_kcalloc(&pdev->dev,
  1844. soc->num_tsensors, sizeof(u32),
  1845. GFP_KERNEL);
  1846. if (!tegra->calib)
  1847. return -ENOMEM;
  1848. /* calculate shared calibration data */
  1849. err = tegra_calc_shared_calib(soc->tfuse, &shared_calib);
  1850. if (err)
  1851. return err;
  1852. /* calculate tsensor calibaration data */
  1853. for (i = 0; i < soc->num_tsensors; ++i) {
  1854. err = tegra_calc_tsensor_calib(&soc->tsensors[i],
  1855. &shared_calib,
  1856. &tegra->calib[i]);
  1857. if (err)
  1858. return err;
  1859. }
  1860. tegra->thermctl_tzs = devm_kcalloc(&pdev->dev,
  1861. soc->num_ttgs, sizeof(z),
  1862. GFP_KERNEL);
  1863. if (!tegra->thermctl_tzs)
  1864. return -ENOMEM;
  1865. err = soctherm_clk_enable(pdev, true);
  1866. if (err)
  1867. return err;
  1868. soctherm_thermtrips_parse(pdev);
  1869. soctherm_init_hw_throt_cdev(pdev);
  1870. soctherm_init(pdev);
  1871. for (i = 0; i < soc->num_ttgs; ++i) {
  1872. struct tegra_thermctl_zone *zone =
  1873. devm_kzalloc(&pdev->dev, sizeof(*zone), GFP_KERNEL);
  1874. if (!zone) {
  1875. err = -ENOMEM;
  1876. goto disable_clocks;
  1877. }
  1878. zone->reg = tegra->regs + soc->ttgs[i]->sensor_temp_offset;
  1879. zone->dev = &pdev->dev;
  1880. zone->sg = soc->ttgs[i];
  1881. zone->ts = tegra;
  1882. z = devm_thermal_zone_of_sensor_register(&pdev->dev,
  1883. soc->ttgs[i]->id, zone,
  1884. &tegra_of_thermal_ops);
  1885. if (IS_ERR(z)) {
  1886. err = PTR_ERR(z);
  1887. dev_err(&pdev->dev, "failed to register sensor: %d\n",
  1888. err);
  1889. goto disable_clocks;
  1890. }
  1891. zone->tz = z;
  1892. tegra->thermctl_tzs[soc->ttgs[i]->id] = z;
  1893. /* Configure hw trip points */
  1894. err = tegra_soctherm_set_hwtrips(&pdev->dev, soc->ttgs[i], z);
  1895. if (err)
  1896. goto disable_clocks;
  1897. }
  1898. err = soctherm_interrupts_init(pdev, tegra);
  1899. soctherm_debug_init(pdev);
  1900. return 0;
  1901. disable_clocks:
  1902. soctherm_clk_enable(pdev, false);
  1903. return err;
  1904. }
  1905. static int tegra_soctherm_remove(struct platform_device *pdev)
  1906. {
  1907. struct tegra_soctherm *tegra = platform_get_drvdata(pdev);
  1908. debugfs_remove_recursive(tegra->debugfs_dir);
  1909. soctherm_clk_enable(pdev, false);
  1910. return 0;
  1911. }
  1912. static int __maybe_unused soctherm_suspend(struct device *dev)
  1913. {
  1914. struct platform_device *pdev = to_platform_device(dev);
  1915. soctherm_clk_enable(pdev, false);
  1916. return 0;
  1917. }
  1918. static int __maybe_unused soctherm_resume(struct device *dev)
  1919. {
  1920. struct platform_device *pdev = to_platform_device(dev);
  1921. struct tegra_soctherm *tegra = platform_get_drvdata(pdev);
  1922. struct tegra_soctherm_soc *soc = tegra->soc;
  1923. int err, i;
  1924. err = soctherm_clk_enable(pdev, true);
  1925. if (err) {
  1926. dev_err(&pdev->dev,
  1927. "Resume failed: enable clocks failed\n");
  1928. return err;
  1929. }
  1930. soctherm_init(pdev);
  1931. for (i = 0; i < soc->num_ttgs; ++i) {
  1932. struct thermal_zone_device *tz;
  1933. tz = tegra->thermctl_tzs[soc->ttgs[i]->id];
  1934. err = tegra_soctherm_set_hwtrips(dev, soc->ttgs[i], tz);
  1935. if (err) {
  1936. dev_err(&pdev->dev,
  1937. "Resume failed: set hwtrips failed\n");
  1938. return err;
  1939. }
  1940. }
  1941. return 0;
  1942. }
  1943. static SIMPLE_DEV_PM_OPS(tegra_soctherm_pm, soctherm_suspend, soctherm_resume);
  1944. static struct platform_driver tegra_soctherm_driver = {
  1945. .probe = tegra_soctherm_probe,
  1946. .remove = tegra_soctherm_remove,
  1947. .driver = {
  1948. .name = "tegra_soctherm",
  1949. .pm = &tegra_soctherm_pm,
  1950. .of_match_table = tegra_soctherm_of_match,
  1951. },
  1952. };
  1953. module_platform_driver(tegra_soctherm_driver);
  1954. MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
  1955. MODULE_DESCRIPTION("NVIDIA Tegra SOCTHERM thermal management driver");
  1956. MODULE_LICENSE("GPL v2");