rockchip_thermal.c 38 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2014-2016, Fuzhou Rockchip Electronics Co., Ltd
  4. * Caesar Wang <wxt@rock-chips.com>
  5. */
  6. #include <linux/clk.h>
  7. #include <linux/delay.h>
  8. #include <linux/interrupt.h>
  9. #include <linux/io.h>
  10. #include <linux/module.h>
  11. #include <linux/of.h>
  12. #include <linux/of_address.h>
  13. #include <linux/of_irq.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/regmap.h>
  16. #include <linux/reset.h>
  17. #include <linux/thermal.h>
  18. #include <linux/mfd/syscon.h>
  19. #include <linux/pinctrl/consumer.h>
  20. /*
  21. * If the temperature over a period of time High,
  22. * the resulting TSHUT gave CRU module,let it reset the entire chip,
  23. * or via GPIO give PMIC.
  24. */
  25. enum tshut_mode {
  26. TSHUT_MODE_CRU = 0,
  27. TSHUT_MODE_GPIO,
  28. };
  29. /*
  30. * The system Temperature Sensors tshut(tshut) polarity
  31. * the bit 8 is tshut polarity.
  32. * 0: low active, 1: high active
  33. */
  34. enum tshut_polarity {
  35. TSHUT_LOW_ACTIVE = 0,
  36. TSHUT_HIGH_ACTIVE,
  37. };
  38. /*
  39. * The system has two Temperature Sensors.
  40. * sensor0 is for CPU, and sensor1 is for GPU.
  41. */
  42. enum sensor_id {
  43. SENSOR_CPU = 0,
  44. SENSOR_GPU,
  45. };
  46. /*
  47. * The conversion table has the adc value and temperature.
  48. * ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table)
  49. * ADC_INCREMENT: the adc value is incremental.(e.g. rk3368_code_table)
  50. */
  51. enum adc_sort_mode {
  52. ADC_DECREMENT = 0,
  53. ADC_INCREMENT,
  54. };
  55. #include "thermal_hwmon.h"
  56. /**
  57. * The max sensors is two in rockchip SoCs.
  58. * Two sensors: CPU and GPU sensor.
  59. */
  60. #define SOC_MAX_SENSORS 2
  61. /**
  62. * struct chip_tsadc_table - hold information about chip-specific differences
  63. * @id: conversion table
  64. * @length: size of conversion table
  65. * @data_mask: mask to apply on data inputs
  66. * @mode: sort mode of this adc variant (incrementing or decrementing)
  67. */
  68. struct chip_tsadc_table {
  69. const struct tsadc_table *id;
  70. unsigned int length;
  71. u32 data_mask;
  72. enum adc_sort_mode mode;
  73. };
  74. /**
  75. * struct rockchip_tsadc_chip - hold the private data of tsadc chip
  76. * @chn_id: array of sensor ids of chip corresponding to the channel
  77. * @chn_num: the channel number of tsadc chip
  78. * @tshut_temp: the hardware-controlled shutdown temperature value
  79. * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
  80. * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
  81. * @initialize: SoC special initialize tsadc controller method
  82. * @irq_ack: clear the interrupt
  83. * @control: enable/disable method for the tsadc controller
  84. * @get_temp: get the temperature
  85. * @set_alarm_temp: set the high temperature interrupt
  86. * @set_tshut_temp: set the hardware-controlled shutdown temperature
  87. * @set_tshut_mode: set the hardware-controlled shutdown mode
  88. * @table: the chip-specific conversion table
  89. */
  90. struct rockchip_tsadc_chip {
  91. /* The sensor id of chip correspond to the ADC channel */
  92. int chn_id[SOC_MAX_SENSORS];
  93. int chn_num;
  94. /* The hardware-controlled tshut property */
  95. int tshut_temp;
  96. enum tshut_mode tshut_mode;
  97. enum tshut_polarity tshut_polarity;
  98. /* Chip-wide methods */
  99. void (*initialize)(struct regmap *grf,
  100. void __iomem *reg, enum tshut_polarity p);
  101. void (*irq_ack)(void __iomem *reg);
  102. void (*control)(void __iomem *reg, bool on);
  103. /* Per-sensor methods */
  104. int (*get_temp)(const struct chip_tsadc_table *table,
  105. int chn, void __iomem *reg, int *temp);
  106. int (*set_alarm_temp)(const struct chip_tsadc_table *table,
  107. int chn, void __iomem *reg, int temp);
  108. int (*set_tshut_temp)(const struct chip_tsadc_table *table,
  109. int chn, void __iomem *reg, int temp);
  110. void (*set_tshut_mode)(int chn, void __iomem *reg, enum tshut_mode m);
  111. /* Per-table methods */
  112. struct chip_tsadc_table table;
  113. };
  114. /**
  115. * struct rockchip_thermal_sensor - hold the information of thermal sensor
  116. * @thermal: pointer to the platform/configuration data
  117. * @tzd: pointer to a thermal zone
  118. * @id: identifier of the thermal sensor
  119. */
  120. struct rockchip_thermal_sensor {
  121. struct rockchip_thermal_data *thermal;
  122. struct thermal_zone_device *tzd;
  123. int id;
  124. };
  125. /**
  126. * struct rockchip_thermal_data - hold the private data of thermal driver
  127. * @chip: pointer to the platform/configuration data
  128. * @pdev: platform device of thermal
  129. * @reset: the reset controller of tsadc
  130. * @sensors: array of thermal sensors
  131. * @clk: the controller clock is divided by the exteral 24MHz
  132. * @pclk: the advanced peripherals bus clock
  133. * @grf: the general register file will be used to do static set by software
  134. * @regs: the base address of tsadc controller
  135. * @tshut_temp: the hardware-controlled shutdown temperature value
  136. * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
  137. * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
  138. */
  139. struct rockchip_thermal_data {
  140. const struct rockchip_tsadc_chip *chip;
  141. struct platform_device *pdev;
  142. struct reset_control *reset;
  143. struct rockchip_thermal_sensor sensors[SOC_MAX_SENSORS];
  144. struct clk *clk;
  145. struct clk *pclk;
  146. struct regmap *grf;
  147. void __iomem *regs;
  148. int tshut_temp;
  149. enum tshut_mode tshut_mode;
  150. enum tshut_polarity tshut_polarity;
  151. };
  152. /**
  153. * TSADC Sensor Register description:
  154. *
  155. * TSADCV2_* are used for RK3288 SoCs, the other chips can reuse it.
  156. * TSADCV3_* are used for newer SoCs than RK3288. (e.g: RK3228, RK3399)
  157. *
  158. */
  159. #define TSADCV2_USER_CON 0x00
  160. #define TSADCV2_AUTO_CON 0x04
  161. #define TSADCV2_INT_EN 0x08
  162. #define TSADCV2_INT_PD 0x0c
  163. #define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04)
  164. #define TSADCV2_COMP_INT(chn) (0x30 + (chn) * 0x04)
  165. #define TSADCV2_COMP_SHUT(chn) (0x40 + (chn) * 0x04)
  166. #define TSADCV2_HIGHT_INT_DEBOUNCE 0x60
  167. #define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64
  168. #define TSADCV2_AUTO_PERIOD 0x68
  169. #define TSADCV2_AUTO_PERIOD_HT 0x6c
  170. #define TSADCV2_AUTO_EN BIT(0)
  171. #define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn))
  172. #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8)
  173. #define TSADCV3_AUTO_Q_SEL_EN BIT(1)
  174. #define TSADCV2_INT_SRC_EN(chn) BIT(chn)
  175. #define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn))
  176. #define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn))
  177. #define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8)
  178. #define TSADCV3_INT_PD_CLEAR_MASK ~BIT(16)
  179. #define TSADCV2_DATA_MASK 0xfff
  180. #define TSADCV3_DATA_MASK 0x3ff
  181. #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4
  182. #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4
  183. #define TSADCV2_AUTO_PERIOD_TIME 250 /* 250ms */
  184. #define TSADCV2_AUTO_PERIOD_HT_TIME 50 /* 50ms */
  185. #define TSADCV3_AUTO_PERIOD_TIME 1875 /* 2.5ms */
  186. #define TSADCV3_AUTO_PERIOD_HT_TIME 1875 /* 2.5ms */
  187. #define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */
  188. #define GRF_SARADC_TESTBIT 0x0e644
  189. #define GRF_TSADC_TESTBIT_L 0x0e648
  190. #define GRF_TSADC_TESTBIT_H 0x0e64c
  191. #define PX30_GRF_SOC_CON2 0x0408
  192. #define GRF_SARADC_TESTBIT_ON (0x10001 << 2)
  193. #define GRF_TSADC_TESTBIT_H_ON (0x10001 << 2)
  194. #define GRF_TSADC_VCM_EN_L (0x10001 << 7)
  195. #define GRF_TSADC_VCM_EN_H (0x10001 << 7)
  196. #define GRF_CON_TSADC_CH_INV (0x10001 << 1)
  197. /**
  198. * struct tsadc_table - code to temperature conversion table
  199. * @code: the value of adc channel
  200. * @temp: the temperature
  201. * Note:
  202. * code to temperature mapping of the temperature sensor is a piece wise linear
  203. * curve.Any temperature, code faling between to 2 give temperatures can be
  204. * linearly interpolated.
  205. * Code to Temperature mapping should be updated based on manufacturer results.
  206. */
  207. struct tsadc_table {
  208. u32 code;
  209. int temp;
  210. };
  211. static const struct tsadc_table rv1108_table[] = {
  212. {0, -40000},
  213. {374, -40000},
  214. {382, -35000},
  215. {389, -30000},
  216. {397, -25000},
  217. {405, -20000},
  218. {413, -15000},
  219. {421, -10000},
  220. {429, -5000},
  221. {436, 0},
  222. {444, 5000},
  223. {452, 10000},
  224. {460, 15000},
  225. {468, 20000},
  226. {476, 25000},
  227. {483, 30000},
  228. {491, 35000},
  229. {499, 40000},
  230. {507, 45000},
  231. {515, 50000},
  232. {523, 55000},
  233. {531, 60000},
  234. {539, 65000},
  235. {547, 70000},
  236. {555, 75000},
  237. {562, 80000},
  238. {570, 85000},
  239. {578, 90000},
  240. {586, 95000},
  241. {594, 100000},
  242. {602, 105000},
  243. {610, 110000},
  244. {618, 115000},
  245. {626, 120000},
  246. {634, 125000},
  247. {TSADCV2_DATA_MASK, 125000},
  248. };
  249. static const struct tsadc_table rk3228_code_table[] = {
  250. {0, -40000},
  251. {588, -40000},
  252. {593, -35000},
  253. {598, -30000},
  254. {603, -25000},
  255. {608, -20000},
  256. {613, -15000},
  257. {618, -10000},
  258. {623, -5000},
  259. {629, 0},
  260. {634, 5000},
  261. {639, 10000},
  262. {644, 15000},
  263. {649, 20000},
  264. {654, 25000},
  265. {660, 30000},
  266. {665, 35000},
  267. {670, 40000},
  268. {675, 45000},
  269. {681, 50000},
  270. {686, 55000},
  271. {691, 60000},
  272. {696, 65000},
  273. {702, 70000},
  274. {707, 75000},
  275. {712, 80000},
  276. {717, 85000},
  277. {723, 90000},
  278. {728, 95000},
  279. {733, 100000},
  280. {738, 105000},
  281. {744, 110000},
  282. {749, 115000},
  283. {754, 120000},
  284. {760, 125000},
  285. {TSADCV2_DATA_MASK, 125000},
  286. };
  287. static const struct tsadc_table rk3288_code_table[] = {
  288. {TSADCV2_DATA_MASK, -40000},
  289. {3800, -40000},
  290. {3792, -35000},
  291. {3783, -30000},
  292. {3774, -25000},
  293. {3765, -20000},
  294. {3756, -15000},
  295. {3747, -10000},
  296. {3737, -5000},
  297. {3728, 0},
  298. {3718, 5000},
  299. {3708, 10000},
  300. {3698, 15000},
  301. {3688, 20000},
  302. {3678, 25000},
  303. {3667, 30000},
  304. {3656, 35000},
  305. {3645, 40000},
  306. {3634, 45000},
  307. {3623, 50000},
  308. {3611, 55000},
  309. {3600, 60000},
  310. {3588, 65000},
  311. {3575, 70000},
  312. {3563, 75000},
  313. {3550, 80000},
  314. {3537, 85000},
  315. {3524, 90000},
  316. {3510, 95000},
  317. {3496, 100000},
  318. {3482, 105000},
  319. {3467, 110000},
  320. {3452, 115000},
  321. {3437, 120000},
  322. {3421, 125000},
  323. {0, 125000},
  324. };
  325. static const struct tsadc_table rk3328_code_table[] = {
  326. {0, -40000},
  327. {296, -40000},
  328. {304, -35000},
  329. {313, -30000},
  330. {331, -20000},
  331. {340, -15000},
  332. {349, -10000},
  333. {359, -5000},
  334. {368, 0},
  335. {378, 5000},
  336. {388, 10000},
  337. {398, 15000},
  338. {408, 20000},
  339. {418, 25000},
  340. {429, 30000},
  341. {440, 35000},
  342. {451, 40000},
  343. {462, 45000},
  344. {473, 50000},
  345. {485, 55000},
  346. {496, 60000},
  347. {508, 65000},
  348. {521, 70000},
  349. {533, 75000},
  350. {546, 80000},
  351. {559, 85000},
  352. {572, 90000},
  353. {586, 95000},
  354. {600, 100000},
  355. {614, 105000},
  356. {629, 110000},
  357. {644, 115000},
  358. {659, 120000},
  359. {675, 125000},
  360. {TSADCV2_DATA_MASK, 125000},
  361. };
  362. static const struct tsadc_table rk3368_code_table[] = {
  363. {0, -40000},
  364. {106, -40000},
  365. {108, -35000},
  366. {110, -30000},
  367. {112, -25000},
  368. {114, -20000},
  369. {116, -15000},
  370. {118, -10000},
  371. {120, -5000},
  372. {122, 0},
  373. {124, 5000},
  374. {126, 10000},
  375. {128, 15000},
  376. {130, 20000},
  377. {132, 25000},
  378. {134, 30000},
  379. {136, 35000},
  380. {138, 40000},
  381. {140, 45000},
  382. {142, 50000},
  383. {144, 55000},
  384. {146, 60000},
  385. {148, 65000},
  386. {150, 70000},
  387. {152, 75000},
  388. {154, 80000},
  389. {156, 85000},
  390. {158, 90000},
  391. {160, 95000},
  392. {162, 100000},
  393. {163, 105000},
  394. {165, 110000},
  395. {167, 115000},
  396. {169, 120000},
  397. {171, 125000},
  398. {TSADCV3_DATA_MASK, 125000},
  399. };
  400. static const struct tsadc_table rk3399_code_table[] = {
  401. {0, -40000},
  402. {402, -40000},
  403. {410, -35000},
  404. {419, -30000},
  405. {427, -25000},
  406. {436, -20000},
  407. {444, -15000},
  408. {453, -10000},
  409. {461, -5000},
  410. {470, 0},
  411. {478, 5000},
  412. {487, 10000},
  413. {496, 15000},
  414. {504, 20000},
  415. {513, 25000},
  416. {521, 30000},
  417. {530, 35000},
  418. {538, 40000},
  419. {547, 45000},
  420. {555, 50000},
  421. {564, 55000},
  422. {573, 60000},
  423. {581, 65000},
  424. {590, 70000},
  425. {599, 75000},
  426. {607, 80000},
  427. {616, 85000},
  428. {624, 90000},
  429. {633, 95000},
  430. {642, 100000},
  431. {650, 105000},
  432. {659, 110000},
  433. {668, 115000},
  434. {677, 120000},
  435. {685, 125000},
  436. {TSADCV3_DATA_MASK, 125000},
  437. };
  438. static u32 rk_tsadcv2_temp_to_code(const struct chip_tsadc_table *table,
  439. int temp)
  440. {
  441. int high, low, mid;
  442. unsigned long num;
  443. unsigned int denom;
  444. u32 error = table->data_mask;
  445. low = 0;
  446. high = (table->length - 1) - 1; /* ignore the last check for table */
  447. mid = (high + low) / 2;
  448. /* Return mask code data when the temp is over table range */
  449. if (temp < table->id[low].temp || temp > table->id[high].temp)
  450. goto exit;
  451. while (low <= high) {
  452. if (temp == table->id[mid].temp)
  453. return table->id[mid].code;
  454. else if (temp < table->id[mid].temp)
  455. high = mid - 1;
  456. else
  457. low = mid + 1;
  458. mid = (low + high) / 2;
  459. }
  460. /*
  461. * The conversion code granularity provided by the table. Let's
  462. * assume that the relationship between temperature and
  463. * analog value between 2 table entries is linear and interpolate
  464. * to produce less granular result.
  465. */
  466. num = abs(table->id[mid + 1].code - table->id[mid].code);
  467. num *= temp - table->id[mid].temp;
  468. denom = table->id[mid + 1].temp - table->id[mid].temp;
  469. switch (table->mode) {
  470. case ADC_DECREMENT:
  471. return table->id[mid].code - (num / denom);
  472. case ADC_INCREMENT:
  473. return table->id[mid].code + (num / denom);
  474. default:
  475. pr_err("%s: unknown table mode: %d\n", __func__, table->mode);
  476. return error;
  477. }
  478. exit:
  479. pr_err("%s: invalid temperature, temp=%d error=%d\n",
  480. __func__, temp, error);
  481. return error;
  482. }
  483. static int rk_tsadcv2_code_to_temp(const struct chip_tsadc_table *table,
  484. u32 code, int *temp)
  485. {
  486. unsigned int low = 1;
  487. unsigned int high = table->length - 1;
  488. unsigned int mid = (low + high) / 2;
  489. unsigned int num;
  490. unsigned long denom;
  491. WARN_ON(table->length < 2);
  492. switch (table->mode) {
  493. case ADC_DECREMENT:
  494. code &= table->data_mask;
  495. if (code <= table->id[high].code)
  496. return -EAGAIN; /* Incorrect reading */
  497. while (low <= high) {
  498. if (code >= table->id[mid].code &&
  499. code < table->id[mid - 1].code)
  500. break;
  501. else if (code < table->id[mid].code)
  502. low = mid + 1;
  503. else
  504. high = mid - 1;
  505. mid = (low + high) / 2;
  506. }
  507. break;
  508. case ADC_INCREMENT:
  509. code &= table->data_mask;
  510. if (code < table->id[low].code)
  511. return -EAGAIN; /* Incorrect reading */
  512. while (low <= high) {
  513. if (code <= table->id[mid].code &&
  514. code > table->id[mid - 1].code)
  515. break;
  516. else if (code > table->id[mid].code)
  517. low = mid + 1;
  518. else
  519. high = mid - 1;
  520. mid = (low + high) / 2;
  521. }
  522. break;
  523. default:
  524. pr_err("%s: unknown table mode: %d\n", __func__, table->mode);
  525. return -EINVAL;
  526. }
  527. /*
  528. * The 5C granularity provided by the table is too much. Let's
  529. * assume that the relationship between sensor readings and
  530. * temperature between 2 table entries is linear and interpolate
  531. * to produce less granular result.
  532. */
  533. num = table->id[mid].temp - table->id[mid - 1].temp;
  534. num *= abs(table->id[mid - 1].code - code);
  535. denom = abs(table->id[mid - 1].code - table->id[mid].code);
  536. *temp = table->id[mid - 1].temp + (num / denom);
  537. return 0;
  538. }
  539. /**
  540. * rk_tsadcv2_initialize - initialize TASDC Controller.
  541. * @grf: the general register file will be used to do static set by software
  542. * @regs: the base address of tsadc controller
  543. * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
  544. *
  545. * (1) Set TSADC_V2_AUTO_PERIOD:
  546. * Configure the interleave between every two accessing of
  547. * TSADC in normal operation.
  548. *
  549. * (2) Set TSADCV2_AUTO_PERIOD_HT:
  550. * Configure the interleave between every two accessing of
  551. * TSADC after the temperature is higher than COM_SHUT or COM_INT.
  552. *
  553. * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE:
  554. * If the temperature is higher than COMP_INT or COMP_SHUT for
  555. * "debounce" times, TSADC controller will generate interrupt or TSHUT.
  556. */
  557. static void rk_tsadcv2_initialize(struct regmap *grf, void __iomem *regs,
  558. enum tshut_polarity tshut_polarity)
  559. {
  560. if (tshut_polarity == TSHUT_HIGH_ACTIVE)
  561. writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
  562. regs + TSADCV2_AUTO_CON);
  563. else
  564. writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
  565. regs + TSADCV2_AUTO_CON);
  566. writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD);
  567. writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
  568. regs + TSADCV2_HIGHT_INT_DEBOUNCE);
  569. writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME,
  570. regs + TSADCV2_AUTO_PERIOD_HT);
  571. writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
  572. regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
  573. }
  574. /**
  575. * rk_tsadcv3_initialize - initialize TASDC Controller.
  576. * @grf: the general register file will be used to do static set by software
  577. * @regs: the base address of tsadc controller
  578. * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
  579. *
  580. * (1) The tsadc control power sequence.
  581. *
  582. * (2) Set TSADC_V2_AUTO_PERIOD:
  583. * Configure the interleave between every two accessing of
  584. * TSADC in normal operation.
  585. *
  586. * (2) Set TSADCV2_AUTO_PERIOD_HT:
  587. * Configure the interleave between every two accessing of
  588. * TSADC after the temperature is higher than COM_SHUT or COM_INT.
  589. *
  590. * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE:
  591. * If the temperature is higher than COMP_INT or COMP_SHUT for
  592. * "debounce" times, TSADC controller will generate interrupt or TSHUT.
  593. */
  594. static void rk_tsadcv3_initialize(struct regmap *grf, void __iomem *regs,
  595. enum tshut_polarity tshut_polarity)
  596. {
  597. /* The tsadc control power sequence */
  598. if (IS_ERR(grf)) {
  599. /* Set interleave value to workround ic time sync issue */
  600. writel_relaxed(TSADCV2_USER_INTER_PD_SOC, regs +
  601. TSADCV2_USER_CON);
  602. writel_relaxed(TSADCV2_AUTO_PERIOD_TIME,
  603. regs + TSADCV2_AUTO_PERIOD);
  604. writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
  605. regs + TSADCV2_HIGHT_INT_DEBOUNCE);
  606. writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME,
  607. regs + TSADCV2_AUTO_PERIOD_HT);
  608. writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
  609. regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
  610. } else {
  611. /* Enable the voltage common mode feature */
  612. regmap_write(grf, GRF_TSADC_TESTBIT_L, GRF_TSADC_VCM_EN_L);
  613. regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_VCM_EN_H);
  614. usleep_range(15, 100); /* The spec note says at least 15 us */
  615. regmap_write(grf, GRF_SARADC_TESTBIT, GRF_SARADC_TESTBIT_ON);
  616. regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_TESTBIT_H_ON);
  617. usleep_range(90, 200); /* The spec note says at least 90 us */
  618. writel_relaxed(TSADCV3_AUTO_PERIOD_TIME,
  619. regs + TSADCV2_AUTO_PERIOD);
  620. writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
  621. regs + TSADCV2_HIGHT_INT_DEBOUNCE);
  622. writel_relaxed(TSADCV3_AUTO_PERIOD_HT_TIME,
  623. regs + TSADCV2_AUTO_PERIOD_HT);
  624. writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
  625. regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
  626. }
  627. if (tshut_polarity == TSHUT_HIGH_ACTIVE)
  628. writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
  629. regs + TSADCV2_AUTO_CON);
  630. else
  631. writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
  632. regs + TSADCV2_AUTO_CON);
  633. }
  634. static void rk_tsadcv4_initialize(struct regmap *grf, void __iomem *regs,
  635. enum tshut_polarity tshut_polarity)
  636. {
  637. rk_tsadcv2_initialize(grf, regs, tshut_polarity);
  638. regmap_write(grf, PX30_GRF_SOC_CON2, GRF_CON_TSADC_CH_INV);
  639. }
  640. static void rk_tsadcv2_irq_ack(void __iomem *regs)
  641. {
  642. u32 val;
  643. val = readl_relaxed(regs + TSADCV2_INT_PD);
  644. writel_relaxed(val & TSADCV2_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
  645. }
  646. static void rk_tsadcv3_irq_ack(void __iomem *regs)
  647. {
  648. u32 val;
  649. val = readl_relaxed(regs + TSADCV2_INT_PD);
  650. writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
  651. }
  652. static void rk_tsadcv2_control(void __iomem *regs, bool enable)
  653. {
  654. u32 val;
  655. val = readl_relaxed(regs + TSADCV2_AUTO_CON);
  656. if (enable)
  657. val |= TSADCV2_AUTO_EN;
  658. else
  659. val &= ~TSADCV2_AUTO_EN;
  660. writel_relaxed(val, regs + TSADCV2_AUTO_CON);
  661. }
  662. /**
  663. * rk_tsadcv3_control - the tsadc controller is enabled or disabled.
  664. * @regs: the base address of tsadc controller
  665. * @enable: boolean flag to enable the controller
  666. *
  667. * NOTE: TSADC controller works at auto mode, and some SoCs need set the
  668. * tsadc_q_sel bit on TSADCV2_AUTO_CON[1]. The (1024 - tsadc_q) as output
  669. * adc value if setting this bit to enable.
  670. */
  671. static void rk_tsadcv3_control(void __iomem *regs, bool enable)
  672. {
  673. u32 val;
  674. val = readl_relaxed(regs + TSADCV2_AUTO_CON);
  675. if (enable)
  676. val |= TSADCV2_AUTO_EN | TSADCV3_AUTO_Q_SEL_EN;
  677. else
  678. val &= ~TSADCV2_AUTO_EN;
  679. writel_relaxed(val, regs + TSADCV2_AUTO_CON);
  680. }
  681. static int rk_tsadcv2_get_temp(const struct chip_tsadc_table *table,
  682. int chn, void __iomem *regs, int *temp)
  683. {
  684. u32 val;
  685. val = readl_relaxed(regs + TSADCV2_DATA(chn));
  686. return rk_tsadcv2_code_to_temp(table, val, temp);
  687. }
  688. static int rk_tsadcv2_alarm_temp(const struct chip_tsadc_table *table,
  689. int chn, void __iomem *regs, int temp)
  690. {
  691. u32 alarm_value;
  692. u32 int_en, int_clr;
  693. /*
  694. * In some cases, some sensors didn't need the trip points, the
  695. * set_trips will pass {-INT_MAX, INT_MAX} to trigger tsadc alarm
  696. * in the end, ignore this case and disable the high temperature
  697. * interrupt.
  698. */
  699. if (temp == INT_MAX) {
  700. int_clr = readl_relaxed(regs + TSADCV2_INT_EN);
  701. int_clr &= ~TSADCV2_INT_SRC_EN(chn);
  702. writel_relaxed(int_clr, regs + TSADCV2_INT_EN);
  703. return 0;
  704. }
  705. /* Make sure the value is valid */
  706. alarm_value = rk_tsadcv2_temp_to_code(table, temp);
  707. if (alarm_value == table->data_mask)
  708. return -ERANGE;
  709. writel_relaxed(alarm_value & table->data_mask,
  710. regs + TSADCV2_COMP_INT(chn));
  711. int_en = readl_relaxed(regs + TSADCV2_INT_EN);
  712. int_en |= TSADCV2_INT_SRC_EN(chn);
  713. writel_relaxed(int_en, regs + TSADCV2_INT_EN);
  714. return 0;
  715. }
  716. static int rk_tsadcv2_tshut_temp(const struct chip_tsadc_table *table,
  717. int chn, void __iomem *regs, int temp)
  718. {
  719. u32 tshut_value, val;
  720. /* Make sure the value is valid */
  721. tshut_value = rk_tsadcv2_temp_to_code(table, temp);
  722. if (tshut_value == table->data_mask)
  723. return -ERANGE;
  724. writel_relaxed(tshut_value, regs + TSADCV2_COMP_SHUT(chn));
  725. /* TSHUT will be valid */
  726. val = readl_relaxed(regs + TSADCV2_AUTO_CON);
  727. writel_relaxed(val | TSADCV2_AUTO_SRC_EN(chn), regs + TSADCV2_AUTO_CON);
  728. return 0;
  729. }
  730. static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs,
  731. enum tshut_mode mode)
  732. {
  733. u32 val;
  734. val = readl_relaxed(regs + TSADCV2_INT_EN);
  735. if (mode == TSHUT_MODE_GPIO) {
  736. val &= ~TSADCV2_SHUT_2CRU_SRC_EN(chn);
  737. val |= TSADCV2_SHUT_2GPIO_SRC_EN(chn);
  738. } else {
  739. val &= ~TSADCV2_SHUT_2GPIO_SRC_EN(chn);
  740. val |= TSADCV2_SHUT_2CRU_SRC_EN(chn);
  741. }
  742. writel_relaxed(val, regs + TSADCV2_INT_EN);
  743. }
  744. static const struct rockchip_tsadc_chip px30_tsadc_data = {
  745. .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
  746. .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
  747. .chn_num = 2, /* 2 channels for tsadc */
  748. .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
  749. .tshut_temp = 95000,
  750. .initialize = rk_tsadcv4_initialize,
  751. .irq_ack = rk_tsadcv3_irq_ack,
  752. .control = rk_tsadcv3_control,
  753. .get_temp = rk_tsadcv2_get_temp,
  754. .set_alarm_temp = rk_tsadcv2_alarm_temp,
  755. .set_tshut_temp = rk_tsadcv2_tshut_temp,
  756. .set_tshut_mode = rk_tsadcv2_tshut_mode,
  757. .table = {
  758. .id = rk3328_code_table,
  759. .length = ARRAY_SIZE(rk3328_code_table),
  760. .data_mask = TSADCV2_DATA_MASK,
  761. .mode = ADC_INCREMENT,
  762. },
  763. };
  764. static const struct rockchip_tsadc_chip rv1108_tsadc_data = {
  765. .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
  766. .chn_num = 1, /* one channel for tsadc */
  767. .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
  768. .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
  769. .tshut_temp = 95000,
  770. .initialize = rk_tsadcv2_initialize,
  771. .irq_ack = rk_tsadcv3_irq_ack,
  772. .control = rk_tsadcv3_control,
  773. .get_temp = rk_tsadcv2_get_temp,
  774. .set_alarm_temp = rk_tsadcv2_alarm_temp,
  775. .set_tshut_temp = rk_tsadcv2_tshut_temp,
  776. .set_tshut_mode = rk_tsadcv2_tshut_mode,
  777. .table = {
  778. .id = rv1108_table,
  779. .length = ARRAY_SIZE(rv1108_table),
  780. .data_mask = TSADCV2_DATA_MASK,
  781. .mode = ADC_INCREMENT,
  782. },
  783. };
  784. static const struct rockchip_tsadc_chip rk3228_tsadc_data = {
  785. .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
  786. .chn_num = 1, /* one channel for tsadc */
  787. .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
  788. .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
  789. .tshut_temp = 95000,
  790. .initialize = rk_tsadcv2_initialize,
  791. .irq_ack = rk_tsadcv3_irq_ack,
  792. .control = rk_tsadcv3_control,
  793. .get_temp = rk_tsadcv2_get_temp,
  794. .set_alarm_temp = rk_tsadcv2_alarm_temp,
  795. .set_tshut_temp = rk_tsadcv2_tshut_temp,
  796. .set_tshut_mode = rk_tsadcv2_tshut_mode,
  797. .table = {
  798. .id = rk3228_code_table,
  799. .length = ARRAY_SIZE(rk3228_code_table),
  800. .data_mask = TSADCV3_DATA_MASK,
  801. .mode = ADC_INCREMENT,
  802. },
  803. };
  804. static const struct rockchip_tsadc_chip rk3288_tsadc_data = {
  805. .chn_id[SENSOR_CPU] = 1, /* cpu sensor is channel 1 */
  806. .chn_id[SENSOR_GPU] = 2, /* gpu sensor is channel 2 */
  807. .chn_num = 2, /* two channels for tsadc */
  808. .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
  809. .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
  810. .tshut_temp = 95000,
  811. .initialize = rk_tsadcv2_initialize,
  812. .irq_ack = rk_tsadcv2_irq_ack,
  813. .control = rk_tsadcv2_control,
  814. .get_temp = rk_tsadcv2_get_temp,
  815. .set_alarm_temp = rk_tsadcv2_alarm_temp,
  816. .set_tshut_temp = rk_tsadcv2_tshut_temp,
  817. .set_tshut_mode = rk_tsadcv2_tshut_mode,
  818. .table = {
  819. .id = rk3288_code_table,
  820. .length = ARRAY_SIZE(rk3288_code_table),
  821. .data_mask = TSADCV2_DATA_MASK,
  822. .mode = ADC_DECREMENT,
  823. },
  824. };
  825. static const struct rockchip_tsadc_chip rk3328_tsadc_data = {
  826. .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
  827. .chn_num = 1, /* one channels for tsadc */
  828. .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
  829. .tshut_temp = 95000,
  830. .initialize = rk_tsadcv2_initialize,
  831. .irq_ack = rk_tsadcv3_irq_ack,
  832. .control = rk_tsadcv3_control,
  833. .get_temp = rk_tsadcv2_get_temp,
  834. .set_alarm_temp = rk_tsadcv2_alarm_temp,
  835. .set_tshut_temp = rk_tsadcv2_tshut_temp,
  836. .set_tshut_mode = rk_tsadcv2_tshut_mode,
  837. .table = {
  838. .id = rk3328_code_table,
  839. .length = ARRAY_SIZE(rk3328_code_table),
  840. .data_mask = TSADCV2_DATA_MASK,
  841. .mode = ADC_INCREMENT,
  842. },
  843. };
  844. static const struct rockchip_tsadc_chip rk3366_tsadc_data = {
  845. .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
  846. .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
  847. .chn_num = 2, /* two channels for tsadc */
  848. .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
  849. .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
  850. .tshut_temp = 95000,
  851. .initialize = rk_tsadcv3_initialize,
  852. .irq_ack = rk_tsadcv3_irq_ack,
  853. .control = rk_tsadcv3_control,
  854. .get_temp = rk_tsadcv2_get_temp,
  855. .set_alarm_temp = rk_tsadcv2_alarm_temp,
  856. .set_tshut_temp = rk_tsadcv2_tshut_temp,
  857. .set_tshut_mode = rk_tsadcv2_tshut_mode,
  858. .table = {
  859. .id = rk3228_code_table,
  860. .length = ARRAY_SIZE(rk3228_code_table),
  861. .data_mask = TSADCV3_DATA_MASK,
  862. .mode = ADC_INCREMENT,
  863. },
  864. };
  865. static const struct rockchip_tsadc_chip rk3368_tsadc_data = {
  866. .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
  867. .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
  868. .chn_num = 2, /* two channels for tsadc */
  869. .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
  870. .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
  871. .tshut_temp = 95000,
  872. .initialize = rk_tsadcv2_initialize,
  873. .irq_ack = rk_tsadcv2_irq_ack,
  874. .control = rk_tsadcv2_control,
  875. .get_temp = rk_tsadcv2_get_temp,
  876. .set_alarm_temp = rk_tsadcv2_alarm_temp,
  877. .set_tshut_temp = rk_tsadcv2_tshut_temp,
  878. .set_tshut_mode = rk_tsadcv2_tshut_mode,
  879. .table = {
  880. .id = rk3368_code_table,
  881. .length = ARRAY_SIZE(rk3368_code_table),
  882. .data_mask = TSADCV3_DATA_MASK,
  883. .mode = ADC_INCREMENT,
  884. },
  885. };
  886. static const struct rockchip_tsadc_chip rk3399_tsadc_data = {
  887. .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
  888. .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
  889. .chn_num = 2, /* two channels for tsadc */
  890. .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
  891. .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
  892. .tshut_temp = 95000,
  893. .initialize = rk_tsadcv3_initialize,
  894. .irq_ack = rk_tsadcv3_irq_ack,
  895. .control = rk_tsadcv3_control,
  896. .get_temp = rk_tsadcv2_get_temp,
  897. .set_alarm_temp = rk_tsadcv2_alarm_temp,
  898. .set_tshut_temp = rk_tsadcv2_tshut_temp,
  899. .set_tshut_mode = rk_tsadcv2_tshut_mode,
  900. .table = {
  901. .id = rk3399_code_table,
  902. .length = ARRAY_SIZE(rk3399_code_table),
  903. .data_mask = TSADCV3_DATA_MASK,
  904. .mode = ADC_INCREMENT,
  905. },
  906. };
  907. static const struct of_device_id of_rockchip_thermal_match[] = {
  908. { .compatible = "rockchip,px30-tsadc",
  909. .data = (void *)&px30_tsadc_data,
  910. },
  911. {
  912. .compatible = "rockchip,rv1108-tsadc",
  913. .data = (void *)&rv1108_tsadc_data,
  914. },
  915. {
  916. .compatible = "rockchip,rk3228-tsadc",
  917. .data = (void *)&rk3228_tsadc_data,
  918. },
  919. {
  920. .compatible = "rockchip,rk3288-tsadc",
  921. .data = (void *)&rk3288_tsadc_data,
  922. },
  923. {
  924. .compatible = "rockchip,rk3328-tsadc",
  925. .data = (void *)&rk3328_tsadc_data,
  926. },
  927. {
  928. .compatible = "rockchip,rk3366-tsadc",
  929. .data = (void *)&rk3366_tsadc_data,
  930. },
  931. {
  932. .compatible = "rockchip,rk3368-tsadc",
  933. .data = (void *)&rk3368_tsadc_data,
  934. },
  935. {
  936. .compatible = "rockchip,rk3399-tsadc",
  937. .data = (void *)&rk3399_tsadc_data,
  938. },
  939. { /* end */ },
  940. };
  941. MODULE_DEVICE_TABLE(of, of_rockchip_thermal_match);
  942. static void
  943. rockchip_thermal_toggle_sensor(struct rockchip_thermal_sensor *sensor, bool on)
  944. {
  945. struct thermal_zone_device *tzd = sensor->tzd;
  946. if (on)
  947. thermal_zone_device_enable(tzd);
  948. else
  949. thermal_zone_device_disable(tzd);
  950. }
  951. static irqreturn_t rockchip_thermal_alarm_irq_thread(int irq, void *dev)
  952. {
  953. struct rockchip_thermal_data *thermal = dev;
  954. int i;
  955. dev_dbg(&thermal->pdev->dev, "thermal alarm\n");
  956. thermal->chip->irq_ack(thermal->regs);
  957. for (i = 0; i < thermal->chip->chn_num; i++)
  958. thermal_zone_device_update(thermal->sensors[i].tzd,
  959. THERMAL_EVENT_UNSPECIFIED);
  960. return IRQ_HANDLED;
  961. }
  962. static int rockchip_thermal_set_trips(void *_sensor, int low, int high)
  963. {
  964. struct rockchip_thermal_sensor *sensor = _sensor;
  965. struct rockchip_thermal_data *thermal = sensor->thermal;
  966. const struct rockchip_tsadc_chip *tsadc = thermal->chip;
  967. dev_dbg(&thermal->pdev->dev, "%s: sensor %d: low: %d, high %d\n",
  968. __func__, sensor->id, low, high);
  969. return tsadc->set_alarm_temp(&tsadc->table,
  970. sensor->id, thermal->regs, high);
  971. }
  972. static int rockchip_thermal_get_temp(void *_sensor, int *out_temp)
  973. {
  974. struct rockchip_thermal_sensor *sensor = _sensor;
  975. struct rockchip_thermal_data *thermal = sensor->thermal;
  976. const struct rockchip_tsadc_chip *tsadc = sensor->thermal->chip;
  977. int retval;
  978. retval = tsadc->get_temp(&tsadc->table,
  979. sensor->id, thermal->regs, out_temp);
  980. dev_dbg(&thermal->pdev->dev, "sensor %d - temp: %d, retval: %d\n",
  981. sensor->id, *out_temp, retval);
  982. return retval;
  983. }
  984. static const struct thermal_zone_of_device_ops rockchip_of_thermal_ops = {
  985. .get_temp = rockchip_thermal_get_temp,
  986. .set_trips = rockchip_thermal_set_trips,
  987. };
  988. static int rockchip_configure_from_dt(struct device *dev,
  989. struct device_node *np,
  990. struct rockchip_thermal_data *thermal)
  991. {
  992. u32 shut_temp, tshut_mode, tshut_polarity;
  993. if (of_property_read_u32(np, "rockchip,hw-tshut-temp", &shut_temp)) {
  994. dev_warn(dev,
  995. "Missing tshut temp property, using default %d\n",
  996. thermal->chip->tshut_temp);
  997. thermal->tshut_temp = thermal->chip->tshut_temp;
  998. } else {
  999. if (shut_temp > INT_MAX) {
  1000. dev_err(dev, "Invalid tshut temperature specified: %d\n",
  1001. shut_temp);
  1002. return -ERANGE;
  1003. }
  1004. thermal->tshut_temp = shut_temp;
  1005. }
  1006. if (of_property_read_u32(np, "rockchip,hw-tshut-mode", &tshut_mode)) {
  1007. dev_warn(dev,
  1008. "Missing tshut mode property, using default (%s)\n",
  1009. thermal->chip->tshut_mode == TSHUT_MODE_GPIO ?
  1010. "gpio" : "cru");
  1011. thermal->tshut_mode = thermal->chip->tshut_mode;
  1012. } else {
  1013. thermal->tshut_mode = tshut_mode;
  1014. }
  1015. if (thermal->tshut_mode > 1) {
  1016. dev_err(dev, "Invalid tshut mode specified: %d\n",
  1017. thermal->tshut_mode);
  1018. return -EINVAL;
  1019. }
  1020. if (of_property_read_u32(np, "rockchip,hw-tshut-polarity",
  1021. &tshut_polarity)) {
  1022. dev_warn(dev,
  1023. "Missing tshut-polarity property, using default (%s)\n",
  1024. thermal->chip->tshut_polarity == TSHUT_LOW_ACTIVE ?
  1025. "low" : "high");
  1026. thermal->tshut_polarity = thermal->chip->tshut_polarity;
  1027. } else {
  1028. thermal->tshut_polarity = tshut_polarity;
  1029. }
  1030. if (thermal->tshut_polarity > 1) {
  1031. dev_err(dev, "Invalid tshut-polarity specified: %d\n",
  1032. thermal->tshut_polarity);
  1033. return -EINVAL;
  1034. }
  1035. /* The tsadc wont to handle the error in here since some SoCs didn't
  1036. * need this property.
  1037. */
  1038. thermal->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
  1039. if (IS_ERR(thermal->grf))
  1040. dev_warn(dev, "Missing rockchip,grf property\n");
  1041. return 0;
  1042. }
  1043. static int
  1044. rockchip_thermal_register_sensor(struct platform_device *pdev,
  1045. struct rockchip_thermal_data *thermal,
  1046. struct rockchip_thermal_sensor *sensor,
  1047. int id)
  1048. {
  1049. const struct rockchip_tsadc_chip *tsadc = thermal->chip;
  1050. int error;
  1051. tsadc->set_tshut_mode(id, thermal->regs, thermal->tshut_mode);
  1052. error = tsadc->set_tshut_temp(&tsadc->table, id, thermal->regs,
  1053. thermal->tshut_temp);
  1054. if (error)
  1055. dev_err(&pdev->dev, "%s: invalid tshut=%d, error=%d\n",
  1056. __func__, thermal->tshut_temp, error);
  1057. sensor->thermal = thermal;
  1058. sensor->id = id;
  1059. sensor->tzd = devm_thermal_zone_of_sensor_register(&pdev->dev, id,
  1060. sensor, &rockchip_of_thermal_ops);
  1061. if (IS_ERR(sensor->tzd)) {
  1062. error = PTR_ERR(sensor->tzd);
  1063. dev_err(&pdev->dev, "failed to register sensor %d: %d\n",
  1064. id, error);
  1065. return error;
  1066. }
  1067. return 0;
  1068. }
  1069. /**
  1070. * Reset TSADC Controller, reset all tsadc registers.
  1071. * @reset: the reset controller of tsadc
  1072. */
  1073. static void rockchip_thermal_reset_controller(struct reset_control *reset)
  1074. {
  1075. reset_control_assert(reset);
  1076. usleep_range(10, 20);
  1077. reset_control_deassert(reset);
  1078. }
  1079. static int rockchip_thermal_probe(struct platform_device *pdev)
  1080. {
  1081. struct device_node *np = pdev->dev.of_node;
  1082. struct rockchip_thermal_data *thermal;
  1083. const struct of_device_id *match;
  1084. struct resource *res;
  1085. int irq;
  1086. int i;
  1087. int error;
  1088. match = of_match_node(of_rockchip_thermal_match, np);
  1089. if (!match)
  1090. return -ENXIO;
  1091. irq = platform_get_irq(pdev, 0);
  1092. if (irq < 0)
  1093. return -EINVAL;
  1094. thermal = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_thermal_data),
  1095. GFP_KERNEL);
  1096. if (!thermal)
  1097. return -ENOMEM;
  1098. thermal->pdev = pdev;
  1099. thermal->chip = (const struct rockchip_tsadc_chip *)match->data;
  1100. if (!thermal->chip)
  1101. return -EINVAL;
  1102. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1103. thermal->regs = devm_ioremap_resource(&pdev->dev, res);
  1104. if (IS_ERR(thermal->regs))
  1105. return PTR_ERR(thermal->regs);
  1106. thermal->reset = devm_reset_control_get(&pdev->dev, "tsadc-apb");
  1107. if (IS_ERR(thermal->reset)) {
  1108. error = PTR_ERR(thermal->reset);
  1109. dev_err(&pdev->dev, "failed to get tsadc reset: %d\n", error);
  1110. return error;
  1111. }
  1112. thermal->clk = devm_clk_get(&pdev->dev, "tsadc");
  1113. if (IS_ERR(thermal->clk)) {
  1114. error = PTR_ERR(thermal->clk);
  1115. dev_err(&pdev->dev, "failed to get tsadc clock: %d\n", error);
  1116. return error;
  1117. }
  1118. thermal->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
  1119. if (IS_ERR(thermal->pclk)) {
  1120. error = PTR_ERR(thermal->pclk);
  1121. dev_err(&pdev->dev, "failed to get apb_pclk clock: %d\n",
  1122. error);
  1123. return error;
  1124. }
  1125. error = clk_prepare_enable(thermal->clk);
  1126. if (error) {
  1127. dev_err(&pdev->dev, "failed to enable converter clock: %d\n",
  1128. error);
  1129. return error;
  1130. }
  1131. error = clk_prepare_enable(thermal->pclk);
  1132. if (error) {
  1133. dev_err(&pdev->dev, "failed to enable pclk: %d\n", error);
  1134. goto err_disable_clk;
  1135. }
  1136. rockchip_thermal_reset_controller(thermal->reset);
  1137. error = rockchip_configure_from_dt(&pdev->dev, np, thermal);
  1138. if (error) {
  1139. dev_err(&pdev->dev, "failed to parse device tree data: %d\n",
  1140. error);
  1141. goto err_disable_pclk;
  1142. }
  1143. thermal->chip->initialize(thermal->grf, thermal->regs,
  1144. thermal->tshut_polarity);
  1145. for (i = 0; i < thermal->chip->chn_num; i++) {
  1146. error = rockchip_thermal_register_sensor(pdev, thermal,
  1147. &thermal->sensors[i],
  1148. thermal->chip->chn_id[i]);
  1149. if (error) {
  1150. dev_err(&pdev->dev,
  1151. "failed to register sensor[%d] : error = %d\n",
  1152. i, error);
  1153. goto err_disable_pclk;
  1154. }
  1155. }
  1156. error = devm_request_threaded_irq(&pdev->dev, irq, NULL,
  1157. &rockchip_thermal_alarm_irq_thread,
  1158. IRQF_ONESHOT,
  1159. "rockchip_thermal", thermal);
  1160. if (error) {
  1161. dev_err(&pdev->dev,
  1162. "failed to request tsadc irq: %d\n", error);
  1163. goto err_disable_pclk;
  1164. }
  1165. thermal->chip->control(thermal->regs, true);
  1166. for (i = 0; i < thermal->chip->chn_num; i++) {
  1167. rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
  1168. thermal->sensors[i].tzd->tzp->no_hwmon = false;
  1169. error = thermal_add_hwmon_sysfs(thermal->sensors[i].tzd);
  1170. if (error)
  1171. dev_warn(&pdev->dev,
  1172. "failed to register sensor %d with hwmon: %d\n",
  1173. i, error);
  1174. }
  1175. platform_set_drvdata(pdev, thermal);
  1176. return 0;
  1177. err_disable_pclk:
  1178. clk_disable_unprepare(thermal->pclk);
  1179. err_disable_clk:
  1180. clk_disable_unprepare(thermal->clk);
  1181. return error;
  1182. }
  1183. static int rockchip_thermal_remove(struct platform_device *pdev)
  1184. {
  1185. struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev);
  1186. int i;
  1187. for (i = 0; i < thermal->chip->chn_num; i++) {
  1188. struct rockchip_thermal_sensor *sensor = &thermal->sensors[i];
  1189. thermal_remove_hwmon_sysfs(sensor->tzd);
  1190. rockchip_thermal_toggle_sensor(sensor, false);
  1191. }
  1192. thermal->chip->control(thermal->regs, false);
  1193. clk_disable_unprepare(thermal->pclk);
  1194. clk_disable_unprepare(thermal->clk);
  1195. return 0;
  1196. }
  1197. static int __maybe_unused rockchip_thermal_suspend(struct device *dev)
  1198. {
  1199. struct rockchip_thermal_data *thermal = dev_get_drvdata(dev);
  1200. int i;
  1201. for (i = 0; i < thermal->chip->chn_num; i++)
  1202. rockchip_thermal_toggle_sensor(&thermal->sensors[i], false);
  1203. thermal->chip->control(thermal->regs, false);
  1204. clk_disable(thermal->pclk);
  1205. clk_disable(thermal->clk);
  1206. pinctrl_pm_select_sleep_state(dev);
  1207. return 0;
  1208. }
  1209. static int __maybe_unused rockchip_thermal_resume(struct device *dev)
  1210. {
  1211. struct rockchip_thermal_data *thermal = dev_get_drvdata(dev);
  1212. int i;
  1213. int error;
  1214. error = clk_enable(thermal->clk);
  1215. if (error)
  1216. return error;
  1217. error = clk_enable(thermal->pclk);
  1218. if (error) {
  1219. clk_disable(thermal->clk);
  1220. return error;
  1221. }
  1222. rockchip_thermal_reset_controller(thermal->reset);
  1223. thermal->chip->initialize(thermal->grf, thermal->regs,
  1224. thermal->tshut_polarity);
  1225. for (i = 0; i < thermal->chip->chn_num; i++) {
  1226. int id = thermal->sensors[i].id;
  1227. thermal->chip->set_tshut_mode(id, thermal->regs,
  1228. thermal->tshut_mode);
  1229. error = thermal->chip->set_tshut_temp(&thermal->chip->table,
  1230. id, thermal->regs,
  1231. thermal->tshut_temp);
  1232. if (error)
  1233. dev_err(dev, "%s: invalid tshut=%d, error=%d\n",
  1234. __func__, thermal->tshut_temp, error);
  1235. }
  1236. thermal->chip->control(thermal->regs, true);
  1237. for (i = 0; i < thermal->chip->chn_num; i++)
  1238. rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
  1239. pinctrl_pm_select_default_state(dev);
  1240. return 0;
  1241. }
  1242. static SIMPLE_DEV_PM_OPS(rockchip_thermal_pm_ops,
  1243. rockchip_thermal_suspend, rockchip_thermal_resume);
  1244. static struct platform_driver rockchip_thermal_driver = {
  1245. .driver = {
  1246. .name = "rockchip-thermal",
  1247. .pm = &rockchip_thermal_pm_ops,
  1248. .of_match_table = of_rockchip_thermal_match,
  1249. },
  1250. .probe = rockchip_thermal_probe,
  1251. .remove = rockchip_thermal_remove,
  1252. };
  1253. module_platform_driver(rockchip_thermal_driver);
  1254. MODULE_DESCRIPTION("ROCKCHIP THERMAL Driver");
  1255. MODULE_AUTHOR("Rockchip, Inc.");
  1256. MODULE_LICENSE("GPL v2");
  1257. MODULE_ALIAS("platform:rockchip-thermal");