qoriq_thermal.c 9.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Copyright 2016 Freescale Semiconductor, Inc.
  4. #include <linux/clk.h>
  5. #include <linux/err.h>
  6. #include <linux/io.h>
  7. #include <linux/module.h>
  8. #include <linux/of.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/regmap.h>
  11. #include <linux/sizes.h>
  12. #include <linux/thermal.h>
  13. #include <linux/units.h>
  14. #include "thermal_core.h"
  15. #include "thermal_hwmon.h"
  16. #define SITES_MAX 16
  17. #define TMR_DISABLE 0x0
  18. #define TMR_ME 0x80000000
  19. #define TMR_ALPF 0x0c000000
  20. #define TMR_ALPF_V2 0x03000000
  21. #define TMTMIR_DEFAULT 0x0000000f
  22. #define TIER_DISABLE 0x0
  23. #define TEUMR0_V2 0x51009c00
  24. #define TMSARA_V2 0xe
  25. #define TMU_VER1 0x1
  26. #define TMU_VER2 0x2
  27. #define REGS_TMR 0x000 /* Mode Register */
  28. #define TMR_DISABLE 0x0
  29. #define TMR_ME 0x80000000
  30. #define TMR_ALPF 0x0c000000
  31. #define TMR_MSITE_ALL GENMASK(15, 0)
  32. #define REGS_TMTMIR 0x008 /* Temperature measurement interval Register */
  33. #define TMTMIR_DEFAULT 0x0000000f
  34. #define REGS_V2_TMSR 0x008 /* monitor site register */
  35. #define REGS_V2_TMTMIR 0x00c /* Temperature measurement interval Register */
  36. #define REGS_TIER 0x020 /* Interrupt Enable Register */
  37. #define TIER_DISABLE 0x0
  38. #define REGS_TTCFGR 0x080 /* Temperature Configuration Register */
  39. #define REGS_TSCFGR 0x084 /* Sensor Configuration Register */
  40. #define REGS_TRITSR(n) (0x100 + 16 * (n)) /* Immediate Temperature
  41. * Site Register
  42. */
  43. #define TRITSR_V BIT(31)
  44. #define REGS_V2_TMSAR(n) (0x304 + 16 * (n)) /* TMU monitoring
  45. * site adjustment register
  46. */
  47. #define REGS_TTRnCR(n) (0xf10 + 4 * (n)) /* Temperature Range n
  48. * Control Register
  49. */
  50. #define REGS_IPBRR(n) (0xbf8 + 4 * (n)) /* IP Block Revision
  51. * Register n
  52. */
  53. #define REGS_V2_TEUMR(n) (0xf00 + 4 * (n))
  54. /*
  55. * Thermal zone data
  56. */
  57. struct qoriq_sensor {
  58. int id;
  59. };
  60. struct qoriq_tmu_data {
  61. int ver;
  62. struct regmap *regmap;
  63. struct clk *clk;
  64. struct qoriq_sensor sensor[SITES_MAX];
  65. };
  66. static struct qoriq_tmu_data *qoriq_sensor_to_data(struct qoriq_sensor *s)
  67. {
  68. return container_of(s, struct qoriq_tmu_data, sensor[s->id]);
  69. }
  70. static int tmu_get_temp(void *p, int *temp)
  71. {
  72. struct qoriq_sensor *qsensor = p;
  73. struct qoriq_tmu_data *qdata = qoriq_sensor_to_data(qsensor);
  74. u32 val;
  75. /*
  76. * REGS_TRITSR(id) has the following layout:
  77. *
  78. * For TMU Rev1:
  79. * 31 ... 7 6 5 4 3 2 1 0
  80. * V TEMP
  81. *
  82. * Where V bit signifies if the measurement is ready and is
  83. * within sensor range. TEMP is an 8 bit value representing
  84. * temperature in Celsius.
  85. * For TMU Rev2:
  86. * 31 ... 8 7 6 5 4 3 2 1 0
  87. * V TEMP
  88. *
  89. * Where V bit signifies if the measurement is ready and is
  90. * within sensor range. TEMP is an 9 bit value representing
  91. * temperature in KelVin.
  92. */
  93. if (regmap_read_poll_timeout(qdata->regmap,
  94. REGS_TRITSR(qsensor->id),
  95. val,
  96. val & TRITSR_V,
  97. USEC_PER_MSEC,
  98. 10 * USEC_PER_MSEC))
  99. return -ENODATA;
  100. if (qdata->ver == TMU_VER1)
  101. *temp = (val & GENMASK(7, 0)) * MILLIDEGREE_PER_DEGREE;
  102. else
  103. *temp = kelvin_to_millicelsius(val & GENMASK(8, 0));
  104. return 0;
  105. }
  106. static const struct thermal_zone_of_device_ops tmu_tz_ops = {
  107. .get_temp = tmu_get_temp,
  108. };
  109. static int qoriq_tmu_register_tmu_zone(struct device *dev,
  110. struct qoriq_tmu_data *qdata)
  111. {
  112. int id;
  113. if (qdata->ver == TMU_VER1) {
  114. regmap_write(qdata->regmap, REGS_TMR,
  115. TMR_MSITE_ALL | TMR_ME | TMR_ALPF);
  116. } else {
  117. regmap_write(qdata->regmap, REGS_V2_TMSR, TMR_MSITE_ALL);
  118. regmap_write(qdata->regmap, REGS_TMR, TMR_ME | TMR_ALPF_V2);
  119. }
  120. for (id = 0; id < SITES_MAX; id++) {
  121. struct thermal_zone_device *tzd;
  122. struct qoriq_sensor *sensor = &qdata->sensor[id];
  123. int ret;
  124. sensor->id = id;
  125. tzd = devm_thermal_zone_of_sensor_register(dev, id,
  126. sensor,
  127. &tmu_tz_ops);
  128. ret = PTR_ERR_OR_ZERO(tzd);
  129. if (ret) {
  130. if (ret == -ENODEV)
  131. continue;
  132. regmap_write(qdata->regmap, REGS_TMR, TMR_DISABLE);
  133. return ret;
  134. }
  135. if (devm_thermal_add_hwmon_sysfs(tzd))
  136. dev_warn(dev,
  137. "Failed to add hwmon sysfs attributes\n");
  138. }
  139. return 0;
  140. }
  141. static int qoriq_tmu_calibration(struct device *dev,
  142. struct qoriq_tmu_data *data)
  143. {
  144. int i, val, len;
  145. u32 range[4];
  146. const u32 *calibration;
  147. struct device_node *np = dev->of_node;
  148. len = of_property_count_u32_elems(np, "fsl,tmu-range");
  149. if (len < 0 || len > 4) {
  150. dev_err(dev, "invalid range data.\n");
  151. return len;
  152. }
  153. val = of_property_read_u32_array(np, "fsl,tmu-range", range, len);
  154. if (val != 0) {
  155. dev_err(dev, "failed to read range data.\n");
  156. return val;
  157. }
  158. /* Init temperature range registers */
  159. for (i = 0; i < len; i++)
  160. regmap_write(data->regmap, REGS_TTRnCR(i), range[i]);
  161. calibration = of_get_property(np, "fsl,tmu-calibration", &len);
  162. if (calibration == NULL || len % 8) {
  163. dev_err(dev, "invalid calibration data.\n");
  164. return -ENODEV;
  165. }
  166. for (i = 0; i < len; i += 8, calibration += 2) {
  167. val = of_read_number(calibration, 1);
  168. regmap_write(data->regmap, REGS_TTCFGR, val);
  169. val = of_read_number(calibration + 1, 1);
  170. regmap_write(data->regmap, REGS_TSCFGR, val);
  171. }
  172. return 0;
  173. }
  174. static void qoriq_tmu_init_device(struct qoriq_tmu_data *data)
  175. {
  176. int i;
  177. /* Disable interrupt, using polling instead */
  178. regmap_write(data->regmap, REGS_TIER, TIER_DISABLE);
  179. /* Set update_interval */
  180. if (data->ver == TMU_VER1) {
  181. regmap_write(data->regmap, REGS_TMTMIR, TMTMIR_DEFAULT);
  182. } else {
  183. regmap_write(data->regmap, REGS_V2_TMTMIR, TMTMIR_DEFAULT);
  184. regmap_write(data->regmap, REGS_V2_TEUMR(0), TEUMR0_V2);
  185. for (i = 0; i < SITES_MAX; i++)
  186. regmap_write(data->regmap, REGS_V2_TMSAR(i), TMSARA_V2);
  187. }
  188. /* Disable monitoring */
  189. regmap_write(data->regmap, REGS_TMR, TMR_DISABLE);
  190. }
  191. static const struct regmap_range qoriq_yes_ranges[] = {
  192. regmap_reg_range(REGS_TMR, REGS_TSCFGR),
  193. regmap_reg_range(REGS_TTRnCR(0), REGS_TTRnCR(3)),
  194. regmap_reg_range(REGS_V2_TEUMR(0), REGS_V2_TEUMR(2)),
  195. regmap_reg_range(REGS_V2_TMSAR(0), REGS_V2_TMSAR(15)),
  196. regmap_reg_range(REGS_IPBRR(0), REGS_IPBRR(1)),
  197. /* Read only registers below */
  198. regmap_reg_range(REGS_TRITSR(0), REGS_TRITSR(15)),
  199. };
  200. static const struct regmap_access_table qoriq_wr_table = {
  201. .yes_ranges = qoriq_yes_ranges,
  202. .n_yes_ranges = ARRAY_SIZE(qoriq_yes_ranges) - 1,
  203. };
  204. static const struct regmap_access_table qoriq_rd_table = {
  205. .yes_ranges = qoriq_yes_ranges,
  206. .n_yes_ranges = ARRAY_SIZE(qoriq_yes_ranges),
  207. };
  208. static void qoriq_tmu_action(void *p)
  209. {
  210. struct qoriq_tmu_data *data = p;
  211. regmap_write(data->regmap, REGS_TMR, TMR_DISABLE);
  212. clk_disable_unprepare(data->clk);
  213. }
  214. static int qoriq_tmu_probe(struct platform_device *pdev)
  215. {
  216. int ret;
  217. u32 ver;
  218. struct qoriq_tmu_data *data;
  219. struct device_node *np = pdev->dev.of_node;
  220. struct device *dev = &pdev->dev;
  221. const bool little_endian = of_property_read_bool(np, "little-endian");
  222. const enum regmap_endian format_endian =
  223. little_endian ? REGMAP_ENDIAN_LITTLE : REGMAP_ENDIAN_BIG;
  224. const struct regmap_config regmap_config = {
  225. .reg_bits = 32,
  226. .val_bits = 32,
  227. .reg_stride = 4,
  228. .rd_table = &qoriq_rd_table,
  229. .wr_table = &qoriq_wr_table,
  230. .val_format_endian = format_endian,
  231. .max_register = SZ_4K,
  232. };
  233. void __iomem *base;
  234. data = devm_kzalloc(dev, sizeof(struct qoriq_tmu_data),
  235. GFP_KERNEL);
  236. if (!data)
  237. return -ENOMEM;
  238. base = devm_platform_ioremap_resource(pdev, 0);
  239. ret = PTR_ERR_OR_ZERO(base);
  240. if (ret) {
  241. dev_err(dev, "Failed to get memory region\n");
  242. return ret;
  243. }
  244. data->regmap = devm_regmap_init_mmio(dev, base, &regmap_config);
  245. ret = PTR_ERR_OR_ZERO(data->regmap);
  246. if (ret) {
  247. dev_err(dev, "Failed to init regmap (%d)\n", ret);
  248. return ret;
  249. }
  250. data->clk = devm_clk_get_optional(dev, NULL);
  251. if (IS_ERR(data->clk))
  252. return PTR_ERR(data->clk);
  253. ret = clk_prepare_enable(data->clk);
  254. if (ret) {
  255. dev_err(dev, "Failed to enable clock\n");
  256. return ret;
  257. }
  258. ret = devm_add_action_or_reset(dev, qoriq_tmu_action, data);
  259. if (ret)
  260. return ret;
  261. /* version register offset at: 0xbf8 on both v1 and v2 */
  262. ret = regmap_read(data->regmap, REGS_IPBRR(0), &ver);
  263. if (ret) {
  264. dev_err(&pdev->dev, "Failed to read IP block version\n");
  265. return ret;
  266. }
  267. data->ver = (ver >> 8) & 0xff;
  268. qoriq_tmu_init_device(data); /* TMU initialization */
  269. ret = qoriq_tmu_calibration(dev, data); /* TMU calibration */
  270. if (ret < 0)
  271. return ret;
  272. ret = qoriq_tmu_register_tmu_zone(dev, data);
  273. if (ret < 0) {
  274. dev_err(dev, "Failed to register sensors\n");
  275. return ret;
  276. }
  277. platform_set_drvdata(pdev, data);
  278. return 0;
  279. }
  280. static int __maybe_unused qoriq_tmu_suspend(struct device *dev)
  281. {
  282. struct qoriq_tmu_data *data = dev_get_drvdata(dev);
  283. int ret;
  284. ret = regmap_update_bits(data->regmap, REGS_TMR, TMR_ME, 0);
  285. if (ret)
  286. return ret;
  287. clk_disable_unprepare(data->clk);
  288. return 0;
  289. }
  290. static int __maybe_unused qoriq_tmu_resume(struct device *dev)
  291. {
  292. int ret;
  293. struct qoriq_tmu_data *data = dev_get_drvdata(dev);
  294. ret = clk_prepare_enable(data->clk);
  295. if (ret)
  296. return ret;
  297. /* Enable monitoring */
  298. return regmap_update_bits(data->regmap, REGS_TMR, TMR_ME, TMR_ME);
  299. }
  300. static SIMPLE_DEV_PM_OPS(qoriq_tmu_pm_ops,
  301. qoriq_tmu_suspend, qoriq_tmu_resume);
  302. static const struct of_device_id qoriq_tmu_match[] = {
  303. { .compatible = "fsl,qoriq-tmu", },
  304. { .compatible = "fsl,imx8mq-tmu", },
  305. {},
  306. };
  307. MODULE_DEVICE_TABLE(of, qoriq_tmu_match);
  308. static struct platform_driver qoriq_tmu = {
  309. .driver = {
  310. .name = "qoriq_thermal",
  311. .pm = &qoriq_tmu_pm_ops,
  312. .of_match_table = qoriq_tmu_match,
  313. },
  314. .probe = qoriq_tmu_probe,
  315. };
  316. module_platform_driver(qoriq_tmu);
  317. MODULE_AUTHOR("Jia Hongtao <hongtao.jia@nxp.com>");
  318. MODULE_DESCRIPTION("QorIQ Thermal Monitoring Unit driver");
  319. MODULE_LICENSE("GPL v2");