tsens.h 15 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (c) 2015, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef __QCOM_TSENS_H__
  6. #define __QCOM_TSENS_H__
  7. #define ONE_PT_CALIB 0x1
  8. #define ONE_PT_CALIB2 0x2
  9. #define TWO_PT_CALIB 0x3
  10. #define CAL_DEGC_PT1 30
  11. #define CAL_DEGC_PT2 120
  12. #define SLOPE_FACTOR 1000
  13. #define SLOPE_DEFAULT 3200
  14. #define THRESHOLD_MAX_ADC_CODE 0x3ff
  15. #define THRESHOLD_MIN_ADC_CODE 0x0
  16. #include <linux/interrupt.h>
  17. #include <linux/thermal.h>
  18. #include <linux/regmap.h>
  19. #include <linux/slab.h>
  20. struct tsens_priv;
  21. /* IP version numbers in ascending order */
  22. enum tsens_ver {
  23. VER_0_1 = 0,
  24. VER_1_X,
  25. VER_2_X,
  26. };
  27. enum tsens_irq_type {
  28. LOWER,
  29. UPPER,
  30. CRITICAL,
  31. };
  32. /**
  33. * struct tsens_sensor - data for each sensor connected to the tsens device
  34. * @priv: tsens device instance that this sensor is connected to
  35. * @tzd: pointer to the thermal zone that this sensor is in
  36. * @offset: offset of temperature adjustment curve
  37. * @hw_id: HW ID can be used in case of platform-specific IDs
  38. * @slope: slope of temperature adjustment curve
  39. * @status: 8960-specific variable to track 8960 and 8660 status register offset
  40. */
  41. struct tsens_sensor {
  42. struct tsens_priv *priv;
  43. struct thermal_zone_device *tzd;
  44. int offset;
  45. unsigned int hw_id;
  46. int slope;
  47. u32 status;
  48. };
  49. /**
  50. * struct tsens_ops - operations as supported by the tsens device
  51. * @init: Function to initialize the tsens device
  52. * @calibrate: Function to calibrate the tsens device
  53. * @get_temp: Function which returns the temp in millidegC
  54. * @enable: Function to enable (clocks/power) tsens device
  55. * @disable: Function to disable the tsens device
  56. * @suspend: Function to suspend the tsens device
  57. * @resume: Function to resume the tsens device
  58. * @get_trend: Function to get the thermal/temp trend
  59. */
  60. struct tsens_ops {
  61. /* mandatory callbacks */
  62. int (*init)(struct tsens_priv *priv);
  63. int (*calibrate)(struct tsens_priv *priv);
  64. int (*get_temp)(const struct tsens_sensor *s, int *temp);
  65. /* optional callbacks */
  66. int (*enable)(struct tsens_priv *priv, int i);
  67. void (*disable)(struct tsens_priv *priv);
  68. int (*suspend)(struct tsens_priv *priv);
  69. int (*resume)(struct tsens_priv *priv);
  70. int (*get_trend)(struct tsens_sensor *s, enum thermal_trend *trend);
  71. };
  72. #define REG_FIELD_FOR_EACH_SENSOR11(_name, _offset, _startbit, _stopbit) \
  73. [_name##_##0] = REG_FIELD(_offset, _startbit, _stopbit), \
  74. [_name##_##1] = REG_FIELD(_offset + 4, _startbit, _stopbit), \
  75. [_name##_##2] = REG_FIELD(_offset + 8, _startbit, _stopbit), \
  76. [_name##_##3] = REG_FIELD(_offset + 12, _startbit, _stopbit), \
  77. [_name##_##4] = REG_FIELD(_offset + 16, _startbit, _stopbit), \
  78. [_name##_##5] = REG_FIELD(_offset + 20, _startbit, _stopbit), \
  79. [_name##_##6] = REG_FIELD(_offset + 24, _startbit, _stopbit), \
  80. [_name##_##7] = REG_FIELD(_offset + 28, _startbit, _stopbit), \
  81. [_name##_##8] = REG_FIELD(_offset + 32, _startbit, _stopbit), \
  82. [_name##_##9] = REG_FIELD(_offset + 36, _startbit, _stopbit), \
  83. [_name##_##10] = REG_FIELD(_offset + 40, _startbit, _stopbit)
  84. #define REG_FIELD_FOR_EACH_SENSOR16(_name, _offset, _startbit, _stopbit) \
  85. [_name##_##0] = REG_FIELD(_offset, _startbit, _stopbit), \
  86. [_name##_##1] = REG_FIELD(_offset + 4, _startbit, _stopbit), \
  87. [_name##_##2] = REG_FIELD(_offset + 8, _startbit, _stopbit), \
  88. [_name##_##3] = REG_FIELD(_offset + 12, _startbit, _stopbit), \
  89. [_name##_##4] = REG_FIELD(_offset + 16, _startbit, _stopbit), \
  90. [_name##_##5] = REG_FIELD(_offset + 20, _startbit, _stopbit), \
  91. [_name##_##6] = REG_FIELD(_offset + 24, _startbit, _stopbit), \
  92. [_name##_##7] = REG_FIELD(_offset + 28, _startbit, _stopbit), \
  93. [_name##_##8] = REG_FIELD(_offset + 32, _startbit, _stopbit), \
  94. [_name##_##9] = REG_FIELD(_offset + 36, _startbit, _stopbit), \
  95. [_name##_##10] = REG_FIELD(_offset + 40, _startbit, _stopbit), \
  96. [_name##_##11] = REG_FIELD(_offset + 44, _startbit, _stopbit), \
  97. [_name##_##12] = REG_FIELD(_offset + 48, _startbit, _stopbit), \
  98. [_name##_##13] = REG_FIELD(_offset + 52, _startbit, _stopbit), \
  99. [_name##_##14] = REG_FIELD(_offset + 56, _startbit, _stopbit), \
  100. [_name##_##15] = REG_FIELD(_offset + 60, _startbit, _stopbit)
  101. #define REG_FIELD_SPLIT_BITS_0_15(_name, _offset) \
  102. [_name##_##0] = REG_FIELD(_offset, 0, 0), \
  103. [_name##_##1] = REG_FIELD(_offset, 1, 1), \
  104. [_name##_##2] = REG_FIELD(_offset, 2, 2), \
  105. [_name##_##3] = REG_FIELD(_offset, 3, 3), \
  106. [_name##_##4] = REG_FIELD(_offset, 4, 4), \
  107. [_name##_##5] = REG_FIELD(_offset, 5, 5), \
  108. [_name##_##6] = REG_FIELD(_offset, 6, 6), \
  109. [_name##_##7] = REG_FIELD(_offset, 7, 7), \
  110. [_name##_##8] = REG_FIELD(_offset, 8, 8), \
  111. [_name##_##9] = REG_FIELD(_offset, 9, 9), \
  112. [_name##_##10] = REG_FIELD(_offset, 10, 10), \
  113. [_name##_##11] = REG_FIELD(_offset, 11, 11), \
  114. [_name##_##12] = REG_FIELD(_offset, 12, 12), \
  115. [_name##_##13] = REG_FIELD(_offset, 13, 13), \
  116. [_name##_##14] = REG_FIELD(_offset, 14, 14), \
  117. [_name##_##15] = REG_FIELD(_offset, 15, 15)
  118. #define REG_FIELD_SPLIT_BITS_16_31(_name, _offset) \
  119. [_name##_##0] = REG_FIELD(_offset, 16, 16), \
  120. [_name##_##1] = REG_FIELD(_offset, 17, 17), \
  121. [_name##_##2] = REG_FIELD(_offset, 18, 18), \
  122. [_name##_##3] = REG_FIELD(_offset, 19, 19), \
  123. [_name##_##4] = REG_FIELD(_offset, 20, 20), \
  124. [_name##_##5] = REG_FIELD(_offset, 21, 21), \
  125. [_name##_##6] = REG_FIELD(_offset, 22, 22), \
  126. [_name##_##7] = REG_FIELD(_offset, 23, 23), \
  127. [_name##_##8] = REG_FIELD(_offset, 24, 24), \
  128. [_name##_##9] = REG_FIELD(_offset, 25, 25), \
  129. [_name##_##10] = REG_FIELD(_offset, 26, 26), \
  130. [_name##_##11] = REG_FIELD(_offset, 27, 27), \
  131. [_name##_##12] = REG_FIELD(_offset, 28, 28), \
  132. [_name##_##13] = REG_FIELD(_offset, 29, 29), \
  133. [_name##_##14] = REG_FIELD(_offset, 30, 30), \
  134. [_name##_##15] = REG_FIELD(_offset, 31, 31)
  135. /*
  136. * reg_field IDs to use as an index into an array
  137. * If you change the order of the entries, check the devm_regmap_field_alloc()
  138. * calls in init_common()
  139. */
  140. enum regfield_ids {
  141. /* ----- SROT ------ */
  142. /* HW_VER */
  143. VER_MAJOR,
  144. VER_MINOR,
  145. VER_STEP,
  146. /* CTRL_OFFSET */
  147. TSENS_EN,
  148. TSENS_SW_RST,
  149. SENSOR_EN,
  150. CODE_OR_TEMP,
  151. /* ----- TM ------ */
  152. /* TRDY */
  153. TRDY,
  154. /* INTERRUPT ENABLE */
  155. INT_EN, /* v2+ has separate enables for crit, upper and lower irq */
  156. /* STATUS */
  157. LAST_TEMP_0, /* Last temperature reading */
  158. LAST_TEMP_1,
  159. LAST_TEMP_2,
  160. LAST_TEMP_3,
  161. LAST_TEMP_4,
  162. LAST_TEMP_5,
  163. LAST_TEMP_6,
  164. LAST_TEMP_7,
  165. LAST_TEMP_8,
  166. LAST_TEMP_9,
  167. LAST_TEMP_10,
  168. LAST_TEMP_11,
  169. LAST_TEMP_12,
  170. LAST_TEMP_13,
  171. LAST_TEMP_14,
  172. LAST_TEMP_15,
  173. VALID_0, /* VALID reading or not */
  174. VALID_1,
  175. VALID_2,
  176. VALID_3,
  177. VALID_4,
  178. VALID_5,
  179. VALID_6,
  180. VALID_7,
  181. VALID_8,
  182. VALID_9,
  183. VALID_10,
  184. VALID_11,
  185. VALID_12,
  186. VALID_13,
  187. VALID_14,
  188. VALID_15,
  189. LOWER_STATUS_0, /* LOWER threshold violated */
  190. LOWER_STATUS_1,
  191. LOWER_STATUS_2,
  192. LOWER_STATUS_3,
  193. LOWER_STATUS_4,
  194. LOWER_STATUS_5,
  195. LOWER_STATUS_6,
  196. LOWER_STATUS_7,
  197. LOWER_STATUS_8,
  198. LOWER_STATUS_9,
  199. LOWER_STATUS_10,
  200. LOWER_STATUS_11,
  201. LOWER_STATUS_12,
  202. LOWER_STATUS_13,
  203. LOWER_STATUS_14,
  204. LOWER_STATUS_15,
  205. LOW_INT_STATUS_0, /* LOWER interrupt status */
  206. LOW_INT_STATUS_1,
  207. LOW_INT_STATUS_2,
  208. LOW_INT_STATUS_3,
  209. LOW_INT_STATUS_4,
  210. LOW_INT_STATUS_5,
  211. LOW_INT_STATUS_6,
  212. LOW_INT_STATUS_7,
  213. LOW_INT_STATUS_8,
  214. LOW_INT_STATUS_9,
  215. LOW_INT_STATUS_10,
  216. LOW_INT_STATUS_11,
  217. LOW_INT_STATUS_12,
  218. LOW_INT_STATUS_13,
  219. LOW_INT_STATUS_14,
  220. LOW_INT_STATUS_15,
  221. LOW_INT_CLEAR_0, /* LOWER interrupt clear */
  222. LOW_INT_CLEAR_1,
  223. LOW_INT_CLEAR_2,
  224. LOW_INT_CLEAR_3,
  225. LOW_INT_CLEAR_4,
  226. LOW_INT_CLEAR_5,
  227. LOW_INT_CLEAR_6,
  228. LOW_INT_CLEAR_7,
  229. LOW_INT_CLEAR_8,
  230. LOW_INT_CLEAR_9,
  231. LOW_INT_CLEAR_10,
  232. LOW_INT_CLEAR_11,
  233. LOW_INT_CLEAR_12,
  234. LOW_INT_CLEAR_13,
  235. LOW_INT_CLEAR_14,
  236. LOW_INT_CLEAR_15,
  237. LOW_INT_MASK_0, /* LOWER interrupt mask */
  238. LOW_INT_MASK_1,
  239. LOW_INT_MASK_2,
  240. LOW_INT_MASK_3,
  241. LOW_INT_MASK_4,
  242. LOW_INT_MASK_5,
  243. LOW_INT_MASK_6,
  244. LOW_INT_MASK_7,
  245. LOW_INT_MASK_8,
  246. LOW_INT_MASK_9,
  247. LOW_INT_MASK_10,
  248. LOW_INT_MASK_11,
  249. LOW_INT_MASK_12,
  250. LOW_INT_MASK_13,
  251. LOW_INT_MASK_14,
  252. LOW_INT_MASK_15,
  253. LOW_THRESH_0, /* LOWER threshold values */
  254. LOW_THRESH_1,
  255. LOW_THRESH_2,
  256. LOW_THRESH_3,
  257. LOW_THRESH_4,
  258. LOW_THRESH_5,
  259. LOW_THRESH_6,
  260. LOW_THRESH_7,
  261. LOW_THRESH_8,
  262. LOW_THRESH_9,
  263. LOW_THRESH_10,
  264. LOW_THRESH_11,
  265. LOW_THRESH_12,
  266. LOW_THRESH_13,
  267. LOW_THRESH_14,
  268. LOW_THRESH_15,
  269. UPPER_STATUS_0, /* UPPER threshold violated */
  270. UPPER_STATUS_1,
  271. UPPER_STATUS_2,
  272. UPPER_STATUS_3,
  273. UPPER_STATUS_4,
  274. UPPER_STATUS_5,
  275. UPPER_STATUS_6,
  276. UPPER_STATUS_7,
  277. UPPER_STATUS_8,
  278. UPPER_STATUS_9,
  279. UPPER_STATUS_10,
  280. UPPER_STATUS_11,
  281. UPPER_STATUS_12,
  282. UPPER_STATUS_13,
  283. UPPER_STATUS_14,
  284. UPPER_STATUS_15,
  285. UP_INT_STATUS_0, /* UPPER interrupt status */
  286. UP_INT_STATUS_1,
  287. UP_INT_STATUS_2,
  288. UP_INT_STATUS_3,
  289. UP_INT_STATUS_4,
  290. UP_INT_STATUS_5,
  291. UP_INT_STATUS_6,
  292. UP_INT_STATUS_7,
  293. UP_INT_STATUS_8,
  294. UP_INT_STATUS_9,
  295. UP_INT_STATUS_10,
  296. UP_INT_STATUS_11,
  297. UP_INT_STATUS_12,
  298. UP_INT_STATUS_13,
  299. UP_INT_STATUS_14,
  300. UP_INT_STATUS_15,
  301. UP_INT_CLEAR_0, /* UPPER interrupt clear */
  302. UP_INT_CLEAR_1,
  303. UP_INT_CLEAR_2,
  304. UP_INT_CLEAR_3,
  305. UP_INT_CLEAR_4,
  306. UP_INT_CLEAR_5,
  307. UP_INT_CLEAR_6,
  308. UP_INT_CLEAR_7,
  309. UP_INT_CLEAR_8,
  310. UP_INT_CLEAR_9,
  311. UP_INT_CLEAR_10,
  312. UP_INT_CLEAR_11,
  313. UP_INT_CLEAR_12,
  314. UP_INT_CLEAR_13,
  315. UP_INT_CLEAR_14,
  316. UP_INT_CLEAR_15,
  317. UP_INT_MASK_0, /* UPPER interrupt mask */
  318. UP_INT_MASK_1,
  319. UP_INT_MASK_2,
  320. UP_INT_MASK_3,
  321. UP_INT_MASK_4,
  322. UP_INT_MASK_5,
  323. UP_INT_MASK_6,
  324. UP_INT_MASK_7,
  325. UP_INT_MASK_8,
  326. UP_INT_MASK_9,
  327. UP_INT_MASK_10,
  328. UP_INT_MASK_11,
  329. UP_INT_MASK_12,
  330. UP_INT_MASK_13,
  331. UP_INT_MASK_14,
  332. UP_INT_MASK_15,
  333. UP_THRESH_0, /* UPPER threshold values */
  334. UP_THRESH_1,
  335. UP_THRESH_2,
  336. UP_THRESH_3,
  337. UP_THRESH_4,
  338. UP_THRESH_5,
  339. UP_THRESH_6,
  340. UP_THRESH_7,
  341. UP_THRESH_8,
  342. UP_THRESH_9,
  343. UP_THRESH_10,
  344. UP_THRESH_11,
  345. UP_THRESH_12,
  346. UP_THRESH_13,
  347. UP_THRESH_14,
  348. UP_THRESH_15,
  349. CRITICAL_STATUS_0, /* CRITICAL threshold violated */
  350. CRITICAL_STATUS_1,
  351. CRITICAL_STATUS_2,
  352. CRITICAL_STATUS_3,
  353. CRITICAL_STATUS_4,
  354. CRITICAL_STATUS_5,
  355. CRITICAL_STATUS_6,
  356. CRITICAL_STATUS_7,
  357. CRITICAL_STATUS_8,
  358. CRITICAL_STATUS_9,
  359. CRITICAL_STATUS_10,
  360. CRITICAL_STATUS_11,
  361. CRITICAL_STATUS_12,
  362. CRITICAL_STATUS_13,
  363. CRITICAL_STATUS_14,
  364. CRITICAL_STATUS_15,
  365. CRIT_INT_STATUS_0, /* CRITICAL interrupt status */
  366. CRIT_INT_STATUS_1,
  367. CRIT_INT_STATUS_2,
  368. CRIT_INT_STATUS_3,
  369. CRIT_INT_STATUS_4,
  370. CRIT_INT_STATUS_5,
  371. CRIT_INT_STATUS_6,
  372. CRIT_INT_STATUS_7,
  373. CRIT_INT_STATUS_8,
  374. CRIT_INT_STATUS_9,
  375. CRIT_INT_STATUS_10,
  376. CRIT_INT_STATUS_11,
  377. CRIT_INT_STATUS_12,
  378. CRIT_INT_STATUS_13,
  379. CRIT_INT_STATUS_14,
  380. CRIT_INT_STATUS_15,
  381. CRIT_INT_CLEAR_0, /* CRITICAL interrupt clear */
  382. CRIT_INT_CLEAR_1,
  383. CRIT_INT_CLEAR_2,
  384. CRIT_INT_CLEAR_3,
  385. CRIT_INT_CLEAR_4,
  386. CRIT_INT_CLEAR_5,
  387. CRIT_INT_CLEAR_6,
  388. CRIT_INT_CLEAR_7,
  389. CRIT_INT_CLEAR_8,
  390. CRIT_INT_CLEAR_9,
  391. CRIT_INT_CLEAR_10,
  392. CRIT_INT_CLEAR_11,
  393. CRIT_INT_CLEAR_12,
  394. CRIT_INT_CLEAR_13,
  395. CRIT_INT_CLEAR_14,
  396. CRIT_INT_CLEAR_15,
  397. CRIT_INT_MASK_0, /* CRITICAL interrupt mask */
  398. CRIT_INT_MASK_1,
  399. CRIT_INT_MASK_2,
  400. CRIT_INT_MASK_3,
  401. CRIT_INT_MASK_4,
  402. CRIT_INT_MASK_5,
  403. CRIT_INT_MASK_6,
  404. CRIT_INT_MASK_7,
  405. CRIT_INT_MASK_8,
  406. CRIT_INT_MASK_9,
  407. CRIT_INT_MASK_10,
  408. CRIT_INT_MASK_11,
  409. CRIT_INT_MASK_12,
  410. CRIT_INT_MASK_13,
  411. CRIT_INT_MASK_14,
  412. CRIT_INT_MASK_15,
  413. CRIT_THRESH_0, /* CRITICAL threshold values */
  414. CRIT_THRESH_1,
  415. CRIT_THRESH_2,
  416. CRIT_THRESH_3,
  417. CRIT_THRESH_4,
  418. CRIT_THRESH_5,
  419. CRIT_THRESH_6,
  420. CRIT_THRESH_7,
  421. CRIT_THRESH_8,
  422. CRIT_THRESH_9,
  423. CRIT_THRESH_10,
  424. CRIT_THRESH_11,
  425. CRIT_THRESH_12,
  426. CRIT_THRESH_13,
  427. CRIT_THRESH_14,
  428. CRIT_THRESH_15,
  429. /* WATCHDOG */
  430. WDOG_BARK_STATUS,
  431. WDOG_BARK_CLEAR,
  432. WDOG_BARK_MASK,
  433. WDOG_BARK_COUNT,
  434. /* CYCLE COMPLETION MONITOR */
  435. CC_MON_STATUS,
  436. CC_MON_CLEAR,
  437. CC_MON_MASK,
  438. MIN_STATUS_0, /* MIN threshold violated */
  439. MIN_STATUS_1,
  440. MIN_STATUS_2,
  441. MIN_STATUS_3,
  442. MIN_STATUS_4,
  443. MIN_STATUS_5,
  444. MIN_STATUS_6,
  445. MIN_STATUS_7,
  446. MIN_STATUS_8,
  447. MIN_STATUS_9,
  448. MIN_STATUS_10,
  449. MIN_STATUS_11,
  450. MIN_STATUS_12,
  451. MIN_STATUS_13,
  452. MIN_STATUS_14,
  453. MIN_STATUS_15,
  454. MAX_STATUS_0, /* MAX threshold violated */
  455. MAX_STATUS_1,
  456. MAX_STATUS_2,
  457. MAX_STATUS_3,
  458. MAX_STATUS_4,
  459. MAX_STATUS_5,
  460. MAX_STATUS_6,
  461. MAX_STATUS_7,
  462. MAX_STATUS_8,
  463. MAX_STATUS_9,
  464. MAX_STATUS_10,
  465. MAX_STATUS_11,
  466. MAX_STATUS_12,
  467. MAX_STATUS_13,
  468. MAX_STATUS_14,
  469. MAX_STATUS_15,
  470. /* Keep last */
  471. MAX_REGFIELDS
  472. };
  473. /**
  474. * struct tsens_features - Features supported by the IP
  475. * @ver_major: Major number of IP version
  476. * @crit_int: does the IP support critical interrupts?
  477. * @adc: do the sensors only output adc code (instead of temperature)?
  478. * @srot_split: does the IP neatly splits the register space into SROT and TM,
  479. * with SROT only being available to secure boot firmware?
  480. * @has_watchdog: does this IP support watchdog functionality?
  481. * @max_sensors: maximum sensors supported by this version of the IP
  482. */
  483. struct tsens_features {
  484. unsigned int ver_major;
  485. unsigned int crit_int:1;
  486. unsigned int adc:1;
  487. unsigned int srot_split:1;
  488. unsigned int has_watchdog:1;
  489. unsigned int max_sensors;
  490. };
  491. /**
  492. * struct tsens_plat_data - tsens compile-time platform data
  493. * @num_sensors: Number of sensors supported by platform
  494. * @ops: operations the tsens instance supports
  495. * @hw_ids: Subset of sensors ids supported by platform, if not the first n
  496. * @feat: features of the IP
  497. * @fields: bitfield locations
  498. */
  499. struct tsens_plat_data {
  500. const u32 num_sensors;
  501. const struct tsens_ops *ops;
  502. unsigned int *hw_ids;
  503. struct tsens_features *feat;
  504. const struct reg_field *fields;
  505. };
  506. /**
  507. * struct tsens_context - Registers to be saved/restored across a context loss
  508. * @threshold: Threshold register value
  509. * @control: Control register value
  510. */
  511. struct tsens_context {
  512. int threshold;
  513. int control;
  514. };
  515. /**
  516. * struct tsens_priv - private data for each instance of the tsens IP
  517. * @dev: pointer to struct device
  518. * @num_sensors: number of sensors enabled on this device
  519. * @tm_map: pointer to TM register address space
  520. * @srot_map: pointer to SROT register address space
  521. * @tm_offset: deal with old device trees that don't address TM and SROT
  522. * address space separately
  523. * @ul_lock: lock while processing upper/lower threshold interrupts
  524. * @crit_lock: lock while processing critical threshold interrupts
  525. * @rf: array of regmap_fields used to store value of the field
  526. * @ctx: registers to be saved and restored during suspend/resume
  527. * @feat: features of the IP
  528. * @fields: bitfield locations
  529. * @ops: pointer to list of callbacks supported by this device
  530. * @debug_root: pointer to debugfs dentry for all tsens
  531. * @debug: pointer to debugfs dentry for tsens controller
  532. * @sensor: list of sensors attached to this device
  533. */
  534. struct tsens_priv {
  535. struct device *dev;
  536. u32 num_sensors;
  537. struct regmap *tm_map;
  538. struct regmap *srot_map;
  539. u32 tm_offset;
  540. /* lock for upper/lower threshold interrupts */
  541. spinlock_t ul_lock;
  542. struct regmap_field *rf[MAX_REGFIELDS];
  543. struct tsens_context ctx;
  544. struct tsens_features *feat;
  545. const struct reg_field *fields;
  546. const struct tsens_ops *ops;
  547. struct dentry *debug_root;
  548. struct dentry *debug;
  549. struct tsens_sensor sensor[];
  550. };
  551. char *qfprom_read(struct device *dev, const char *cname);
  552. void compute_intercept_slope(struct tsens_priv *priv, u32 *pt1, u32 *pt2, u32 mode);
  553. int init_common(struct tsens_priv *priv);
  554. int get_temp_tsens_valid(const struct tsens_sensor *s, int *temp);
  555. int get_temp_common(const struct tsens_sensor *s, int *temp);
  556. /* TSENS target */
  557. extern struct tsens_plat_data data_8960;
  558. /* TSENS v0.1 targets */
  559. extern struct tsens_plat_data data_8916, data_8939, data_8974;
  560. /* TSENS v1 targets */
  561. extern struct tsens_plat_data data_tsens_v1, data_8976;
  562. /* TSENS v2 targets */
  563. extern struct tsens_plat_data data_8996, data_tsens_v2;
  564. #endif /* __QCOM_TSENS_H__ */