tsens.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2015, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2019, 2020, Linaro Ltd.
  5. */
  6. #include <linux/debugfs.h>
  7. #include <linux/err.h>
  8. #include <linux/io.h>
  9. #include <linux/module.h>
  10. #include <linux/nvmem-consumer.h>
  11. #include <linux/of.h>
  12. #include <linux/of_address.h>
  13. #include <linux/of_platform.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/pm.h>
  16. #include <linux/regmap.h>
  17. #include <linux/slab.h>
  18. #include <linux/thermal.h>
  19. #include "tsens.h"
  20. /**
  21. * struct tsens_irq_data - IRQ status and temperature violations
  22. * @up_viol: upper threshold violated
  23. * @up_thresh: upper threshold temperature value
  24. * @up_irq_mask: mask register for upper threshold irqs
  25. * @up_irq_clear: clear register for uppper threshold irqs
  26. * @low_viol: lower threshold violated
  27. * @low_thresh: lower threshold temperature value
  28. * @low_irq_mask: mask register for lower threshold irqs
  29. * @low_irq_clear: clear register for lower threshold irqs
  30. * @crit_viol: critical threshold violated
  31. * @crit_thresh: critical threshold temperature value
  32. * @crit_irq_mask: mask register for critical threshold irqs
  33. * @crit_irq_clear: clear register for critical threshold irqs
  34. *
  35. * Structure containing data about temperature threshold settings and
  36. * irq status if they were violated.
  37. */
  38. struct tsens_irq_data {
  39. u32 up_viol;
  40. int up_thresh;
  41. u32 up_irq_mask;
  42. u32 up_irq_clear;
  43. u32 low_viol;
  44. int low_thresh;
  45. u32 low_irq_mask;
  46. u32 low_irq_clear;
  47. u32 crit_viol;
  48. u32 crit_thresh;
  49. u32 crit_irq_mask;
  50. u32 crit_irq_clear;
  51. };
  52. char *qfprom_read(struct device *dev, const char *cname)
  53. {
  54. struct nvmem_cell *cell;
  55. ssize_t data;
  56. char *ret;
  57. cell = nvmem_cell_get(dev, cname);
  58. if (IS_ERR(cell))
  59. return ERR_CAST(cell);
  60. ret = nvmem_cell_read(cell, &data);
  61. nvmem_cell_put(cell);
  62. return ret;
  63. }
  64. /*
  65. * Use this function on devices where slope and offset calculations
  66. * depend on calibration data read from qfprom. On others the slope
  67. * and offset values are derived from tz->tzp->slope and tz->tzp->offset
  68. * resp.
  69. */
  70. void compute_intercept_slope(struct tsens_priv *priv, u32 *p1,
  71. u32 *p2, u32 mode)
  72. {
  73. int i;
  74. int num, den;
  75. for (i = 0; i < priv->num_sensors; i++) {
  76. dev_dbg(priv->dev,
  77. "%s: sensor%d - data_point1:%#x data_point2:%#x\n",
  78. __func__, i, p1[i], p2[i]);
  79. priv->sensor[i].slope = SLOPE_DEFAULT;
  80. if (mode == TWO_PT_CALIB) {
  81. /*
  82. * slope (m) = adc_code2 - adc_code1 (y2 - y1)/
  83. * temp_120_degc - temp_30_degc (x2 - x1)
  84. */
  85. num = p2[i] - p1[i];
  86. num *= SLOPE_FACTOR;
  87. den = CAL_DEGC_PT2 - CAL_DEGC_PT1;
  88. priv->sensor[i].slope = num / den;
  89. }
  90. priv->sensor[i].offset = (p1[i] * SLOPE_FACTOR) -
  91. (CAL_DEGC_PT1 *
  92. priv->sensor[i].slope);
  93. dev_dbg(priv->dev, "%s: offset:%d\n", __func__,
  94. priv->sensor[i].offset);
  95. }
  96. }
  97. static inline u32 degc_to_code(int degc, const struct tsens_sensor *s)
  98. {
  99. u64 code = div_u64(((u64)degc * s->slope + s->offset), SLOPE_FACTOR);
  100. pr_debug("%s: raw_code: 0x%llx, degc:%d\n", __func__, code, degc);
  101. return clamp_val(code, THRESHOLD_MIN_ADC_CODE, THRESHOLD_MAX_ADC_CODE);
  102. }
  103. static inline int code_to_degc(u32 adc_code, const struct tsens_sensor *s)
  104. {
  105. int degc, num, den;
  106. num = (adc_code * SLOPE_FACTOR) - s->offset;
  107. den = s->slope;
  108. if (num > 0)
  109. degc = num + (den / 2);
  110. else if (num < 0)
  111. degc = num - (den / 2);
  112. else
  113. degc = num;
  114. degc /= den;
  115. return degc;
  116. }
  117. /**
  118. * tsens_hw_to_mC - Return sign-extended temperature in mCelsius.
  119. * @s: Pointer to sensor struct
  120. * @field: Index into regmap_field array pointing to temperature data
  121. *
  122. * This function handles temperature returned in ADC code or deciCelsius
  123. * depending on IP version.
  124. *
  125. * Return: Temperature in milliCelsius on success, a negative errno will
  126. * be returned in error cases
  127. */
  128. static int tsens_hw_to_mC(const struct tsens_sensor *s, int field)
  129. {
  130. struct tsens_priv *priv = s->priv;
  131. u32 resolution;
  132. u32 temp = 0;
  133. int ret;
  134. resolution = priv->fields[LAST_TEMP_0].msb -
  135. priv->fields[LAST_TEMP_0].lsb;
  136. ret = regmap_field_read(priv->rf[field], &temp);
  137. if (ret)
  138. return ret;
  139. /* Convert temperature from ADC code to milliCelsius */
  140. if (priv->feat->adc)
  141. return code_to_degc(temp, s) * 1000;
  142. /* deciCelsius -> milliCelsius along with sign extension */
  143. return sign_extend32(temp, resolution) * 100;
  144. }
  145. /**
  146. * tsens_mC_to_hw - Convert temperature to hardware register value
  147. * @s: Pointer to sensor struct
  148. * @temp: temperature in milliCelsius to be programmed to hardware
  149. *
  150. * This function outputs the value to be written to hardware in ADC code
  151. * or deciCelsius depending on IP version.
  152. *
  153. * Return: ADC code or temperature in deciCelsius.
  154. */
  155. static int tsens_mC_to_hw(const struct tsens_sensor *s, int temp)
  156. {
  157. struct tsens_priv *priv = s->priv;
  158. /* milliC to adc code */
  159. if (priv->feat->adc)
  160. return degc_to_code(temp / 1000, s);
  161. /* milliC to deciC */
  162. return temp / 100;
  163. }
  164. static inline enum tsens_ver tsens_version(struct tsens_priv *priv)
  165. {
  166. return priv->feat->ver_major;
  167. }
  168. static void tsens_set_interrupt_v1(struct tsens_priv *priv, u32 hw_id,
  169. enum tsens_irq_type irq_type, bool enable)
  170. {
  171. u32 index = 0;
  172. switch (irq_type) {
  173. case UPPER:
  174. index = UP_INT_CLEAR_0 + hw_id;
  175. break;
  176. case LOWER:
  177. index = LOW_INT_CLEAR_0 + hw_id;
  178. break;
  179. case CRITICAL:
  180. /* No critical interrupts before v2 */
  181. return;
  182. }
  183. regmap_field_write(priv->rf[index], enable ? 0 : 1);
  184. }
  185. static void tsens_set_interrupt_v2(struct tsens_priv *priv, u32 hw_id,
  186. enum tsens_irq_type irq_type, bool enable)
  187. {
  188. u32 index_mask = 0, index_clear = 0;
  189. /*
  190. * To enable the interrupt flag for a sensor:
  191. * - clear the mask bit
  192. * To disable the interrupt flag for a sensor:
  193. * - Mask further interrupts for this sensor
  194. * - Write 1 followed by 0 to clear the interrupt
  195. */
  196. switch (irq_type) {
  197. case UPPER:
  198. index_mask = UP_INT_MASK_0 + hw_id;
  199. index_clear = UP_INT_CLEAR_0 + hw_id;
  200. break;
  201. case LOWER:
  202. index_mask = LOW_INT_MASK_0 + hw_id;
  203. index_clear = LOW_INT_CLEAR_0 + hw_id;
  204. break;
  205. case CRITICAL:
  206. index_mask = CRIT_INT_MASK_0 + hw_id;
  207. index_clear = CRIT_INT_CLEAR_0 + hw_id;
  208. break;
  209. }
  210. if (enable) {
  211. regmap_field_write(priv->rf[index_mask], 0);
  212. } else {
  213. regmap_field_write(priv->rf[index_mask], 1);
  214. regmap_field_write(priv->rf[index_clear], 1);
  215. regmap_field_write(priv->rf[index_clear], 0);
  216. }
  217. }
  218. /**
  219. * tsens_set_interrupt - Set state of an interrupt
  220. * @priv: Pointer to tsens controller private data
  221. * @hw_id: Hardware ID aka. sensor number
  222. * @irq_type: irq_type from enum tsens_irq_type
  223. * @enable: false = disable, true = enable
  224. *
  225. * Call IP-specific function to set state of an interrupt
  226. *
  227. * Return: void
  228. */
  229. static void tsens_set_interrupt(struct tsens_priv *priv, u32 hw_id,
  230. enum tsens_irq_type irq_type, bool enable)
  231. {
  232. dev_dbg(priv->dev, "[%u] %s: %s -> %s\n", hw_id, __func__,
  233. irq_type ? ((irq_type == 1) ? "UP" : "CRITICAL") : "LOW",
  234. enable ? "en" : "dis");
  235. if (tsens_version(priv) > VER_1_X)
  236. tsens_set_interrupt_v2(priv, hw_id, irq_type, enable);
  237. else
  238. tsens_set_interrupt_v1(priv, hw_id, irq_type, enable);
  239. }
  240. /**
  241. * tsens_threshold_violated - Check if a sensor temperature violated a preset threshold
  242. * @priv: Pointer to tsens controller private data
  243. * @hw_id: Hardware ID aka. sensor number
  244. * @d: Pointer to irq state data
  245. *
  246. * Return: 0 if threshold was not violated, 1 if it was violated and negative
  247. * errno in case of errors
  248. */
  249. static int tsens_threshold_violated(struct tsens_priv *priv, u32 hw_id,
  250. struct tsens_irq_data *d)
  251. {
  252. int ret;
  253. ret = regmap_field_read(priv->rf[UPPER_STATUS_0 + hw_id], &d->up_viol);
  254. if (ret)
  255. return ret;
  256. ret = regmap_field_read(priv->rf[LOWER_STATUS_0 + hw_id], &d->low_viol);
  257. if (ret)
  258. return ret;
  259. if (priv->feat->crit_int) {
  260. ret = regmap_field_read(priv->rf[CRITICAL_STATUS_0 + hw_id],
  261. &d->crit_viol);
  262. if (ret)
  263. return ret;
  264. }
  265. if (d->up_viol || d->low_viol || d->crit_viol)
  266. return 1;
  267. return 0;
  268. }
  269. static int tsens_read_irq_state(struct tsens_priv *priv, u32 hw_id,
  270. const struct tsens_sensor *s,
  271. struct tsens_irq_data *d)
  272. {
  273. int ret;
  274. ret = regmap_field_read(priv->rf[UP_INT_CLEAR_0 + hw_id], &d->up_irq_clear);
  275. if (ret)
  276. return ret;
  277. ret = regmap_field_read(priv->rf[LOW_INT_CLEAR_0 + hw_id], &d->low_irq_clear);
  278. if (ret)
  279. return ret;
  280. if (tsens_version(priv) > VER_1_X) {
  281. ret = regmap_field_read(priv->rf[UP_INT_MASK_0 + hw_id], &d->up_irq_mask);
  282. if (ret)
  283. return ret;
  284. ret = regmap_field_read(priv->rf[LOW_INT_MASK_0 + hw_id], &d->low_irq_mask);
  285. if (ret)
  286. return ret;
  287. ret = regmap_field_read(priv->rf[CRIT_INT_CLEAR_0 + hw_id],
  288. &d->crit_irq_clear);
  289. if (ret)
  290. return ret;
  291. ret = regmap_field_read(priv->rf[CRIT_INT_MASK_0 + hw_id],
  292. &d->crit_irq_mask);
  293. if (ret)
  294. return ret;
  295. d->crit_thresh = tsens_hw_to_mC(s, CRIT_THRESH_0 + hw_id);
  296. } else {
  297. /* No mask register on older TSENS */
  298. d->up_irq_mask = 0;
  299. d->low_irq_mask = 0;
  300. d->crit_irq_clear = 0;
  301. d->crit_irq_mask = 0;
  302. d->crit_thresh = 0;
  303. }
  304. d->up_thresh = tsens_hw_to_mC(s, UP_THRESH_0 + hw_id);
  305. d->low_thresh = tsens_hw_to_mC(s, LOW_THRESH_0 + hw_id);
  306. dev_dbg(priv->dev, "[%u] %s%s: status(%u|%u|%u) | clr(%u|%u|%u) | mask(%u|%u|%u)\n",
  307. hw_id, __func__,
  308. (d->up_viol || d->low_viol || d->crit_viol) ? "(V)" : "",
  309. d->low_viol, d->up_viol, d->crit_viol,
  310. d->low_irq_clear, d->up_irq_clear, d->crit_irq_clear,
  311. d->low_irq_mask, d->up_irq_mask, d->crit_irq_mask);
  312. dev_dbg(priv->dev, "[%u] %s%s: thresh: (%d:%d:%d)\n", hw_id, __func__,
  313. (d->up_viol || d->low_viol || d->crit_viol) ? "(V)" : "",
  314. d->low_thresh, d->up_thresh, d->crit_thresh);
  315. return 0;
  316. }
  317. static inline u32 masked_irq(u32 hw_id, u32 mask, enum tsens_ver ver)
  318. {
  319. if (ver > VER_1_X)
  320. return mask & (1 << hw_id);
  321. /* v1, v0.1 don't have a irq mask register */
  322. return 0;
  323. }
  324. /**
  325. * tsens_critical_irq_thread() - Threaded handler for critical interrupts
  326. * @irq: irq number
  327. * @data: tsens controller private data
  328. *
  329. * Check FSM watchdog bark status and clear if needed.
  330. * Check all sensors to find ones that violated their critical threshold limits.
  331. * Clear and then re-enable the interrupt.
  332. *
  333. * The level-triggered interrupt might deassert if the temperature returned to
  334. * within the threshold limits by the time the handler got scheduled. We
  335. * consider the irq to have been handled in that case.
  336. *
  337. * Return: IRQ_HANDLED
  338. */
  339. static irqreturn_t tsens_critical_irq_thread(int irq, void *data)
  340. {
  341. struct tsens_priv *priv = data;
  342. struct tsens_irq_data d;
  343. int temp, ret, i;
  344. u32 wdog_status, wdog_count;
  345. if (priv->feat->has_watchdog) {
  346. ret = regmap_field_read(priv->rf[WDOG_BARK_STATUS],
  347. &wdog_status);
  348. if (ret)
  349. return ret;
  350. if (wdog_status) {
  351. /* Clear WDOG interrupt */
  352. regmap_field_write(priv->rf[WDOG_BARK_CLEAR], 1);
  353. regmap_field_write(priv->rf[WDOG_BARK_CLEAR], 0);
  354. ret = regmap_field_read(priv->rf[WDOG_BARK_COUNT],
  355. &wdog_count);
  356. if (ret)
  357. return ret;
  358. if (wdog_count)
  359. dev_dbg(priv->dev, "%s: watchdog count: %d\n",
  360. __func__, wdog_count);
  361. /* Fall through to handle critical interrupts if any */
  362. }
  363. }
  364. for (i = 0; i < priv->num_sensors; i++) {
  365. const struct tsens_sensor *s = &priv->sensor[i];
  366. u32 hw_id = s->hw_id;
  367. if (!s->tzd)
  368. continue;
  369. if (!tsens_threshold_violated(priv, hw_id, &d))
  370. continue;
  371. ret = get_temp_tsens_valid(s, &temp);
  372. if (ret) {
  373. dev_err(priv->dev, "[%u] %s: error reading sensor\n",
  374. hw_id, __func__);
  375. continue;
  376. }
  377. tsens_read_irq_state(priv, hw_id, s, &d);
  378. if (d.crit_viol &&
  379. !masked_irq(hw_id, d.crit_irq_mask, tsens_version(priv))) {
  380. /* Mask critical interrupts, unused on Linux */
  381. tsens_set_interrupt(priv, hw_id, CRITICAL, false);
  382. }
  383. }
  384. return IRQ_HANDLED;
  385. }
  386. /**
  387. * tsens_irq_thread - Threaded interrupt handler for uplow interrupts
  388. * @irq: irq number
  389. * @data: tsens controller private data
  390. *
  391. * Check all sensors to find ones that violated their threshold limits. If the
  392. * temperature is still outside the limits, call thermal_zone_device_update() to
  393. * update the thresholds, else re-enable the interrupts.
  394. *
  395. * The level-triggered interrupt might deassert if the temperature returned to
  396. * within the threshold limits by the time the handler got scheduled. We
  397. * consider the irq to have been handled in that case.
  398. *
  399. * Return: IRQ_HANDLED
  400. */
  401. static irqreturn_t tsens_irq_thread(int irq, void *data)
  402. {
  403. struct tsens_priv *priv = data;
  404. struct tsens_irq_data d;
  405. bool enable = true, disable = false;
  406. unsigned long flags;
  407. int temp, ret, i;
  408. for (i = 0; i < priv->num_sensors; i++) {
  409. bool trigger = false;
  410. const struct tsens_sensor *s = &priv->sensor[i];
  411. u32 hw_id = s->hw_id;
  412. if (!s->tzd)
  413. continue;
  414. if (!tsens_threshold_violated(priv, hw_id, &d))
  415. continue;
  416. ret = get_temp_tsens_valid(s, &temp);
  417. if (ret) {
  418. dev_err(priv->dev, "[%u] %s: error reading sensor\n",
  419. hw_id, __func__);
  420. continue;
  421. }
  422. spin_lock_irqsave(&priv->ul_lock, flags);
  423. tsens_read_irq_state(priv, hw_id, s, &d);
  424. if (d.up_viol &&
  425. !masked_irq(hw_id, d.up_irq_mask, tsens_version(priv))) {
  426. tsens_set_interrupt(priv, hw_id, UPPER, disable);
  427. if (d.up_thresh > temp) {
  428. dev_dbg(priv->dev, "[%u] %s: re-arm upper\n",
  429. hw_id, __func__);
  430. tsens_set_interrupt(priv, hw_id, UPPER, enable);
  431. } else {
  432. trigger = true;
  433. /* Keep irq masked */
  434. }
  435. } else if (d.low_viol &&
  436. !masked_irq(hw_id, d.low_irq_mask, tsens_version(priv))) {
  437. tsens_set_interrupt(priv, hw_id, LOWER, disable);
  438. if (d.low_thresh < temp) {
  439. dev_dbg(priv->dev, "[%u] %s: re-arm low\n",
  440. hw_id, __func__);
  441. tsens_set_interrupt(priv, hw_id, LOWER, enable);
  442. } else {
  443. trigger = true;
  444. /* Keep irq masked */
  445. }
  446. }
  447. spin_unlock_irqrestore(&priv->ul_lock, flags);
  448. if (trigger) {
  449. dev_dbg(priv->dev, "[%u] %s: TZ update trigger (%d mC)\n",
  450. hw_id, __func__, temp);
  451. thermal_zone_device_update(s->tzd,
  452. THERMAL_EVENT_UNSPECIFIED);
  453. } else {
  454. dev_dbg(priv->dev, "[%u] %s: no violation: %d\n",
  455. hw_id, __func__, temp);
  456. }
  457. }
  458. return IRQ_HANDLED;
  459. }
  460. static int tsens_set_trips(void *_sensor, int low, int high)
  461. {
  462. struct tsens_sensor *s = _sensor;
  463. struct tsens_priv *priv = s->priv;
  464. struct device *dev = priv->dev;
  465. struct tsens_irq_data d;
  466. unsigned long flags;
  467. int high_val, low_val, cl_high, cl_low;
  468. u32 hw_id = s->hw_id;
  469. dev_dbg(dev, "[%u] %s: proposed thresholds: (%d:%d)\n",
  470. hw_id, __func__, low, high);
  471. cl_high = clamp_val(high, -40000, 120000);
  472. cl_low = clamp_val(low, -40000, 120000);
  473. high_val = tsens_mC_to_hw(s, cl_high);
  474. low_val = tsens_mC_to_hw(s, cl_low);
  475. spin_lock_irqsave(&priv->ul_lock, flags);
  476. tsens_read_irq_state(priv, hw_id, s, &d);
  477. /* Write the new thresholds and clear the status */
  478. regmap_field_write(priv->rf[LOW_THRESH_0 + hw_id], low_val);
  479. regmap_field_write(priv->rf[UP_THRESH_0 + hw_id], high_val);
  480. tsens_set_interrupt(priv, hw_id, LOWER, true);
  481. tsens_set_interrupt(priv, hw_id, UPPER, true);
  482. spin_unlock_irqrestore(&priv->ul_lock, flags);
  483. dev_dbg(dev, "[%u] %s: (%d:%d)->(%d:%d)\n",
  484. hw_id, __func__, d.low_thresh, d.up_thresh, cl_low, cl_high);
  485. return 0;
  486. }
  487. static int tsens_enable_irq(struct tsens_priv *priv)
  488. {
  489. int ret;
  490. int val = tsens_version(priv) > VER_1_X ? 7 : 1;
  491. ret = regmap_field_write(priv->rf[INT_EN], val);
  492. if (ret < 0)
  493. dev_err(priv->dev, "%s: failed to enable interrupts\n",
  494. __func__);
  495. return ret;
  496. }
  497. static void tsens_disable_irq(struct tsens_priv *priv)
  498. {
  499. regmap_field_write(priv->rf[INT_EN], 0);
  500. }
  501. int get_temp_tsens_valid(const struct tsens_sensor *s, int *temp)
  502. {
  503. struct tsens_priv *priv = s->priv;
  504. int hw_id = s->hw_id;
  505. u32 temp_idx = LAST_TEMP_0 + hw_id;
  506. u32 valid_idx = VALID_0 + hw_id;
  507. u32 valid;
  508. int ret;
  509. ret = regmap_field_read(priv->rf[valid_idx], &valid);
  510. if (ret)
  511. return ret;
  512. while (!valid) {
  513. /* Valid bit is 0 for 6 AHB clock cycles.
  514. * At 19.2MHz, 1 AHB clock is ~60ns.
  515. * We should enter this loop very, very rarely.
  516. */
  517. ndelay(400);
  518. ret = regmap_field_read(priv->rf[valid_idx], &valid);
  519. if (ret)
  520. return ret;
  521. }
  522. /* Valid bit is set, OK to read the temperature */
  523. *temp = tsens_hw_to_mC(s, temp_idx);
  524. return 0;
  525. }
  526. int get_temp_common(const struct tsens_sensor *s, int *temp)
  527. {
  528. struct tsens_priv *priv = s->priv;
  529. int hw_id = s->hw_id;
  530. int last_temp = 0, ret;
  531. ret = regmap_field_read(priv->rf[LAST_TEMP_0 + hw_id], &last_temp);
  532. if (ret)
  533. return ret;
  534. *temp = code_to_degc(last_temp, s) * 1000;
  535. return 0;
  536. }
  537. #ifdef CONFIG_DEBUG_FS
  538. static int dbg_sensors_show(struct seq_file *s, void *data)
  539. {
  540. struct platform_device *pdev = s->private;
  541. struct tsens_priv *priv = platform_get_drvdata(pdev);
  542. int i;
  543. seq_printf(s, "max: %2d\nnum: %2d\n\n",
  544. priv->feat->max_sensors, priv->num_sensors);
  545. seq_puts(s, " id slope offset\n--------------------------\n");
  546. for (i = 0; i < priv->num_sensors; i++) {
  547. seq_printf(s, "%8d %8d %8d\n", priv->sensor[i].hw_id,
  548. priv->sensor[i].slope, priv->sensor[i].offset);
  549. }
  550. return 0;
  551. }
  552. static int dbg_version_show(struct seq_file *s, void *data)
  553. {
  554. struct platform_device *pdev = s->private;
  555. struct tsens_priv *priv = platform_get_drvdata(pdev);
  556. u32 maj_ver, min_ver, step_ver;
  557. int ret;
  558. if (tsens_version(priv) > VER_0_1) {
  559. ret = regmap_field_read(priv->rf[VER_MAJOR], &maj_ver);
  560. if (ret)
  561. return ret;
  562. ret = regmap_field_read(priv->rf[VER_MINOR], &min_ver);
  563. if (ret)
  564. return ret;
  565. ret = regmap_field_read(priv->rf[VER_STEP], &step_ver);
  566. if (ret)
  567. return ret;
  568. seq_printf(s, "%d.%d.%d\n", maj_ver, min_ver, step_ver);
  569. } else {
  570. seq_puts(s, "0.1.0\n");
  571. }
  572. return 0;
  573. }
  574. DEFINE_SHOW_ATTRIBUTE(dbg_version);
  575. DEFINE_SHOW_ATTRIBUTE(dbg_sensors);
  576. static void tsens_debug_init(struct platform_device *pdev)
  577. {
  578. struct tsens_priv *priv = platform_get_drvdata(pdev);
  579. struct dentry *root, *file;
  580. root = debugfs_lookup("tsens", NULL);
  581. if (!root)
  582. priv->debug_root = debugfs_create_dir("tsens", NULL);
  583. else
  584. priv->debug_root = root;
  585. file = debugfs_lookup("version", priv->debug_root);
  586. if (!file)
  587. debugfs_create_file("version", 0444, priv->debug_root,
  588. pdev, &dbg_version_fops);
  589. /* A directory for each instance of the TSENS IP */
  590. priv->debug = debugfs_create_dir(dev_name(&pdev->dev), priv->debug_root);
  591. debugfs_create_file("sensors", 0444, priv->debug, pdev, &dbg_sensors_fops);
  592. }
  593. #else
  594. static inline void tsens_debug_init(struct platform_device *pdev) {}
  595. #endif
  596. static const struct regmap_config tsens_config = {
  597. .name = "tm",
  598. .reg_bits = 32,
  599. .val_bits = 32,
  600. .reg_stride = 4,
  601. };
  602. static const struct regmap_config tsens_srot_config = {
  603. .name = "srot",
  604. .reg_bits = 32,
  605. .val_bits = 32,
  606. .reg_stride = 4,
  607. };
  608. int __init init_common(struct tsens_priv *priv)
  609. {
  610. void __iomem *tm_base, *srot_base;
  611. struct device *dev = priv->dev;
  612. u32 ver_minor;
  613. struct resource *res;
  614. u32 enabled;
  615. int ret, i, j;
  616. struct platform_device *op = of_find_device_by_node(priv->dev->of_node);
  617. if (!op)
  618. return -EINVAL;
  619. if (op->num_resources > 1) {
  620. /* DT with separate SROT and TM address space */
  621. priv->tm_offset = 0;
  622. res = platform_get_resource(op, IORESOURCE_MEM, 1);
  623. srot_base = devm_ioremap_resource(dev, res);
  624. if (IS_ERR(srot_base)) {
  625. ret = PTR_ERR(srot_base);
  626. goto err_put_device;
  627. }
  628. priv->srot_map = devm_regmap_init_mmio(dev, srot_base,
  629. &tsens_srot_config);
  630. if (IS_ERR(priv->srot_map)) {
  631. ret = PTR_ERR(priv->srot_map);
  632. goto err_put_device;
  633. }
  634. } else {
  635. /* old DTs where SROT and TM were in a contiguous 2K block */
  636. priv->tm_offset = 0x1000;
  637. }
  638. res = platform_get_resource(op, IORESOURCE_MEM, 0);
  639. tm_base = devm_ioremap_resource(dev, res);
  640. if (IS_ERR(tm_base)) {
  641. ret = PTR_ERR(tm_base);
  642. goto err_put_device;
  643. }
  644. priv->tm_map = devm_regmap_init_mmio(dev, tm_base, &tsens_config);
  645. if (IS_ERR(priv->tm_map)) {
  646. ret = PTR_ERR(priv->tm_map);
  647. goto err_put_device;
  648. }
  649. if (tsens_version(priv) > VER_0_1) {
  650. for (i = VER_MAJOR; i <= VER_STEP; i++) {
  651. priv->rf[i] = devm_regmap_field_alloc(dev, priv->srot_map,
  652. priv->fields[i]);
  653. if (IS_ERR(priv->rf[i])) {
  654. ret = PTR_ERR(priv->rf[i]);
  655. goto err_put_device;
  656. }
  657. }
  658. ret = regmap_field_read(priv->rf[VER_MINOR], &ver_minor);
  659. if (ret)
  660. goto err_put_device;
  661. }
  662. priv->rf[TSENS_EN] = devm_regmap_field_alloc(dev, priv->srot_map,
  663. priv->fields[TSENS_EN]);
  664. if (IS_ERR(priv->rf[TSENS_EN])) {
  665. ret = PTR_ERR(priv->rf[TSENS_EN]);
  666. goto err_put_device;
  667. }
  668. ret = regmap_field_read(priv->rf[TSENS_EN], &enabled);
  669. if (ret)
  670. goto err_put_device;
  671. if (!enabled) {
  672. dev_err(dev, "%s: device not enabled\n", __func__);
  673. ret = -ENODEV;
  674. goto err_put_device;
  675. }
  676. priv->rf[SENSOR_EN] = devm_regmap_field_alloc(dev, priv->srot_map,
  677. priv->fields[SENSOR_EN]);
  678. if (IS_ERR(priv->rf[SENSOR_EN])) {
  679. ret = PTR_ERR(priv->rf[SENSOR_EN]);
  680. goto err_put_device;
  681. }
  682. priv->rf[INT_EN] = devm_regmap_field_alloc(dev, priv->tm_map,
  683. priv->fields[INT_EN]);
  684. if (IS_ERR(priv->rf[INT_EN])) {
  685. ret = PTR_ERR(priv->rf[INT_EN]);
  686. goto err_put_device;
  687. }
  688. /* This loop might need changes if enum regfield_ids is reordered */
  689. for (j = LAST_TEMP_0; j <= UP_THRESH_15; j += 16) {
  690. for (i = 0; i < priv->feat->max_sensors; i++) {
  691. int idx = j + i;
  692. priv->rf[idx] = devm_regmap_field_alloc(dev,
  693. priv->tm_map,
  694. priv->fields[idx]);
  695. if (IS_ERR(priv->rf[idx])) {
  696. ret = PTR_ERR(priv->rf[idx]);
  697. goto err_put_device;
  698. }
  699. }
  700. }
  701. if (priv->feat->crit_int) {
  702. /* Loop might need changes if enum regfield_ids is reordered */
  703. for (j = CRITICAL_STATUS_0; j <= CRIT_THRESH_15; j += 16) {
  704. for (i = 0; i < priv->feat->max_sensors; i++) {
  705. int idx = j + i;
  706. priv->rf[idx] =
  707. devm_regmap_field_alloc(dev,
  708. priv->tm_map,
  709. priv->fields[idx]);
  710. if (IS_ERR(priv->rf[idx])) {
  711. ret = PTR_ERR(priv->rf[idx]);
  712. goto err_put_device;
  713. }
  714. }
  715. }
  716. }
  717. if (tsens_version(priv) > VER_1_X && ver_minor > 2) {
  718. /* Watchdog is present only on v2.3+ */
  719. priv->feat->has_watchdog = 1;
  720. for (i = WDOG_BARK_STATUS; i <= CC_MON_MASK; i++) {
  721. priv->rf[i] = devm_regmap_field_alloc(dev, priv->tm_map,
  722. priv->fields[i]);
  723. if (IS_ERR(priv->rf[i])) {
  724. ret = PTR_ERR(priv->rf[i]);
  725. goto err_put_device;
  726. }
  727. }
  728. /*
  729. * Watchdog is already enabled, unmask the bark.
  730. * Disable cycle completion monitoring
  731. */
  732. regmap_field_write(priv->rf[WDOG_BARK_MASK], 0);
  733. regmap_field_write(priv->rf[CC_MON_MASK], 1);
  734. }
  735. spin_lock_init(&priv->ul_lock);
  736. tsens_enable_irq(priv);
  737. tsens_debug_init(op);
  738. err_put_device:
  739. put_device(&op->dev);
  740. return ret;
  741. }
  742. static int tsens_get_temp(void *data, int *temp)
  743. {
  744. struct tsens_sensor *s = data;
  745. struct tsens_priv *priv = s->priv;
  746. return priv->ops->get_temp(s, temp);
  747. }
  748. static int tsens_get_trend(void *data, int trip, enum thermal_trend *trend)
  749. {
  750. struct tsens_sensor *s = data;
  751. struct tsens_priv *priv = s->priv;
  752. if (priv->ops->get_trend)
  753. return priv->ops->get_trend(s, trend);
  754. return -ENOTSUPP;
  755. }
  756. static int __maybe_unused tsens_suspend(struct device *dev)
  757. {
  758. struct tsens_priv *priv = dev_get_drvdata(dev);
  759. if (priv->ops && priv->ops->suspend)
  760. return priv->ops->suspend(priv);
  761. return 0;
  762. }
  763. static int __maybe_unused tsens_resume(struct device *dev)
  764. {
  765. struct tsens_priv *priv = dev_get_drvdata(dev);
  766. if (priv->ops && priv->ops->resume)
  767. return priv->ops->resume(priv);
  768. return 0;
  769. }
  770. static SIMPLE_DEV_PM_OPS(tsens_pm_ops, tsens_suspend, tsens_resume);
  771. static const struct of_device_id tsens_table[] = {
  772. {
  773. .compatible = "qcom,msm8916-tsens",
  774. .data = &data_8916,
  775. }, {
  776. .compatible = "qcom,msm8939-tsens",
  777. .data = &data_8939,
  778. }, {
  779. .compatible = "qcom,msm8974-tsens",
  780. .data = &data_8974,
  781. }, {
  782. .compatible = "qcom,msm8976-tsens",
  783. .data = &data_8976,
  784. }, {
  785. .compatible = "qcom,msm8996-tsens",
  786. .data = &data_8996,
  787. }, {
  788. .compatible = "qcom,tsens-v1",
  789. .data = &data_tsens_v1,
  790. }, {
  791. .compatible = "qcom,tsens-v2",
  792. .data = &data_tsens_v2,
  793. },
  794. {}
  795. };
  796. MODULE_DEVICE_TABLE(of, tsens_table);
  797. static const struct thermal_zone_of_device_ops tsens_of_ops = {
  798. .get_temp = tsens_get_temp,
  799. .get_trend = tsens_get_trend,
  800. .set_trips = tsens_set_trips,
  801. };
  802. static int tsens_register_irq(struct tsens_priv *priv, char *irqname,
  803. irq_handler_t thread_fn)
  804. {
  805. struct platform_device *pdev;
  806. int ret, irq;
  807. pdev = of_find_device_by_node(priv->dev->of_node);
  808. if (!pdev)
  809. return -ENODEV;
  810. irq = platform_get_irq_byname(pdev, irqname);
  811. if (irq < 0) {
  812. ret = irq;
  813. /* For old DTs with no IRQ defined */
  814. if (irq == -ENXIO)
  815. ret = 0;
  816. } else {
  817. ret = devm_request_threaded_irq(&pdev->dev, irq,
  818. NULL, thread_fn,
  819. IRQF_ONESHOT,
  820. dev_name(&pdev->dev), priv);
  821. if (ret)
  822. dev_err(&pdev->dev, "%s: failed to get irq\n",
  823. __func__);
  824. else
  825. enable_irq_wake(irq);
  826. }
  827. put_device(&pdev->dev);
  828. return ret;
  829. }
  830. static int tsens_register(struct tsens_priv *priv)
  831. {
  832. int i, ret;
  833. struct thermal_zone_device *tzd;
  834. for (i = 0; i < priv->num_sensors; i++) {
  835. priv->sensor[i].priv = priv;
  836. tzd = devm_thermal_zone_of_sensor_register(priv->dev, priv->sensor[i].hw_id,
  837. &priv->sensor[i],
  838. &tsens_of_ops);
  839. if (IS_ERR(tzd))
  840. continue;
  841. priv->sensor[i].tzd = tzd;
  842. if (priv->ops->enable)
  843. priv->ops->enable(priv, i);
  844. }
  845. ret = tsens_register_irq(priv, "uplow", tsens_irq_thread);
  846. if (ret < 0)
  847. return ret;
  848. if (priv->feat->crit_int)
  849. ret = tsens_register_irq(priv, "critical",
  850. tsens_critical_irq_thread);
  851. return ret;
  852. }
  853. static int tsens_probe(struct platform_device *pdev)
  854. {
  855. int ret, i;
  856. struct device *dev;
  857. struct device_node *np;
  858. struct tsens_priv *priv;
  859. const struct tsens_plat_data *data;
  860. const struct of_device_id *id;
  861. u32 num_sensors;
  862. if (pdev->dev.of_node)
  863. dev = &pdev->dev;
  864. else
  865. dev = pdev->dev.parent;
  866. np = dev->of_node;
  867. id = of_match_node(tsens_table, np);
  868. if (id)
  869. data = id->data;
  870. else
  871. data = &data_8960;
  872. num_sensors = data->num_sensors;
  873. if (np)
  874. of_property_read_u32(np, "#qcom,sensors", &num_sensors);
  875. if (num_sensors <= 0) {
  876. dev_err(dev, "%s: invalid number of sensors\n", __func__);
  877. return -EINVAL;
  878. }
  879. priv = devm_kzalloc(dev,
  880. struct_size(priv, sensor, num_sensors),
  881. GFP_KERNEL);
  882. if (!priv)
  883. return -ENOMEM;
  884. priv->dev = dev;
  885. priv->num_sensors = num_sensors;
  886. priv->ops = data->ops;
  887. for (i = 0; i < priv->num_sensors; i++) {
  888. if (data->hw_ids)
  889. priv->sensor[i].hw_id = data->hw_ids[i];
  890. else
  891. priv->sensor[i].hw_id = i;
  892. }
  893. priv->feat = data->feat;
  894. priv->fields = data->fields;
  895. platform_set_drvdata(pdev, priv);
  896. if (!priv->ops || !priv->ops->init || !priv->ops->get_temp)
  897. return -EINVAL;
  898. ret = priv->ops->init(priv);
  899. if (ret < 0) {
  900. dev_err(dev, "%s: init failed\n", __func__);
  901. return ret;
  902. }
  903. if (priv->ops->calibrate) {
  904. ret = priv->ops->calibrate(priv);
  905. if (ret < 0) {
  906. if (ret != -EPROBE_DEFER)
  907. dev_err(dev, "%s: calibration failed\n", __func__);
  908. return ret;
  909. }
  910. }
  911. return tsens_register(priv);
  912. }
  913. static int tsens_remove(struct platform_device *pdev)
  914. {
  915. struct tsens_priv *priv = platform_get_drvdata(pdev);
  916. debugfs_remove_recursive(priv->debug_root);
  917. tsens_disable_irq(priv);
  918. if (priv->ops->disable)
  919. priv->ops->disable(priv);
  920. return 0;
  921. }
  922. static struct platform_driver tsens_driver = {
  923. .probe = tsens_probe,
  924. .remove = tsens_remove,
  925. .driver = {
  926. .name = "qcom-tsens",
  927. .pm = &tsens_pm_ops,
  928. .of_match_table = tsens_table,
  929. },
  930. };
  931. module_platform_driver(tsens_driver);
  932. MODULE_LICENSE("GPL v2");
  933. MODULE_DESCRIPTION("QCOM Temperature Sensor driver");
  934. MODULE_ALIAS("platform:qcom-tsens");