mtk_thermal.c 30 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015 MediaTek Inc.
  4. * Author: Hanyi Wu <hanyi.wu@mediatek.com>
  5. * Sascha Hauer <s.hauer@pengutronix.de>
  6. * Dawei Chien <dawei.chien@mediatek.com>
  7. * Louis Yu <louis.yu@mediatek.com>
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/delay.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/kernel.h>
  13. #include <linux/module.h>
  14. #include <linux/nvmem-consumer.h>
  15. #include <linux/of.h>
  16. #include <linux/of_address.h>
  17. #include <linux/of_device.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/slab.h>
  20. #include <linux/io.h>
  21. #include <linux/thermal.h>
  22. #include <linux/reset.h>
  23. #include <linux/types.h>
  24. /* AUXADC Registers */
  25. #define AUXADC_CON1_SET_V 0x008
  26. #define AUXADC_CON1_CLR_V 0x00c
  27. #define AUXADC_CON2_V 0x010
  28. #define AUXADC_DATA(channel) (0x14 + (channel) * 4)
  29. #define APMIXED_SYS_TS_CON1 0x604
  30. /* Thermal Controller Registers */
  31. #define TEMP_MONCTL0 0x000
  32. #define TEMP_MONCTL1 0x004
  33. #define TEMP_MONCTL2 0x008
  34. #define TEMP_MONIDET0 0x014
  35. #define TEMP_MONIDET1 0x018
  36. #define TEMP_MSRCTL0 0x038
  37. #define TEMP_MSRCTL1 0x03c
  38. #define TEMP_AHBPOLL 0x040
  39. #define TEMP_AHBTO 0x044
  40. #define TEMP_ADCPNP0 0x048
  41. #define TEMP_ADCPNP1 0x04c
  42. #define TEMP_ADCPNP2 0x050
  43. #define TEMP_ADCPNP3 0x0b4
  44. #define TEMP_ADCMUX 0x054
  45. #define TEMP_ADCEN 0x060
  46. #define TEMP_PNPMUXADDR 0x064
  47. #define TEMP_ADCMUXADDR 0x068
  48. #define TEMP_ADCENADDR 0x074
  49. #define TEMP_ADCVALIDADDR 0x078
  50. #define TEMP_ADCVOLTADDR 0x07c
  51. #define TEMP_RDCTRL 0x080
  52. #define TEMP_ADCVALIDMASK 0x084
  53. #define TEMP_ADCVOLTAGESHIFT 0x088
  54. #define TEMP_ADCWRITECTRL 0x08c
  55. #define TEMP_MSR0 0x090
  56. #define TEMP_MSR1 0x094
  57. #define TEMP_MSR2 0x098
  58. #define TEMP_MSR3 0x0B8
  59. #define TEMP_SPARE0 0x0f0
  60. #define TEMP_ADCPNP0_1 0x148
  61. #define TEMP_ADCPNP1_1 0x14c
  62. #define TEMP_ADCPNP2_1 0x150
  63. #define TEMP_MSR0_1 0x190
  64. #define TEMP_MSR1_1 0x194
  65. #define TEMP_MSR2_1 0x198
  66. #define TEMP_ADCPNP3_1 0x1b4
  67. #define TEMP_MSR3_1 0x1B8
  68. #define PTPCORESEL 0x400
  69. #define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff)
  70. #define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff) << 16)
  71. #define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff)
  72. #define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x)
  73. #define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0)
  74. #define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1)
  75. #define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5)
  76. #define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit)
  77. /* MT8173 thermal sensors */
  78. #define MT8173_TS1 0
  79. #define MT8173_TS2 1
  80. #define MT8173_TS3 2
  81. #define MT8173_TS4 3
  82. #define MT8173_TSABB 4
  83. /* AUXADC channel 11 is used for the temperature sensors */
  84. #define MT8173_TEMP_AUXADC_CHANNEL 11
  85. /* The total number of temperature sensors in the MT8173 */
  86. #define MT8173_NUM_SENSORS 5
  87. /* The number of banks in the MT8173 */
  88. #define MT8173_NUM_ZONES 4
  89. /* The number of sensing points per bank */
  90. #define MT8173_NUM_SENSORS_PER_ZONE 4
  91. /* The number of controller in the MT8173 */
  92. #define MT8173_NUM_CONTROLLER 1
  93. /* The calibration coefficient of sensor */
  94. #define MT8173_CALIBRATION 165
  95. /*
  96. * Layout of the fuses providing the calibration data
  97. * These macros could be used for MT8183, MT8173, MT2701, and MT2712.
  98. * MT8183 has 6 sensors and needs 6 VTS calibration data.
  99. * MT8173 has 5 sensors and needs 5 VTS calibration data.
  100. * MT2701 has 3 sensors and needs 3 VTS calibration data.
  101. * MT2712 has 4 sensors and needs 4 VTS calibration data.
  102. */
  103. #define CALIB_BUF0_VALID_V1 BIT(0)
  104. #define CALIB_BUF1_ADC_GE_V1(x) (((x) >> 22) & 0x3ff)
  105. #define CALIB_BUF0_VTS_TS1_V1(x) (((x) >> 17) & 0x1ff)
  106. #define CALIB_BUF0_VTS_TS2_V1(x) (((x) >> 8) & 0x1ff)
  107. #define CALIB_BUF1_VTS_TS3_V1(x) (((x) >> 0) & 0x1ff)
  108. #define CALIB_BUF2_VTS_TS4_V1(x) (((x) >> 23) & 0x1ff)
  109. #define CALIB_BUF2_VTS_TS5_V1(x) (((x) >> 5) & 0x1ff)
  110. #define CALIB_BUF2_VTS_TSABB_V1(x) (((x) >> 14) & 0x1ff)
  111. #define CALIB_BUF0_DEGC_CALI_V1(x) (((x) >> 1) & 0x3f)
  112. #define CALIB_BUF0_O_SLOPE_V1(x) (((x) >> 26) & 0x3f)
  113. #define CALIB_BUF0_O_SLOPE_SIGN_V1(x) (((x) >> 7) & 0x1)
  114. #define CALIB_BUF1_ID_V1(x) (((x) >> 9) & 0x1)
  115. /*
  116. * Layout of the fuses providing the calibration data
  117. * These macros could be used for MT7622.
  118. */
  119. #define CALIB_BUF0_ADC_OE_V2(x) (((x) >> 22) & 0x3ff)
  120. #define CALIB_BUF0_ADC_GE_V2(x) (((x) >> 12) & 0x3ff)
  121. #define CALIB_BUF0_DEGC_CALI_V2(x) (((x) >> 6) & 0x3f)
  122. #define CALIB_BUF0_O_SLOPE_V2(x) (((x) >> 0) & 0x3f)
  123. #define CALIB_BUF1_VTS_TS1_V2(x) (((x) >> 23) & 0x1ff)
  124. #define CALIB_BUF1_VTS_TS2_V2(x) (((x) >> 14) & 0x1ff)
  125. #define CALIB_BUF1_VTS_TSABB_V2(x) (((x) >> 5) & 0x1ff)
  126. #define CALIB_BUF1_VALID_V2(x) (((x) >> 4) & 0x1)
  127. #define CALIB_BUF1_O_SLOPE_SIGN_V2(x) (((x) >> 3) & 0x1)
  128. enum {
  129. VTS1,
  130. VTS2,
  131. VTS3,
  132. VTS4,
  133. VTS5,
  134. VTSABB,
  135. MAX_NUM_VTS,
  136. };
  137. enum mtk_thermal_version {
  138. MTK_THERMAL_V1 = 1,
  139. MTK_THERMAL_V2,
  140. };
  141. /* MT2701 thermal sensors */
  142. #define MT2701_TS1 0
  143. #define MT2701_TS2 1
  144. #define MT2701_TSABB 2
  145. /* AUXADC channel 11 is used for the temperature sensors */
  146. #define MT2701_TEMP_AUXADC_CHANNEL 11
  147. /* The total number of temperature sensors in the MT2701 */
  148. #define MT2701_NUM_SENSORS 3
  149. /* The number of sensing points per bank */
  150. #define MT2701_NUM_SENSORS_PER_ZONE 3
  151. /* The number of controller in the MT2701 */
  152. #define MT2701_NUM_CONTROLLER 1
  153. /* The calibration coefficient of sensor */
  154. #define MT2701_CALIBRATION 165
  155. /* MT2712 thermal sensors */
  156. #define MT2712_TS1 0
  157. #define MT2712_TS2 1
  158. #define MT2712_TS3 2
  159. #define MT2712_TS4 3
  160. /* AUXADC channel 11 is used for the temperature sensors */
  161. #define MT2712_TEMP_AUXADC_CHANNEL 11
  162. /* The total number of temperature sensors in the MT2712 */
  163. #define MT2712_NUM_SENSORS 4
  164. /* The number of sensing points per bank */
  165. #define MT2712_NUM_SENSORS_PER_ZONE 4
  166. /* The number of controller in the MT2712 */
  167. #define MT2712_NUM_CONTROLLER 1
  168. /* The calibration coefficient of sensor */
  169. #define MT2712_CALIBRATION 165
  170. #define MT7622_TEMP_AUXADC_CHANNEL 11
  171. #define MT7622_NUM_SENSORS 1
  172. #define MT7622_NUM_ZONES 1
  173. #define MT7622_NUM_SENSORS_PER_ZONE 1
  174. #define MT7622_TS1 0
  175. #define MT7622_NUM_CONTROLLER 1
  176. /* The maximum number of banks */
  177. #define MAX_NUM_ZONES 8
  178. /* The calibration coefficient of sensor */
  179. #define MT7622_CALIBRATION 165
  180. /* MT8183 thermal sensors */
  181. #define MT8183_TS1 0
  182. #define MT8183_TS2 1
  183. #define MT8183_TS3 2
  184. #define MT8183_TS4 3
  185. #define MT8183_TS5 4
  186. #define MT8183_TSABB 5
  187. /* AUXADC channel is used for the temperature sensors */
  188. #define MT8183_TEMP_AUXADC_CHANNEL 11
  189. /* The total number of temperature sensors in the MT8183 */
  190. #define MT8183_NUM_SENSORS 6
  191. /* The number of banks in the MT8183 */
  192. #define MT8183_NUM_ZONES 1
  193. /* The number of sensing points per bank */
  194. #define MT8183_NUM_SENSORS_PER_ZONE 6
  195. /* The number of controller in the MT8183 */
  196. #define MT8183_NUM_CONTROLLER 2
  197. /* The calibration coefficient of sensor */
  198. #define MT8183_CALIBRATION 153
  199. struct mtk_thermal;
  200. struct thermal_bank_cfg {
  201. unsigned int num_sensors;
  202. const int *sensors;
  203. };
  204. struct mtk_thermal_bank {
  205. struct mtk_thermal *mt;
  206. int id;
  207. };
  208. struct mtk_thermal_data {
  209. s32 num_banks;
  210. s32 num_sensors;
  211. s32 auxadc_channel;
  212. const int *vts_index;
  213. const int *sensor_mux_values;
  214. const int *msr;
  215. const int *adcpnp;
  216. const int cali_val;
  217. const int num_controller;
  218. const int *controller_offset;
  219. bool need_switch_bank;
  220. struct thermal_bank_cfg bank_data[MAX_NUM_ZONES];
  221. enum mtk_thermal_version version;
  222. };
  223. struct mtk_thermal {
  224. struct device *dev;
  225. void __iomem *thermal_base;
  226. struct clk *clk_peri_therm;
  227. struct clk *clk_auxadc;
  228. /* lock: for getting and putting banks */
  229. struct mutex lock;
  230. /* Calibration values */
  231. s32 adc_ge;
  232. s32 adc_oe;
  233. s32 degc_cali;
  234. s32 o_slope;
  235. s32 o_slope_sign;
  236. s32 vts[MAX_NUM_VTS];
  237. const struct mtk_thermal_data *conf;
  238. struct mtk_thermal_bank banks[MAX_NUM_ZONES];
  239. };
  240. /* MT8183 thermal sensor data */
  241. static const int mt8183_bank_data[MT8183_NUM_SENSORS] = {
  242. MT8183_TS1, MT8183_TS2, MT8183_TS3, MT8183_TS4, MT8183_TS5, MT8183_TSABB
  243. };
  244. static const int mt8183_msr[MT8183_NUM_SENSORS_PER_ZONE] = {
  245. TEMP_MSR0_1, TEMP_MSR1_1, TEMP_MSR2_1, TEMP_MSR1, TEMP_MSR0, TEMP_MSR3_1
  246. };
  247. static const int mt8183_adcpnp[MT8183_NUM_SENSORS_PER_ZONE] = {
  248. TEMP_ADCPNP0_1, TEMP_ADCPNP1_1, TEMP_ADCPNP2_1,
  249. TEMP_ADCPNP1, TEMP_ADCPNP0, TEMP_ADCPNP3_1
  250. };
  251. static const int mt8183_mux_values[MT8183_NUM_SENSORS] = { 0, 1, 2, 3, 4, 0 };
  252. static const int mt8183_tc_offset[MT8183_NUM_CONTROLLER] = {0x0, 0x100};
  253. static const int mt8183_vts_index[MT8183_NUM_SENSORS] = {
  254. VTS1, VTS2, VTS3, VTS4, VTS5, VTSABB
  255. };
  256. /* MT8173 thermal sensor data */
  257. static const int mt8173_bank_data[MT8173_NUM_ZONES][3] = {
  258. { MT8173_TS2, MT8173_TS3 },
  259. { MT8173_TS2, MT8173_TS4 },
  260. { MT8173_TS1, MT8173_TS2, MT8173_TSABB },
  261. { MT8173_TS2 },
  262. };
  263. static const int mt8173_msr[MT8173_NUM_SENSORS_PER_ZONE] = {
  264. TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
  265. };
  266. static const int mt8173_adcpnp[MT8173_NUM_SENSORS_PER_ZONE] = {
  267. TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
  268. };
  269. static const int mt8173_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 };
  270. static const int mt8173_tc_offset[MT8173_NUM_CONTROLLER] = { 0x0, };
  271. static const int mt8173_vts_index[MT8173_NUM_SENSORS] = {
  272. VTS1, VTS2, VTS3, VTS4, VTSABB
  273. };
  274. /* MT2701 thermal sensor data */
  275. static const int mt2701_bank_data[MT2701_NUM_SENSORS] = {
  276. MT2701_TS1, MT2701_TS2, MT2701_TSABB
  277. };
  278. static const int mt2701_msr[MT2701_NUM_SENSORS_PER_ZONE] = {
  279. TEMP_MSR0, TEMP_MSR1, TEMP_MSR2
  280. };
  281. static const int mt2701_adcpnp[MT2701_NUM_SENSORS_PER_ZONE] = {
  282. TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2
  283. };
  284. static const int mt2701_mux_values[MT2701_NUM_SENSORS] = { 0, 1, 16 };
  285. static const int mt2701_tc_offset[MT2701_NUM_CONTROLLER] = { 0x0, };
  286. static const int mt2701_vts_index[MT2701_NUM_SENSORS] = {
  287. VTS1, VTS2, VTS3
  288. };
  289. /* MT2712 thermal sensor data */
  290. static const int mt2712_bank_data[MT2712_NUM_SENSORS] = {
  291. MT2712_TS1, MT2712_TS2, MT2712_TS3, MT2712_TS4
  292. };
  293. static const int mt2712_msr[MT2712_NUM_SENSORS_PER_ZONE] = {
  294. TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
  295. };
  296. static const int mt2712_adcpnp[MT2712_NUM_SENSORS_PER_ZONE] = {
  297. TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
  298. };
  299. static const int mt2712_mux_values[MT2712_NUM_SENSORS] = { 0, 1, 2, 3 };
  300. static const int mt2712_tc_offset[MT2712_NUM_CONTROLLER] = { 0x0, };
  301. static const int mt2712_vts_index[MT2712_NUM_SENSORS] = {
  302. VTS1, VTS2, VTS3, VTS4
  303. };
  304. /* MT7622 thermal sensor data */
  305. static const int mt7622_bank_data[MT7622_NUM_SENSORS] = { MT7622_TS1, };
  306. static const int mt7622_msr[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
  307. static const int mt7622_adcpnp[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
  308. static const int mt7622_mux_values[MT7622_NUM_SENSORS] = { 0, };
  309. static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 };
  310. static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, };
  311. /*
  312. * The MT8173 thermal controller has four banks. Each bank can read up to
  313. * four temperature sensors simultaneously. The MT8173 has a total of 5
  314. * temperature sensors. We use each bank to measure a certain area of the
  315. * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple
  316. * areas, hence is used in different banks.
  317. *
  318. * The thermal core only gets the maximum temperature of all banks, so
  319. * the bank concept wouldn't be necessary here. However, the SVS (Smart
  320. * Voltage Scaling) unit makes its decisions based on the same bank
  321. * data, and this indeed needs the temperatures of the individual banks
  322. * for making better decisions.
  323. */
  324. static const struct mtk_thermal_data mt8173_thermal_data = {
  325. .auxadc_channel = MT8173_TEMP_AUXADC_CHANNEL,
  326. .num_banks = MT8173_NUM_ZONES,
  327. .num_sensors = MT8173_NUM_SENSORS,
  328. .vts_index = mt8173_vts_index,
  329. .cali_val = MT8173_CALIBRATION,
  330. .num_controller = MT8173_NUM_CONTROLLER,
  331. .controller_offset = mt8173_tc_offset,
  332. .need_switch_bank = true,
  333. .bank_data = {
  334. {
  335. .num_sensors = 2,
  336. .sensors = mt8173_bank_data[0],
  337. }, {
  338. .num_sensors = 2,
  339. .sensors = mt8173_bank_data[1],
  340. }, {
  341. .num_sensors = 3,
  342. .sensors = mt8173_bank_data[2],
  343. }, {
  344. .num_sensors = 1,
  345. .sensors = mt8173_bank_data[3],
  346. },
  347. },
  348. .msr = mt8173_msr,
  349. .adcpnp = mt8173_adcpnp,
  350. .sensor_mux_values = mt8173_mux_values,
  351. .version = MTK_THERMAL_V1,
  352. };
  353. /*
  354. * The MT2701 thermal controller has one bank, which can read up to
  355. * three temperature sensors simultaneously. The MT2701 has a total of 3
  356. * temperature sensors.
  357. *
  358. * The thermal core only gets the maximum temperature of this one bank,
  359. * so the bank concept wouldn't be necessary here. However, the SVS (Smart
  360. * Voltage Scaling) unit makes its decisions based on the same bank
  361. * data.
  362. */
  363. static const struct mtk_thermal_data mt2701_thermal_data = {
  364. .auxadc_channel = MT2701_TEMP_AUXADC_CHANNEL,
  365. .num_banks = 1,
  366. .num_sensors = MT2701_NUM_SENSORS,
  367. .vts_index = mt2701_vts_index,
  368. .cali_val = MT2701_CALIBRATION,
  369. .num_controller = MT2701_NUM_CONTROLLER,
  370. .controller_offset = mt2701_tc_offset,
  371. .need_switch_bank = true,
  372. .bank_data = {
  373. {
  374. .num_sensors = 3,
  375. .sensors = mt2701_bank_data,
  376. },
  377. },
  378. .msr = mt2701_msr,
  379. .adcpnp = mt2701_adcpnp,
  380. .sensor_mux_values = mt2701_mux_values,
  381. .version = MTK_THERMAL_V1,
  382. };
  383. /*
  384. * The MT2712 thermal controller has one bank, which can read up to
  385. * four temperature sensors simultaneously. The MT2712 has a total of 4
  386. * temperature sensors.
  387. *
  388. * The thermal core only gets the maximum temperature of this one bank,
  389. * so the bank concept wouldn't be necessary here. However, the SVS (Smart
  390. * Voltage Scaling) unit makes its decisions based on the same bank
  391. * data.
  392. */
  393. static const struct mtk_thermal_data mt2712_thermal_data = {
  394. .auxadc_channel = MT2712_TEMP_AUXADC_CHANNEL,
  395. .num_banks = 1,
  396. .num_sensors = MT2712_NUM_SENSORS,
  397. .vts_index = mt2712_vts_index,
  398. .cali_val = MT2712_CALIBRATION,
  399. .num_controller = MT2712_NUM_CONTROLLER,
  400. .controller_offset = mt2712_tc_offset,
  401. .need_switch_bank = true,
  402. .bank_data = {
  403. {
  404. .num_sensors = 4,
  405. .sensors = mt2712_bank_data,
  406. },
  407. },
  408. .msr = mt2712_msr,
  409. .adcpnp = mt2712_adcpnp,
  410. .sensor_mux_values = mt2712_mux_values,
  411. .version = MTK_THERMAL_V1,
  412. };
  413. /*
  414. * MT7622 have only one sensing point which uses AUXADC Channel 11 for raw data
  415. * access.
  416. */
  417. static const struct mtk_thermal_data mt7622_thermal_data = {
  418. .auxadc_channel = MT7622_TEMP_AUXADC_CHANNEL,
  419. .num_banks = MT7622_NUM_ZONES,
  420. .num_sensors = MT7622_NUM_SENSORS,
  421. .vts_index = mt7622_vts_index,
  422. .cali_val = MT7622_CALIBRATION,
  423. .num_controller = MT7622_NUM_CONTROLLER,
  424. .controller_offset = mt7622_tc_offset,
  425. .need_switch_bank = true,
  426. .bank_data = {
  427. {
  428. .num_sensors = 1,
  429. .sensors = mt7622_bank_data,
  430. },
  431. },
  432. .msr = mt7622_msr,
  433. .adcpnp = mt7622_adcpnp,
  434. .sensor_mux_values = mt7622_mux_values,
  435. .version = MTK_THERMAL_V2,
  436. };
  437. /*
  438. * The MT8183 thermal controller has one bank for the current SW framework.
  439. * The MT8183 has a total of 6 temperature sensors.
  440. * There are two thermal controller to control the six sensor.
  441. * The first one bind 2 sensor, and the other bind 4 sensors.
  442. * The thermal core only gets the maximum temperature of all sensor, so
  443. * the bank concept wouldn't be necessary here. However, the SVS (Smart
  444. * Voltage Scaling) unit makes its decisions based on the same bank
  445. * data, and this indeed needs the temperatures of the individual banks
  446. * for making better decisions.
  447. */
  448. static const struct mtk_thermal_data mt8183_thermal_data = {
  449. .auxadc_channel = MT8183_TEMP_AUXADC_CHANNEL,
  450. .num_banks = MT8183_NUM_ZONES,
  451. .num_sensors = MT8183_NUM_SENSORS,
  452. .vts_index = mt8183_vts_index,
  453. .cali_val = MT8183_CALIBRATION,
  454. .num_controller = MT8183_NUM_CONTROLLER,
  455. .controller_offset = mt8183_tc_offset,
  456. .need_switch_bank = false,
  457. .bank_data = {
  458. {
  459. .num_sensors = 6,
  460. .sensors = mt8183_bank_data,
  461. },
  462. },
  463. .msr = mt8183_msr,
  464. .adcpnp = mt8183_adcpnp,
  465. .sensor_mux_values = mt8183_mux_values,
  466. .version = MTK_THERMAL_V1,
  467. };
  468. /**
  469. * raw_to_mcelsius - convert a raw ADC value to mcelsius
  470. * @mt: The thermal controller
  471. * @sensno: sensor number
  472. * @raw: raw ADC value
  473. *
  474. * This converts the raw ADC value to mcelsius using the SoC specific
  475. * calibration constants
  476. */
  477. static int raw_to_mcelsius_v1(struct mtk_thermal *mt, int sensno, s32 raw)
  478. {
  479. s32 tmp;
  480. raw &= 0xfff;
  481. tmp = 203450520 << 3;
  482. tmp /= mt->conf->cali_val + mt->o_slope;
  483. tmp /= 10000 + mt->adc_ge;
  484. tmp *= raw - mt->vts[sensno] - 3350;
  485. tmp >>= 3;
  486. return mt->degc_cali * 500 - tmp;
  487. }
  488. static int raw_to_mcelsius_v2(struct mtk_thermal *mt, int sensno, s32 raw)
  489. {
  490. s32 format_1 = 0;
  491. s32 format_2 = 0;
  492. s32 g_oe = 1;
  493. s32 g_gain = 1;
  494. s32 g_x_roomt = 0;
  495. s32 tmp = 0;
  496. if (raw == 0)
  497. return 0;
  498. raw &= 0xfff;
  499. g_gain = 10000 + (((mt->adc_ge - 512) * 10000) >> 12);
  500. g_oe = mt->adc_oe - 512;
  501. format_1 = mt->vts[VTS2] + 3105 - g_oe;
  502. format_2 = (mt->degc_cali * 10) >> 1;
  503. g_x_roomt = (((format_1 * 10000) >> 12) * 10000) / g_gain;
  504. tmp = (((((raw - g_oe) * 10000) >> 12) * 10000) / g_gain) - g_x_roomt;
  505. tmp = tmp * 10 * 100 / 11;
  506. if (mt->o_slope_sign == 0)
  507. tmp = tmp / (165 - mt->o_slope);
  508. else
  509. tmp = tmp / (165 + mt->o_slope);
  510. return (format_2 - tmp) * 100;
  511. }
  512. /**
  513. * mtk_thermal_get_bank - get bank
  514. * @bank: The bank
  515. *
  516. * The bank registers are banked, we have to select a bank in the
  517. * PTPCORESEL register to access it.
  518. */
  519. static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank)
  520. {
  521. struct mtk_thermal *mt = bank->mt;
  522. u32 val;
  523. if (mt->conf->need_switch_bank) {
  524. mutex_lock(&mt->lock);
  525. val = readl(mt->thermal_base + PTPCORESEL);
  526. val &= ~0xf;
  527. val |= bank->id;
  528. writel(val, mt->thermal_base + PTPCORESEL);
  529. }
  530. }
  531. /**
  532. * mtk_thermal_put_bank - release bank
  533. * @bank: The bank
  534. *
  535. * release a bank previously taken with mtk_thermal_get_bank,
  536. */
  537. static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank)
  538. {
  539. struct mtk_thermal *mt = bank->mt;
  540. if (mt->conf->need_switch_bank)
  541. mutex_unlock(&mt->lock);
  542. }
  543. /**
  544. * mtk_thermal_bank_temperature - get the temperature of a bank
  545. * @bank: The bank
  546. *
  547. * The temperature of a bank is considered the maximum temperature of
  548. * the sensors associated to the bank.
  549. */
  550. static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank)
  551. {
  552. struct mtk_thermal *mt = bank->mt;
  553. const struct mtk_thermal_data *conf = mt->conf;
  554. int i, temp = INT_MIN, max = INT_MIN;
  555. u32 raw;
  556. for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) {
  557. raw = readl(mt->thermal_base + conf->msr[i]);
  558. if (mt->conf->version == MTK_THERMAL_V1) {
  559. temp = raw_to_mcelsius_v1(
  560. mt, conf->bank_data[bank->id].sensors[i], raw);
  561. } else {
  562. temp = raw_to_mcelsius_v2(
  563. mt, conf->bank_data[bank->id].sensors[i], raw);
  564. }
  565. /*
  566. * The first read of a sensor often contains very high bogus
  567. * temperature value. Filter these out so that the system does
  568. * not immediately shut down.
  569. */
  570. if (temp > 200000)
  571. temp = 0;
  572. if (temp > max)
  573. max = temp;
  574. }
  575. return max;
  576. }
  577. static int mtk_read_temp(void *data, int *temperature)
  578. {
  579. struct mtk_thermal *mt = data;
  580. int i;
  581. int tempmax = INT_MIN;
  582. for (i = 0; i < mt->conf->num_banks; i++) {
  583. struct mtk_thermal_bank *bank = &mt->banks[i];
  584. mtk_thermal_get_bank(bank);
  585. tempmax = max(tempmax, mtk_thermal_bank_temperature(bank));
  586. mtk_thermal_put_bank(bank);
  587. }
  588. *temperature = tempmax;
  589. return 0;
  590. }
  591. static const struct thermal_zone_of_device_ops mtk_thermal_ops = {
  592. .get_temp = mtk_read_temp,
  593. };
  594. static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
  595. u32 apmixed_phys_base, u32 auxadc_phys_base,
  596. int ctrl_id)
  597. {
  598. struct mtk_thermal_bank *bank = &mt->banks[num];
  599. const struct mtk_thermal_data *conf = mt->conf;
  600. int i;
  601. int offset = mt->conf->controller_offset[ctrl_id];
  602. void __iomem *controller_base = mt->thermal_base + offset;
  603. bank->id = num;
  604. bank->mt = mt;
  605. mtk_thermal_get_bank(bank);
  606. /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */
  607. writel(TEMP_MONCTL1_PERIOD_UNIT(12), controller_base + TEMP_MONCTL1);
  608. /*
  609. * filt interval is 1 * 46.540us = 46.54us,
  610. * sen interval is 429 * 46.540us = 19.96ms
  611. */
  612. writel(TEMP_MONCTL2_FILTER_INTERVAL(1) |
  613. TEMP_MONCTL2_SENSOR_INTERVAL(429),
  614. controller_base + TEMP_MONCTL2);
  615. /* poll is set to 10u */
  616. writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768),
  617. controller_base + TEMP_AHBPOLL);
  618. /* temperature sampling control, 1 sample */
  619. writel(0x0, controller_base + TEMP_MSRCTL0);
  620. /* exceed this polling time, IRQ would be inserted */
  621. writel(0xffffffff, controller_base + TEMP_AHBTO);
  622. /* number of interrupts per event, 1 is enough */
  623. writel(0x0, controller_base + TEMP_MONIDET0);
  624. writel(0x0, controller_base + TEMP_MONIDET1);
  625. /*
  626. * The MT8173 thermal controller does not have its own ADC. Instead it
  627. * uses AHB bus accesses to control the AUXADC. To do this the thermal
  628. * controller has to be programmed with the physical addresses of the
  629. * AUXADC registers and with the various bit positions in the AUXADC.
  630. * Also the thermal controller controls a mux in the APMIXEDSYS register
  631. * space.
  632. */
  633. /*
  634. * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0)
  635. * automatically by hw
  636. */
  637. writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCMUX);
  638. /* AHB address for auxadc mux selection */
  639. writel(auxadc_phys_base + AUXADC_CON1_CLR_V,
  640. controller_base + TEMP_ADCMUXADDR);
  641. if (mt->conf->version == MTK_THERMAL_V1) {
  642. /* AHB address for pnp sensor mux selection */
  643. writel(apmixed_phys_base + APMIXED_SYS_TS_CON1,
  644. controller_base + TEMP_PNPMUXADDR);
  645. }
  646. /* AHB value for auxadc enable */
  647. writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCEN);
  648. /* AHB address for auxadc enable (channel 0 immediate mode selected) */
  649. writel(auxadc_phys_base + AUXADC_CON1_SET_V,
  650. controller_base + TEMP_ADCENADDR);
  651. /* AHB address for auxadc valid bit */
  652. writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
  653. controller_base + TEMP_ADCVALIDADDR);
  654. /* AHB address for auxadc voltage output */
  655. writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
  656. controller_base + TEMP_ADCVOLTADDR);
  657. /* read valid & voltage are at the same register */
  658. writel(0x0, controller_base + TEMP_RDCTRL);
  659. /* indicate where the valid bit is */
  660. writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12),
  661. controller_base + TEMP_ADCVALIDMASK);
  662. /* no shift */
  663. writel(0x0, controller_base + TEMP_ADCVOLTAGESHIFT);
  664. /* enable auxadc mux write transaction */
  665. writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
  666. controller_base + TEMP_ADCWRITECTRL);
  667. for (i = 0; i < conf->bank_data[num].num_sensors; i++)
  668. writel(conf->sensor_mux_values[conf->bank_data[num].sensors[i]],
  669. mt->thermal_base + conf->adcpnp[i]);
  670. writel((1 << conf->bank_data[num].num_sensors) - 1,
  671. controller_base + TEMP_MONCTL0);
  672. writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE |
  673. TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
  674. controller_base + TEMP_ADCWRITECTRL);
  675. mtk_thermal_put_bank(bank);
  676. }
  677. static u64 of_get_phys_base(struct device_node *np)
  678. {
  679. u64 size64;
  680. const __be32 *regaddr_p;
  681. regaddr_p = of_get_address(np, 0, &size64, NULL);
  682. if (!regaddr_p)
  683. return OF_BAD_ADDR;
  684. return of_translate_address(np, regaddr_p);
  685. }
  686. static int mtk_thermal_extract_efuse_v1(struct mtk_thermal *mt, u32 *buf)
  687. {
  688. int i;
  689. if (!(buf[0] & CALIB_BUF0_VALID_V1))
  690. return -EINVAL;
  691. mt->adc_ge = CALIB_BUF1_ADC_GE_V1(buf[1]);
  692. for (i = 0; i < mt->conf->num_sensors; i++) {
  693. switch (mt->conf->vts_index[i]) {
  694. case VTS1:
  695. mt->vts[VTS1] = CALIB_BUF0_VTS_TS1_V1(buf[0]);
  696. break;
  697. case VTS2:
  698. mt->vts[VTS2] = CALIB_BUF0_VTS_TS2_V1(buf[0]);
  699. break;
  700. case VTS3:
  701. mt->vts[VTS3] = CALIB_BUF1_VTS_TS3_V1(buf[1]);
  702. break;
  703. case VTS4:
  704. mt->vts[VTS4] = CALIB_BUF2_VTS_TS4_V1(buf[2]);
  705. break;
  706. case VTS5:
  707. mt->vts[VTS5] = CALIB_BUF2_VTS_TS5_V1(buf[2]);
  708. break;
  709. case VTSABB:
  710. mt->vts[VTSABB] =
  711. CALIB_BUF2_VTS_TSABB_V1(buf[2]);
  712. break;
  713. default:
  714. break;
  715. }
  716. }
  717. mt->degc_cali = CALIB_BUF0_DEGC_CALI_V1(buf[0]);
  718. if (CALIB_BUF1_ID_V1(buf[1]) &
  719. CALIB_BUF0_O_SLOPE_SIGN_V1(buf[0]))
  720. mt->o_slope = -CALIB_BUF0_O_SLOPE_V1(buf[0]);
  721. else
  722. mt->o_slope = CALIB_BUF0_O_SLOPE_V1(buf[0]);
  723. return 0;
  724. }
  725. static int mtk_thermal_extract_efuse_v2(struct mtk_thermal *mt, u32 *buf)
  726. {
  727. if (!CALIB_BUF1_VALID_V2(buf[1]))
  728. return -EINVAL;
  729. mt->adc_oe = CALIB_BUF0_ADC_OE_V2(buf[0]);
  730. mt->adc_ge = CALIB_BUF0_ADC_GE_V2(buf[0]);
  731. mt->degc_cali = CALIB_BUF0_DEGC_CALI_V2(buf[0]);
  732. mt->o_slope = CALIB_BUF0_O_SLOPE_V2(buf[0]);
  733. mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V2(buf[1]);
  734. mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V2(buf[1]);
  735. mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V2(buf[1]);
  736. mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V2(buf[1]);
  737. return 0;
  738. }
  739. static int mtk_thermal_get_calibration_data(struct device *dev,
  740. struct mtk_thermal *mt)
  741. {
  742. struct nvmem_cell *cell;
  743. u32 *buf;
  744. size_t len;
  745. int i, ret = 0;
  746. /* Start with default values */
  747. mt->adc_ge = 512;
  748. for (i = 0; i < mt->conf->num_sensors; i++)
  749. mt->vts[i] = 260;
  750. mt->degc_cali = 40;
  751. mt->o_slope = 0;
  752. cell = nvmem_cell_get(dev, "calibration-data");
  753. if (IS_ERR(cell)) {
  754. if (PTR_ERR(cell) == -EPROBE_DEFER)
  755. return PTR_ERR(cell);
  756. return 0;
  757. }
  758. buf = (u32 *)nvmem_cell_read(cell, &len);
  759. nvmem_cell_put(cell);
  760. if (IS_ERR(buf))
  761. return PTR_ERR(buf);
  762. if (len < 3 * sizeof(u32)) {
  763. dev_warn(dev, "invalid calibration data\n");
  764. ret = -EINVAL;
  765. goto out;
  766. }
  767. if (mt->conf->version == MTK_THERMAL_V1)
  768. ret = mtk_thermal_extract_efuse_v1(mt, buf);
  769. else
  770. ret = mtk_thermal_extract_efuse_v2(mt, buf);
  771. if (ret) {
  772. dev_info(dev, "Device not calibrated, using default calibration values\n");
  773. ret = 0;
  774. }
  775. out:
  776. kfree(buf);
  777. return ret;
  778. }
  779. static const struct of_device_id mtk_thermal_of_match[] = {
  780. {
  781. .compatible = "mediatek,mt8173-thermal",
  782. .data = (void *)&mt8173_thermal_data,
  783. },
  784. {
  785. .compatible = "mediatek,mt2701-thermal",
  786. .data = (void *)&mt2701_thermal_data,
  787. },
  788. {
  789. .compatible = "mediatek,mt2712-thermal",
  790. .data = (void *)&mt2712_thermal_data,
  791. },
  792. {
  793. .compatible = "mediatek,mt7622-thermal",
  794. .data = (void *)&mt7622_thermal_data,
  795. },
  796. {
  797. .compatible = "mediatek,mt8183-thermal",
  798. .data = (void *)&mt8183_thermal_data,
  799. }, {
  800. },
  801. };
  802. MODULE_DEVICE_TABLE(of, mtk_thermal_of_match);
  803. static void mtk_thermal_turn_on_buffer(void __iomem *apmixed_base)
  804. {
  805. int tmp;
  806. tmp = readl(apmixed_base + APMIXED_SYS_TS_CON1);
  807. tmp &= ~(0x37);
  808. tmp |= 0x1;
  809. writel(tmp, apmixed_base + APMIXED_SYS_TS_CON1);
  810. udelay(200);
  811. }
  812. static void mtk_thermal_release_periodic_ts(struct mtk_thermal *mt,
  813. void __iomem *auxadc_base)
  814. {
  815. int tmp;
  816. writel(0x800, auxadc_base + AUXADC_CON1_SET_V);
  817. writel(0x1, mt->thermal_base + TEMP_MONCTL0);
  818. tmp = readl(mt->thermal_base + TEMP_MSRCTL1);
  819. writel((tmp & (~0x10e)), mt->thermal_base + TEMP_MSRCTL1);
  820. }
  821. static int mtk_thermal_probe(struct platform_device *pdev)
  822. {
  823. int ret, i, ctrl_id;
  824. struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node;
  825. struct mtk_thermal *mt;
  826. struct resource *res;
  827. u64 auxadc_phys_base, apmixed_phys_base;
  828. struct thermal_zone_device *tzdev;
  829. void __iomem *apmixed_base, *auxadc_base;
  830. mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL);
  831. if (!mt)
  832. return -ENOMEM;
  833. mt->conf = of_device_get_match_data(&pdev->dev);
  834. mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm");
  835. if (IS_ERR(mt->clk_peri_therm))
  836. return PTR_ERR(mt->clk_peri_therm);
  837. mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc");
  838. if (IS_ERR(mt->clk_auxadc))
  839. return PTR_ERR(mt->clk_auxadc);
  840. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  841. mt->thermal_base = devm_ioremap_resource(&pdev->dev, res);
  842. if (IS_ERR(mt->thermal_base))
  843. return PTR_ERR(mt->thermal_base);
  844. ret = mtk_thermal_get_calibration_data(&pdev->dev, mt);
  845. if (ret)
  846. return ret;
  847. mutex_init(&mt->lock);
  848. mt->dev = &pdev->dev;
  849. auxadc = of_parse_phandle(np, "mediatek,auxadc", 0);
  850. if (!auxadc) {
  851. dev_err(&pdev->dev, "missing auxadc node\n");
  852. return -ENODEV;
  853. }
  854. auxadc_base = of_iomap(auxadc, 0);
  855. auxadc_phys_base = of_get_phys_base(auxadc);
  856. of_node_put(auxadc);
  857. if (auxadc_phys_base == OF_BAD_ADDR) {
  858. dev_err(&pdev->dev, "Can't get auxadc phys address\n");
  859. return -EINVAL;
  860. }
  861. apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0);
  862. if (!apmixedsys) {
  863. dev_err(&pdev->dev, "missing apmixedsys node\n");
  864. return -ENODEV;
  865. }
  866. apmixed_base = of_iomap(apmixedsys, 0);
  867. apmixed_phys_base = of_get_phys_base(apmixedsys);
  868. of_node_put(apmixedsys);
  869. if (apmixed_phys_base == OF_BAD_ADDR) {
  870. dev_err(&pdev->dev, "Can't get auxadc phys address\n");
  871. return -EINVAL;
  872. }
  873. ret = device_reset(&pdev->dev);
  874. if (ret)
  875. return ret;
  876. ret = clk_prepare_enable(mt->clk_auxadc);
  877. if (ret) {
  878. dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret);
  879. return ret;
  880. }
  881. ret = clk_prepare_enable(mt->clk_peri_therm);
  882. if (ret) {
  883. dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret);
  884. goto err_disable_clk_auxadc;
  885. }
  886. if (mt->conf->version == MTK_THERMAL_V2) {
  887. mtk_thermal_turn_on_buffer(apmixed_base);
  888. mtk_thermal_release_periodic_ts(mt, auxadc_base);
  889. }
  890. for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++)
  891. for (i = 0; i < mt->conf->num_banks; i++)
  892. mtk_thermal_init_bank(mt, i, apmixed_phys_base,
  893. auxadc_phys_base, ctrl_id);
  894. platform_set_drvdata(pdev, mt);
  895. tzdev = devm_thermal_zone_of_sensor_register(&pdev->dev, 0, mt,
  896. &mtk_thermal_ops);
  897. if (IS_ERR(tzdev)) {
  898. ret = PTR_ERR(tzdev);
  899. goto err_disable_clk_peri_therm;
  900. }
  901. return 0;
  902. err_disable_clk_peri_therm:
  903. clk_disable_unprepare(mt->clk_peri_therm);
  904. err_disable_clk_auxadc:
  905. clk_disable_unprepare(mt->clk_auxadc);
  906. return ret;
  907. }
  908. static int mtk_thermal_remove(struct platform_device *pdev)
  909. {
  910. struct mtk_thermal *mt = platform_get_drvdata(pdev);
  911. clk_disable_unprepare(mt->clk_peri_therm);
  912. clk_disable_unprepare(mt->clk_auxadc);
  913. return 0;
  914. }
  915. static struct platform_driver mtk_thermal_driver = {
  916. .probe = mtk_thermal_probe,
  917. .remove = mtk_thermal_remove,
  918. .driver = {
  919. .name = "mtk-thermal",
  920. .of_match_table = mtk_thermal_of_match,
  921. },
  922. };
  923. module_platform_driver(mtk_thermal_driver);
  924. MODULE_AUTHOR("Michael Kao <michael.kao@mediatek.com>");
  925. MODULE_AUTHOR("Louis Yu <louis.yu@mediatek.com>");
  926. MODULE_AUTHOR("Dawei Chien <dawei.chien@mediatek.com>");
  927. MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
  928. MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>");
  929. MODULE_DESCRIPTION("Mediatek thermal driver");
  930. MODULE_LICENSE("GPL v2");