hif_api_general.h 7.7 KB

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  1. /* SPDX-License-Identifier: Apache-2.0 */
  2. /*
  3. * WFx hardware interface definitions
  4. *
  5. * Copyright (c) 2018-2020, Silicon Laboratories Inc.
  6. */
  7. #ifndef WFX_HIF_API_GENERAL_H
  8. #define WFX_HIF_API_GENERAL_H
  9. #ifdef __KERNEL__
  10. #include <linux/types.h>
  11. #include <linux/if_ether.h>
  12. #else
  13. #include <net/ethernet.h>
  14. #include <stdint.h>
  15. #define __packed __attribute__((__packed__))
  16. #endif
  17. #define HIF_ID_IS_INDICATION 0x80
  18. #define HIF_COUNTER_MAX 7
  19. struct hif_msg {
  20. __le16 len;
  21. u8 id;
  22. u8 reserved:1;
  23. u8 interface:2;
  24. u8 seqnum:3;
  25. u8 encrypted:2;
  26. u8 body[];
  27. } __packed;
  28. enum hif_general_requests_ids {
  29. HIF_REQ_ID_CONFIGURATION = 0x09,
  30. HIF_REQ_ID_CONTROL_GPIO = 0x26,
  31. HIF_REQ_ID_SET_SL_MAC_KEY = 0x27,
  32. HIF_REQ_ID_SL_EXCHANGE_PUB_KEYS = 0x28,
  33. HIF_REQ_ID_SL_CONFIGURE = 0x29,
  34. HIF_REQ_ID_PREVENT_ROLLBACK = 0x2a,
  35. HIF_REQ_ID_PTA_SETTINGS = 0x2b,
  36. HIF_REQ_ID_PTA_PRIORITY = 0x2c,
  37. HIF_REQ_ID_PTA_STATE = 0x2d,
  38. HIF_REQ_ID_SHUT_DOWN = 0x32,
  39. };
  40. enum hif_general_confirmations_ids {
  41. HIF_CNF_ID_CONFIGURATION = 0x09,
  42. HIF_CNF_ID_CONTROL_GPIO = 0x26,
  43. HIF_CNF_ID_SET_SL_MAC_KEY = 0x27,
  44. HIF_CNF_ID_SL_EXCHANGE_PUB_KEYS = 0x28,
  45. HIF_CNF_ID_SL_CONFIGURE = 0x29,
  46. HIF_CNF_ID_PREVENT_ROLLBACK = 0x2a,
  47. HIF_CNF_ID_PTA_SETTINGS = 0x2b,
  48. HIF_CNF_ID_PTA_PRIORITY = 0x2c,
  49. HIF_CNF_ID_PTA_STATE = 0x2d,
  50. HIF_CNF_ID_SHUT_DOWN = 0x32,
  51. };
  52. enum hif_general_indications_ids {
  53. HIF_IND_ID_EXCEPTION = 0xe0,
  54. HIF_IND_ID_STARTUP = 0xe1,
  55. HIF_IND_ID_WAKEUP = 0xe2,
  56. HIF_IND_ID_GENERIC = 0xe3,
  57. HIF_IND_ID_ERROR = 0xe4,
  58. HIF_IND_ID_SL_EXCHANGE_PUB_KEYS = 0xe5
  59. };
  60. #define HIF_STATUS_SUCCESS (cpu_to_le32(0x0000))
  61. #define HIF_STATUS_FAIL (cpu_to_le32(0x0001))
  62. #define HIF_STATUS_INVALID_PARAMETER (cpu_to_le32(0x0002))
  63. #define HIF_STATUS_WARNING (cpu_to_le32(0x0003))
  64. #define HIF_STATUS_UNKNOWN_REQUEST (cpu_to_le32(0x0004))
  65. #define HIF_STATUS_RX_FAIL_DECRYPT (cpu_to_le32(0x0010))
  66. #define HIF_STATUS_RX_FAIL_MIC (cpu_to_le32(0x0011))
  67. #define HIF_STATUS_RX_FAIL_NO_KEY (cpu_to_le32(0x0012))
  68. #define HIF_STATUS_TX_FAIL_RETRIES (cpu_to_le32(0x0013))
  69. #define HIF_STATUS_TX_FAIL_TIMEOUT (cpu_to_le32(0x0014))
  70. #define HIF_STATUS_TX_FAIL_REQUEUE (cpu_to_le32(0x0015))
  71. #define HIF_STATUS_REFUSED (cpu_to_le32(0x0016))
  72. #define HIF_STATUS_BUSY (cpu_to_le32(0x0017))
  73. #define HIF_STATUS_SLK_SET_KEY_SUCCESS (cpu_to_le32(0x005A))
  74. #define HIF_STATUS_SLK_SET_KEY_ALREADY_BURNED (cpu_to_le32(0x006B))
  75. #define HIF_STATUS_SLK_SET_KEY_DISALLOWED_MODE (cpu_to_le32(0x007C))
  76. #define HIF_STATUS_SLK_SET_KEY_UNKNOWN_MODE (cpu_to_le32(0x008D))
  77. #define HIF_STATUS_SLK_NEGO_SUCCESS (cpu_to_le32(0x009E))
  78. #define HIF_STATUS_SLK_NEGO_FAILED (cpu_to_le32(0x00AF))
  79. #define HIF_STATUS_ROLLBACK_SUCCESS (cpu_to_le32(0x1234))
  80. #define HIF_STATUS_ROLLBACK_FAIL (cpu_to_le32(0x1256))
  81. enum hif_api_rate_index {
  82. API_RATE_INDEX_B_1MBPS = 0,
  83. API_RATE_INDEX_B_2MBPS = 1,
  84. API_RATE_INDEX_B_5P5MBPS = 2,
  85. API_RATE_INDEX_B_11MBPS = 3,
  86. API_RATE_INDEX_PBCC_22MBPS = 4,
  87. API_RATE_INDEX_PBCC_33MBPS = 5,
  88. API_RATE_INDEX_G_6MBPS = 6,
  89. API_RATE_INDEX_G_9MBPS = 7,
  90. API_RATE_INDEX_G_12MBPS = 8,
  91. API_RATE_INDEX_G_18MBPS = 9,
  92. API_RATE_INDEX_G_24MBPS = 10,
  93. API_RATE_INDEX_G_36MBPS = 11,
  94. API_RATE_INDEX_G_48MBPS = 12,
  95. API_RATE_INDEX_G_54MBPS = 13,
  96. API_RATE_INDEX_N_6P5MBPS = 14,
  97. API_RATE_INDEX_N_13MBPS = 15,
  98. API_RATE_INDEX_N_19P5MBPS = 16,
  99. API_RATE_INDEX_N_26MBPS = 17,
  100. API_RATE_INDEX_N_39MBPS = 18,
  101. API_RATE_INDEX_N_52MBPS = 19,
  102. API_RATE_INDEX_N_58P5MBPS = 20,
  103. API_RATE_INDEX_N_65MBPS = 21,
  104. API_RATE_NUM_ENTRIES = 22
  105. };
  106. enum hif_fw_type {
  107. HIF_FW_TYPE_ETF = 0x0,
  108. HIF_FW_TYPE_WFM = 0x1,
  109. HIF_FW_TYPE_WSM = 0x2
  110. };
  111. struct hif_ind_startup {
  112. // As the others, this struct is interpreted as little endian by the
  113. // device. However, this struct is also used by the driver. We prefer to
  114. // declare it in native order and doing byte swap on reception.
  115. __le32 status;
  116. u16 hardware_id;
  117. u8 opn[14];
  118. u8 uid[8];
  119. u16 num_inp_ch_bufs;
  120. u16 size_inp_ch_buf;
  121. u8 num_links_ap;
  122. u8 num_interfaces;
  123. u8 mac_addr[2][ETH_ALEN];
  124. u8 api_version_minor;
  125. u8 api_version_major;
  126. u8 link_mode:2;
  127. u8 reserved1:6;
  128. u8 reserved2;
  129. u8 reserved3;
  130. u8 reserved4;
  131. u8 firmware_build;
  132. u8 firmware_minor;
  133. u8 firmware_major;
  134. u8 firmware_type;
  135. u8 disabled_channel_list[2];
  136. u8 region_sel_mode:4;
  137. u8 reserved5:4;
  138. u8 phy1_region:3;
  139. u8 phy0_region:3;
  140. u8 otp_phy_ver:2;
  141. u32 supported_rate_mask;
  142. u8 firmware_label[128];
  143. } __packed;
  144. struct hif_ind_wakeup {
  145. } __packed;
  146. struct hif_req_configuration {
  147. __le16 length;
  148. u8 pds_data[];
  149. } __packed;
  150. struct hif_cnf_configuration {
  151. __le32 status;
  152. } __packed;
  153. enum hif_gpio_mode {
  154. HIF_GPIO_MODE_D0 = 0x0,
  155. HIF_GPIO_MODE_D1 = 0x1,
  156. HIF_GPIO_MODE_OD0 = 0x2,
  157. HIF_GPIO_MODE_OD1 = 0x3,
  158. HIF_GPIO_MODE_TRISTATE = 0x4,
  159. HIF_GPIO_MODE_TOGGLE = 0x5,
  160. HIF_GPIO_MODE_READ = 0x6
  161. };
  162. struct hif_req_control_gpio {
  163. u8 gpio_label;
  164. u8 gpio_mode;
  165. } __packed;
  166. struct hif_cnf_control_gpio {
  167. __le32 status;
  168. __le32 value;
  169. } __packed;
  170. enum hif_generic_indication_type {
  171. HIF_GENERIC_INDICATION_TYPE_RAW = 0x0,
  172. HIF_GENERIC_INDICATION_TYPE_STRING = 0x1,
  173. HIF_GENERIC_INDICATION_TYPE_RX_STATS = 0x2,
  174. HIF_GENERIC_INDICATION_TYPE_TX_POWER_LOOP_INFO = 0x3,
  175. };
  176. struct hif_rx_stats {
  177. __le32 nb_rx_frame;
  178. __le32 nb_crc_frame;
  179. __le32 per_total;
  180. __le32 throughput;
  181. __le32 nb_rx_by_rate[API_RATE_NUM_ENTRIES];
  182. __le16 per[API_RATE_NUM_ENTRIES];
  183. __le16 snr[API_RATE_NUM_ENTRIES]; // signed value
  184. __le16 rssi[API_RATE_NUM_ENTRIES]; // signed value
  185. __le16 cfo[API_RATE_NUM_ENTRIES]; // signed value
  186. __le32 date;
  187. __le32 pwr_clk_freq;
  188. u8 is_ext_pwr_clk;
  189. s8 current_temp;
  190. } __packed;
  191. struct hif_tx_power_loop_info {
  192. __le16 tx_gain_dig;
  193. __le16 tx_gain_pa;
  194. __le16 target_pout; // signed value
  195. __le16 p_estimation; // signed value
  196. __le16 vpdet;
  197. u8 measurement_index;
  198. u8 reserved;
  199. } __packed;
  200. struct hif_ind_generic {
  201. __le32 type;
  202. union {
  203. struct hif_rx_stats rx_stats;
  204. struct hif_tx_power_loop_info tx_power_loop_info;
  205. } data;
  206. } __packed;
  207. enum hif_error {
  208. HIF_ERROR_FIRMWARE_ROLLBACK = 0x00,
  209. HIF_ERROR_FIRMWARE_DEBUG_ENABLED = 0x01,
  210. HIF_ERROR_SLK_OUTDATED_SESSION_KEY = 0x02,
  211. HIF_ERROR_SLK_SESSION_KEY = 0x03,
  212. HIF_ERROR_OOR_VOLTAGE = 0x04,
  213. HIF_ERROR_PDS_PAYLOAD = 0x05,
  214. HIF_ERROR_OOR_TEMPERATURE = 0x06,
  215. HIF_ERROR_SLK_REQ_DURING_KEY_EXCHANGE = 0x07,
  216. HIF_ERROR_SLK_MULTI_TX_UNSUPPORTED = 0x08,
  217. HIF_ERROR_SLK_OVERFLOW = 0x09,
  218. HIF_ERROR_SLK_DECRYPTION = 0x0a,
  219. HIF_ERROR_SLK_WRONG_ENCRYPTION_STATE = 0x0b,
  220. HIF_ERROR_HIF_BUS_FREQUENCY_TOO_LOW = 0x0c,
  221. HIF_ERROR_HIF_RX_DATA_TOO_LARGE = 0x0e,
  222. HIF_ERROR_HIF_TX_QUEUE_FULL = 0x0d,
  223. HIF_ERROR_HIF_BUS = 0x0f,
  224. HIF_ERROR_PDS_TESTFEATURE = 0x10,
  225. HIF_ERROR_SLK_UNCONFIGURED = 0x11,
  226. };
  227. struct hif_ind_error {
  228. __le32 type;
  229. u8 data[];
  230. } __packed;
  231. struct hif_ind_exception {
  232. __le32 type;
  233. u8 data[];
  234. } __packed;
  235. enum hif_secure_link_state {
  236. SEC_LINK_UNAVAILABLE = 0x0,
  237. SEC_LINK_RESERVED = 0x1,
  238. SEC_LINK_EVAL = 0x2,
  239. SEC_LINK_ENFORCED = 0x3
  240. };
  241. #endif