pci-mt7621-phy.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Mediatek MT7621 PCI PHY Driver
  4. * Author: Sergio Paracuellos <sergio.paracuellos@gmail.com>
  5. */
  6. #include <dt-bindings/phy/phy.h>
  7. #include <linux/bitops.h>
  8. #include <linux/module.h>
  9. #include <linux/of_address.h>
  10. #include <linux/of_device.h>
  11. #include <linux/phy/phy.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/regmap.h>
  14. #include <linux/sys_soc.h>
  15. #include <mt7621.h>
  16. #include <ralink_regs.h>
  17. #define RG_PE1_PIPE_REG 0x02c
  18. #define RG_PE1_PIPE_RST BIT(12)
  19. #define RG_PE1_PIPE_CMD_FRC BIT(4)
  20. #define RG_P0_TO_P1_WIDTH 0x100
  21. #define RG_PE1_H_LCDDS_REG 0x49c
  22. #define RG_PE1_H_LCDDS_PCW GENMASK(30, 0)
  23. #define RG_PE1_H_LCDDS_PCW_VAL(x) ((0x7fffffff & (x)) << 0)
  24. #define RG_PE1_FRC_H_XTAL_REG 0x400
  25. #define RG_PE1_FRC_H_XTAL_TYPE BIT(8)
  26. #define RG_PE1_H_XTAL_TYPE GENMASK(10, 9)
  27. #define RG_PE1_H_XTAL_TYPE_VAL(x) ((0x3 & (x)) << 9)
  28. #define RG_PE1_FRC_PHY_REG 0x000
  29. #define RG_PE1_FRC_PHY_EN BIT(4)
  30. #define RG_PE1_PHY_EN BIT(5)
  31. #define RG_PE1_H_PLL_REG 0x490
  32. #define RG_PE1_H_PLL_BC GENMASK(23, 22)
  33. #define RG_PE1_H_PLL_BC_VAL(x) ((0x3 & (x)) << 22)
  34. #define RG_PE1_H_PLL_BP GENMASK(21, 18)
  35. #define RG_PE1_H_PLL_BP_VAL(x) ((0xf & (x)) << 18)
  36. #define RG_PE1_H_PLL_IR GENMASK(15, 12)
  37. #define RG_PE1_H_PLL_IR_VAL(x) ((0xf & (x)) << 12)
  38. #define RG_PE1_H_PLL_IC GENMASK(11, 8)
  39. #define RG_PE1_H_PLL_IC_VAL(x) ((0xf & (x)) << 8)
  40. #define RG_PE1_H_PLL_PREDIV GENMASK(7, 6)
  41. #define RG_PE1_H_PLL_PREDIV_VAL(x) ((0x3 & (x)) << 6)
  42. #define RG_PE1_PLL_DIVEN GENMASK(3, 1)
  43. #define RG_PE1_PLL_DIVEN_VAL(x) ((0x7 & (x)) << 1)
  44. #define RG_PE1_H_PLL_FBKSEL_REG 0x4bc
  45. #define RG_PE1_H_PLL_FBKSEL GENMASK(5, 4)
  46. #define RG_PE1_H_PLL_FBKSEL_VAL(x) ((0x3 & (x)) << 4)
  47. #define RG_PE1_H_LCDDS_SSC_PRD_REG 0x4a4
  48. #define RG_PE1_H_LCDDS_SSC_PRD GENMASK(15, 0)
  49. #define RG_PE1_H_LCDDS_SSC_PRD_VAL(x) ((0xffff & (x)) << 0)
  50. #define RG_PE1_H_LCDDS_SSC_DELTA_REG 0x4a8
  51. #define RG_PE1_H_LCDDS_SSC_DELTA GENMASK(11, 0)
  52. #define RG_PE1_H_LCDDS_SSC_DELTA_VAL(x) ((0xfff & (x)) << 0)
  53. #define RG_PE1_H_LCDDS_SSC_DELTA1 GENMASK(27, 16)
  54. #define RG_PE1_H_LCDDS_SSC_DELTA1_VAL(x) ((0xff & (x)) << 16)
  55. #define RG_PE1_LCDDS_CLK_PH_INV_REG 0x4a0
  56. #define RG_PE1_LCDDS_CLK_PH_INV BIT(5)
  57. #define RG_PE1_H_PLL_BR_REG 0x4ac
  58. #define RG_PE1_H_PLL_BR GENMASK(18, 16)
  59. #define RG_PE1_H_PLL_BR_VAL(x) ((0x7 & (x)) << 16)
  60. #define RG_PE1_MSTCKDIV_REG 0x414
  61. #define RG_PE1_MSTCKDIV GENMASK(7, 6)
  62. #define RG_PE1_MSTCKDIV_VAL(x) ((0x3 & (x)) << 6)
  63. #define RG_PE1_FRC_MSTCKDIV BIT(5)
  64. #define XTAL_MODE_SEL_SHIFT 6
  65. #define XTAL_MODE_SEL_MASK 0x7
  66. #define MAX_PHYS 2
  67. /**
  68. * struct mt7621_pci_phy - Mt7621 Pcie PHY core
  69. * @dev: pointer to device
  70. * @regmap: kernel regmap pointer
  71. * @phy: pointer to the kernel PHY device
  72. * @port_base: base register
  73. * @has_dual_port: if the phy has dual ports.
  74. * @bypass_pipe_rst: mark if 'mt7621_bypass_pipe_rst'
  75. * needs to be executed. Depends on chip revision.
  76. */
  77. struct mt7621_pci_phy {
  78. struct device *dev;
  79. struct regmap *regmap;
  80. struct phy *phy;
  81. void __iomem *port_base;
  82. bool has_dual_port;
  83. bool bypass_pipe_rst;
  84. };
  85. static inline u32 phy_read(struct mt7621_pci_phy *phy, u32 reg)
  86. {
  87. u32 val;
  88. regmap_read(phy->regmap, reg, &val);
  89. return val;
  90. }
  91. static inline void phy_write(struct mt7621_pci_phy *phy, u32 val, u32 reg)
  92. {
  93. regmap_write(phy->regmap, reg, val);
  94. }
  95. static inline void mt7621_phy_rmw(struct mt7621_pci_phy *phy,
  96. u32 reg, u32 clr, u32 set)
  97. {
  98. u32 val = phy_read(phy, reg);
  99. val &= ~clr;
  100. val |= set;
  101. phy_write(phy, val, reg);
  102. }
  103. static void mt7621_bypass_pipe_rst(struct mt7621_pci_phy *phy)
  104. {
  105. mt7621_phy_rmw(phy, RG_PE1_PIPE_REG, 0, RG_PE1_PIPE_RST);
  106. mt7621_phy_rmw(phy, RG_PE1_PIPE_REG, 0, RG_PE1_PIPE_CMD_FRC);
  107. if (phy->has_dual_port) {
  108. mt7621_phy_rmw(phy, RG_PE1_PIPE_REG + RG_P0_TO_P1_WIDTH,
  109. 0, RG_PE1_PIPE_RST);
  110. mt7621_phy_rmw(phy, RG_PE1_PIPE_REG + RG_P0_TO_P1_WIDTH,
  111. 0, RG_PE1_PIPE_CMD_FRC);
  112. }
  113. }
  114. static void mt7621_set_phy_for_ssc(struct mt7621_pci_phy *phy)
  115. {
  116. struct device *dev = phy->dev;
  117. u32 xtal_mode;
  118. xtal_mode = (rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0)
  119. >> XTAL_MODE_SEL_SHIFT) & XTAL_MODE_SEL_MASK;
  120. /* Set PCIe Port PHY to disable SSC */
  121. /* Debug Xtal Type */
  122. mt7621_phy_rmw(phy, RG_PE1_FRC_H_XTAL_REG,
  123. RG_PE1_FRC_H_XTAL_TYPE | RG_PE1_H_XTAL_TYPE,
  124. RG_PE1_FRC_H_XTAL_TYPE | RG_PE1_H_XTAL_TYPE_VAL(0x00));
  125. /* disable port */
  126. mt7621_phy_rmw(phy, RG_PE1_FRC_PHY_REG,
  127. RG_PE1_PHY_EN, RG_PE1_FRC_PHY_EN);
  128. if (phy->has_dual_port) {
  129. mt7621_phy_rmw(phy, RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH,
  130. RG_PE1_PHY_EN, RG_PE1_FRC_PHY_EN);
  131. }
  132. if (xtal_mode <= 5 && xtal_mode >= 3) { /* 40MHz Xtal */
  133. /* Set Pre-divider ratio (for host mode) */
  134. mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG,
  135. RG_PE1_H_PLL_PREDIV,
  136. RG_PE1_H_PLL_PREDIV_VAL(0x01));
  137. dev_info(dev, "Xtal is 40MHz\n");
  138. } else if (xtal_mode >= 6) { /* 25MHz Xal */
  139. mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG,
  140. RG_PE1_H_PLL_PREDIV,
  141. RG_PE1_H_PLL_PREDIV_VAL(0x00));
  142. /* Select feedback clock */
  143. mt7621_phy_rmw(phy, RG_PE1_H_PLL_FBKSEL_REG,
  144. RG_PE1_H_PLL_FBKSEL,
  145. RG_PE1_H_PLL_FBKSEL_VAL(0x01));
  146. /* DDS NCPO PCW (for host mode) */
  147. mt7621_phy_rmw(phy, RG_PE1_H_LCDDS_SSC_PRD_REG,
  148. RG_PE1_H_LCDDS_SSC_PRD,
  149. RG_PE1_H_LCDDS_SSC_PRD_VAL(0x18000000));
  150. /* DDS SSC dither period control */
  151. mt7621_phy_rmw(phy, RG_PE1_H_LCDDS_SSC_PRD_REG,
  152. RG_PE1_H_LCDDS_SSC_PRD,
  153. RG_PE1_H_LCDDS_SSC_PRD_VAL(0x18d));
  154. /* DDS SSC dither amplitude control */
  155. mt7621_phy_rmw(phy, RG_PE1_H_LCDDS_SSC_DELTA_REG,
  156. RG_PE1_H_LCDDS_SSC_DELTA |
  157. RG_PE1_H_LCDDS_SSC_DELTA1,
  158. RG_PE1_H_LCDDS_SSC_DELTA_VAL(0x4a) |
  159. RG_PE1_H_LCDDS_SSC_DELTA1_VAL(0x4a));
  160. dev_info(dev, "Xtal is 25MHz\n");
  161. } else { /* 20MHz Xtal */
  162. mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG,
  163. RG_PE1_H_PLL_PREDIV,
  164. RG_PE1_H_PLL_PREDIV_VAL(0x00));
  165. dev_info(dev, "Xtal is 20MHz\n");
  166. }
  167. /* DDS clock inversion */
  168. mt7621_phy_rmw(phy, RG_PE1_LCDDS_CLK_PH_INV_REG,
  169. RG_PE1_LCDDS_CLK_PH_INV, RG_PE1_LCDDS_CLK_PH_INV);
  170. /* Set PLL bits */
  171. mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG,
  172. RG_PE1_H_PLL_BC | RG_PE1_H_PLL_BP | RG_PE1_H_PLL_IR |
  173. RG_PE1_H_PLL_IC | RG_PE1_PLL_DIVEN,
  174. RG_PE1_H_PLL_BC_VAL(0x02) | RG_PE1_H_PLL_BP_VAL(0x06) |
  175. RG_PE1_H_PLL_IR_VAL(0x02) | RG_PE1_H_PLL_IC_VAL(0x01) |
  176. RG_PE1_PLL_DIVEN_VAL(0x02));
  177. mt7621_phy_rmw(phy, RG_PE1_H_PLL_BR_REG,
  178. RG_PE1_H_PLL_BR, RG_PE1_H_PLL_BR_VAL(0x00));
  179. if (xtal_mode <= 5 && xtal_mode >= 3) { /* 40MHz Xtal */
  180. /* set force mode enable of da_pe1_mstckdiv */
  181. mt7621_phy_rmw(phy, RG_PE1_MSTCKDIV_REG,
  182. RG_PE1_MSTCKDIV | RG_PE1_FRC_MSTCKDIV,
  183. RG_PE1_MSTCKDIV_VAL(0x01) | RG_PE1_FRC_MSTCKDIV);
  184. }
  185. }
  186. static int mt7621_pci_phy_init(struct phy *phy)
  187. {
  188. struct mt7621_pci_phy *mphy = phy_get_drvdata(phy);
  189. if (mphy->bypass_pipe_rst)
  190. mt7621_bypass_pipe_rst(mphy);
  191. mt7621_set_phy_for_ssc(mphy);
  192. return 0;
  193. }
  194. static int mt7621_pci_phy_power_on(struct phy *phy)
  195. {
  196. struct mt7621_pci_phy *mphy = phy_get_drvdata(phy);
  197. /* Enable PHY and disable force mode */
  198. mt7621_phy_rmw(mphy, RG_PE1_FRC_PHY_REG,
  199. RG_PE1_FRC_PHY_EN, RG_PE1_PHY_EN);
  200. if (mphy->has_dual_port) {
  201. mt7621_phy_rmw(mphy, RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH,
  202. RG_PE1_FRC_PHY_EN, RG_PE1_PHY_EN);
  203. }
  204. return 0;
  205. }
  206. static int mt7621_pci_phy_power_off(struct phy *phy)
  207. {
  208. struct mt7621_pci_phy *mphy = phy_get_drvdata(phy);
  209. /* Disable PHY */
  210. mt7621_phy_rmw(mphy, RG_PE1_FRC_PHY_REG,
  211. RG_PE1_PHY_EN, RG_PE1_FRC_PHY_EN);
  212. if (mphy->has_dual_port) {
  213. mt7621_phy_rmw(mphy, RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH,
  214. RG_PE1_PHY_EN, RG_PE1_FRC_PHY_EN);
  215. }
  216. return 0;
  217. }
  218. static int mt7621_pci_phy_exit(struct phy *phy)
  219. {
  220. return 0;
  221. }
  222. static const struct phy_ops mt7621_pci_phy_ops = {
  223. .init = mt7621_pci_phy_init,
  224. .exit = mt7621_pci_phy_exit,
  225. .power_on = mt7621_pci_phy_power_on,
  226. .power_off = mt7621_pci_phy_power_off,
  227. .owner = THIS_MODULE,
  228. };
  229. static struct phy *mt7621_pcie_phy_of_xlate(struct device *dev,
  230. struct of_phandle_args *args)
  231. {
  232. struct mt7621_pci_phy *mt7621_phy = dev_get_drvdata(dev);
  233. if (WARN_ON(args->args[0] >= MAX_PHYS))
  234. return ERR_PTR(-ENODEV);
  235. mt7621_phy->has_dual_port = args->args[0];
  236. dev_info(dev, "PHY for 0x%08x (dual port = %d)\n",
  237. (unsigned int)mt7621_phy->port_base, mt7621_phy->has_dual_port);
  238. return mt7621_phy->phy;
  239. }
  240. static const struct soc_device_attribute mt7621_pci_quirks_match[] = {
  241. { .soc_id = "mt7621", .revision = "E2" }
  242. };
  243. static const struct regmap_config mt7621_pci_phy_regmap_config = {
  244. .reg_bits = 32,
  245. .val_bits = 32,
  246. .reg_stride = 4,
  247. .max_register = 0x700,
  248. };
  249. static int mt7621_pci_phy_probe(struct platform_device *pdev)
  250. {
  251. struct device *dev = &pdev->dev;
  252. const struct soc_device_attribute *attr;
  253. struct phy_provider *provider;
  254. struct mt7621_pci_phy *phy;
  255. struct resource *res;
  256. phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
  257. if (!phy)
  258. return -ENOMEM;
  259. attr = soc_device_match(mt7621_pci_quirks_match);
  260. if (attr)
  261. phy->bypass_pipe_rst = true;
  262. phy->dev = dev;
  263. platform_set_drvdata(pdev, phy);
  264. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  265. if (!res) {
  266. dev_err(dev, "failed to get address resource\n");
  267. return -ENXIO;
  268. }
  269. phy->port_base = devm_ioremap_resource(dev, res);
  270. if (IS_ERR(phy->port_base)) {
  271. dev_err(dev, "failed to remap phy regs\n");
  272. return PTR_ERR(phy->port_base);
  273. }
  274. phy->regmap = devm_regmap_init_mmio(phy->dev, phy->port_base,
  275. &mt7621_pci_phy_regmap_config);
  276. if (IS_ERR(phy->regmap))
  277. return PTR_ERR(phy->regmap);
  278. phy->phy = devm_phy_create(dev, dev->of_node, &mt7621_pci_phy_ops);
  279. if (IS_ERR(phy)) {
  280. dev_err(dev, "failed to create phy\n");
  281. return PTR_ERR(phy);
  282. }
  283. phy_set_drvdata(phy->phy, phy);
  284. provider = devm_of_phy_provider_register(dev, mt7621_pcie_phy_of_xlate);
  285. return PTR_ERR_OR_ZERO(provider);
  286. }
  287. static const struct of_device_id mt7621_pci_phy_ids[] = {
  288. { .compatible = "mediatek,mt7621-pci-phy" },
  289. {},
  290. };
  291. MODULE_DEVICE_TABLE(of, mt7621_pci_ids);
  292. static struct platform_driver mt7621_pci_phy_driver = {
  293. .probe = mt7621_pci_phy_probe,
  294. .driver = {
  295. .name = "mt7621-pci-phy",
  296. .of_match_table = of_match_ptr(mt7621_pci_phy_ids),
  297. },
  298. };
  299. builtin_platform_driver(mt7621_pci_phy_driver);
  300. MODULE_AUTHOR("Sergio Paracuellos <sergio.paracuellos@gmail.com>");
  301. MODULE_DESCRIPTION("MediaTek MT7621 PCIe PHY driver");
  302. MODULE_LICENSE("GPL v2");