dt-binding.txt 1.0 KB

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  1. Binding for Xilinx Clocking Wizard IP Core
  2. This binding uses the common clock binding[1]. Details about the devices can be
  3. found in the product guide[2].
  4. [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
  5. [2] Clocking Wizard Product Guide
  6. https://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v5_1/pg065-clk-wiz.pdf
  7. Required properties:
  8. - compatible: Must be 'xlnx,clocking-wizard'
  9. - reg: Base and size of the cores register space
  10. - clocks: Handle to input clock
  11. - clock-names: Tuple containing 'clk_in1' and 's_axi_aclk'
  12. - clock-output-names: Names for the output clocks
  13. Optional properties:
  14. - speed-grade: Speed grade of the device (valid values are 1..3)
  15. Example:
  16. clock-generator@40040000 {
  17. reg = <0x40040000 0x1000>;
  18. compatible = "xlnx,clocking-wizard";
  19. speed-grade = <1>;
  20. clock-names = "clk_in1", "s_axi_aclk";
  21. clocks = <&clkc 15>, <&clkc 15>;
  22. clock-output-names = "clk_out0", "clk_out1", "clk_out2",
  23. "clk_out3", "clk_out4", "clk_out5",
  24. "clk_out6", "clk_out7";
  25. };