pci.c 37 KB

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  1. /*
  2. * Sonics Silicon Backplane PCI-Hostbus related functions.
  3. *
  4. * Copyright (C) 2005-2006 Michael Buesch <m@bues.ch>
  5. * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
  6. * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
  7. * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
  8. * Copyright (C) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  9. *
  10. * Derived from the Broadcom 4400 device driver.
  11. * Copyright (C) 2002 David S. Miller (davem@redhat.com)
  12. * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
  13. * Copyright (C) 2006 Broadcom Corporation.
  14. *
  15. * Licensed under the GNU/GPL. See COPYING for details.
  16. */
  17. #include "ssb_private.h"
  18. #include <linux/ssb/ssb.h>
  19. #include <linux/ssb/ssb_regs.h>
  20. #include <linux/slab.h>
  21. #include <linux/pci.h>
  22. #include <linux/delay.h>
  23. /* Define the following to 1 to enable a printk on each coreswitch. */
  24. #define SSB_VERBOSE_PCICORESWITCH_DEBUG 0
  25. /* Lowlevel coreswitching */
  26. int ssb_pci_switch_coreidx(struct ssb_bus *bus, u8 coreidx)
  27. {
  28. int err;
  29. int attempts = 0;
  30. u32 cur_core;
  31. while (1) {
  32. err = pci_write_config_dword(bus->host_pci, SSB_BAR0_WIN,
  33. (coreidx * SSB_CORE_SIZE)
  34. + SSB_ENUM_BASE);
  35. if (err)
  36. goto error;
  37. err = pci_read_config_dword(bus->host_pci, SSB_BAR0_WIN,
  38. &cur_core);
  39. if (err)
  40. goto error;
  41. cur_core = (cur_core - SSB_ENUM_BASE)
  42. / SSB_CORE_SIZE;
  43. if (cur_core == coreidx)
  44. break;
  45. if (attempts++ > SSB_BAR0_MAX_RETRIES)
  46. goto error;
  47. udelay(10);
  48. }
  49. return 0;
  50. error:
  51. pr_err("Failed to switch to core %u\n", coreidx);
  52. return -ENODEV;
  53. }
  54. int ssb_pci_switch_core(struct ssb_bus *bus,
  55. struct ssb_device *dev)
  56. {
  57. int err;
  58. unsigned long flags;
  59. #if SSB_VERBOSE_PCICORESWITCH_DEBUG
  60. pr_info("Switching to %s core, index %d\n",
  61. ssb_core_name(dev->id.coreid), dev->core_index);
  62. #endif
  63. spin_lock_irqsave(&bus->bar_lock, flags);
  64. err = ssb_pci_switch_coreidx(bus, dev->core_index);
  65. if (!err)
  66. bus->mapped_device = dev;
  67. spin_unlock_irqrestore(&bus->bar_lock, flags);
  68. return err;
  69. }
  70. /* Enable/disable the on board crystal oscillator and/or PLL. */
  71. int ssb_pci_xtal(struct ssb_bus *bus, u32 what, int turn_on)
  72. {
  73. int err;
  74. u32 in, out, outenable;
  75. u16 pci_status;
  76. if (bus->bustype != SSB_BUSTYPE_PCI)
  77. return 0;
  78. err = pci_read_config_dword(bus->host_pci, SSB_GPIO_IN, &in);
  79. if (err)
  80. goto err_pci;
  81. err = pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT, &out);
  82. if (err)
  83. goto err_pci;
  84. err = pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT_ENABLE, &outenable);
  85. if (err)
  86. goto err_pci;
  87. outenable |= what;
  88. if (turn_on) {
  89. /* Avoid glitching the clock if GPRS is already using it.
  90. * We can't actually read the state of the PLLPD so we infer it
  91. * by the value of XTAL_PU which *is* readable via gpioin.
  92. */
  93. if (!(in & SSB_GPIO_XTAL)) {
  94. if (what & SSB_GPIO_XTAL) {
  95. /* Turn the crystal on */
  96. out |= SSB_GPIO_XTAL;
  97. if (what & SSB_GPIO_PLL)
  98. out |= SSB_GPIO_PLL;
  99. err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT, out);
  100. if (err)
  101. goto err_pci;
  102. err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT_ENABLE,
  103. outenable);
  104. if (err)
  105. goto err_pci;
  106. msleep(1);
  107. }
  108. if (what & SSB_GPIO_PLL) {
  109. /* Turn the PLL on */
  110. out &= ~SSB_GPIO_PLL;
  111. err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT, out);
  112. if (err)
  113. goto err_pci;
  114. msleep(5);
  115. }
  116. }
  117. err = pci_read_config_word(bus->host_pci, PCI_STATUS, &pci_status);
  118. if (err)
  119. goto err_pci;
  120. pci_status &= ~PCI_STATUS_SIG_TARGET_ABORT;
  121. err = pci_write_config_word(bus->host_pci, PCI_STATUS, pci_status);
  122. if (err)
  123. goto err_pci;
  124. } else {
  125. if (what & SSB_GPIO_XTAL) {
  126. /* Turn the crystal off */
  127. out &= ~SSB_GPIO_XTAL;
  128. }
  129. if (what & SSB_GPIO_PLL) {
  130. /* Turn the PLL off */
  131. out |= SSB_GPIO_PLL;
  132. }
  133. err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT, out);
  134. if (err)
  135. goto err_pci;
  136. err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT_ENABLE, outenable);
  137. if (err)
  138. goto err_pci;
  139. }
  140. out:
  141. return err;
  142. err_pci:
  143. pr_err("Error: ssb_pci_xtal() could not access PCI config space!\n");
  144. err = -EBUSY;
  145. goto out;
  146. }
  147. /* Get the word-offset for a SSB_SPROM_XXX define. */
  148. #define SPOFF(offset) ((offset) / sizeof(u16))
  149. /* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
  150. #define SPEX16(_outvar, _offset, _mask, _shift) \
  151. out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
  152. #define SPEX32(_outvar, _offset, _mask, _shift) \
  153. out->_outvar = ((((u32)in[SPOFF((_offset)+2)] << 16 | \
  154. in[SPOFF(_offset)]) & (_mask)) >> (_shift))
  155. #define SPEX(_outvar, _offset, _mask, _shift) \
  156. SPEX16(_outvar, _offset, _mask, _shift)
  157. #define SPEX_ARRAY8(_field, _offset, _mask, _shift) \
  158. do { \
  159. SPEX(_field[0], _offset + 0, _mask, _shift); \
  160. SPEX(_field[1], _offset + 2, _mask, _shift); \
  161. SPEX(_field[2], _offset + 4, _mask, _shift); \
  162. SPEX(_field[3], _offset + 6, _mask, _shift); \
  163. SPEX(_field[4], _offset + 8, _mask, _shift); \
  164. SPEX(_field[5], _offset + 10, _mask, _shift); \
  165. SPEX(_field[6], _offset + 12, _mask, _shift); \
  166. SPEX(_field[7], _offset + 14, _mask, _shift); \
  167. } while (0)
  168. static inline u8 ssb_crc8(u8 crc, u8 data)
  169. {
  170. /* Polynomial: x^8 + x^7 + x^6 + x^4 + x^2 + 1 */
  171. static const u8 t[] = {
  172. 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
  173. 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
  174. 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
  175. 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
  176. 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
  177. 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
  178. 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
  179. 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
  180. 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
  181. 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
  182. 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
  183. 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
  184. 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
  185. 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
  186. 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
  187. 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
  188. 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
  189. 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
  190. 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
  191. 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
  192. 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
  193. 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
  194. 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
  195. 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
  196. 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
  197. 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
  198. 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
  199. 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
  200. 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
  201. 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
  202. 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
  203. 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F,
  204. };
  205. return t[crc ^ data];
  206. }
  207. static void sprom_get_mac(char *mac, const u16 *in)
  208. {
  209. int i;
  210. for (i = 0; i < 3; i++) {
  211. *mac++ = in[i] >> 8;
  212. *mac++ = in[i];
  213. }
  214. }
  215. static u8 ssb_sprom_crc(const u16 *sprom, u16 size)
  216. {
  217. int word;
  218. u8 crc = 0xFF;
  219. for (word = 0; word < size - 1; word++) {
  220. crc = ssb_crc8(crc, sprom[word] & 0x00FF);
  221. crc = ssb_crc8(crc, (sprom[word] & 0xFF00) >> 8);
  222. }
  223. crc = ssb_crc8(crc, sprom[size - 1] & 0x00FF);
  224. crc ^= 0xFF;
  225. return crc;
  226. }
  227. static int sprom_check_crc(const u16 *sprom, size_t size)
  228. {
  229. u8 crc;
  230. u8 expected_crc;
  231. u16 tmp;
  232. crc = ssb_sprom_crc(sprom, size);
  233. tmp = sprom[size - 1] & SSB_SPROM_REVISION_CRC;
  234. expected_crc = tmp >> SSB_SPROM_REVISION_CRC_SHIFT;
  235. if (crc != expected_crc)
  236. return -EPROTO;
  237. return 0;
  238. }
  239. static int sprom_do_read(struct ssb_bus *bus, u16 *sprom)
  240. {
  241. int i;
  242. for (i = 0; i < bus->sprom_size; i++)
  243. sprom[i] = ioread16(bus->mmio + bus->sprom_offset + (i * 2));
  244. return 0;
  245. }
  246. static int sprom_do_write(struct ssb_bus *bus, const u16 *sprom)
  247. {
  248. struct pci_dev *pdev = bus->host_pci;
  249. int i, err;
  250. u32 spromctl;
  251. u16 size = bus->sprom_size;
  252. pr_notice("Writing SPROM. Do NOT turn off the power! Please stand by...\n");
  253. err = pci_read_config_dword(pdev, SSB_SPROMCTL, &spromctl);
  254. if (err)
  255. goto err_ctlreg;
  256. spromctl |= SSB_SPROMCTL_WE;
  257. err = pci_write_config_dword(pdev, SSB_SPROMCTL, spromctl);
  258. if (err)
  259. goto err_ctlreg;
  260. pr_notice("[ 0%%");
  261. msleep(500);
  262. for (i = 0; i < size; i++) {
  263. if (i == size / 4)
  264. pr_cont("25%%");
  265. else if (i == size / 2)
  266. pr_cont("50%%");
  267. else if (i == (size * 3) / 4)
  268. pr_cont("75%%");
  269. else if (i % 2)
  270. pr_cont(".");
  271. writew(sprom[i], bus->mmio + bus->sprom_offset + (i * 2));
  272. msleep(20);
  273. }
  274. err = pci_read_config_dword(pdev, SSB_SPROMCTL, &spromctl);
  275. if (err)
  276. goto err_ctlreg;
  277. spromctl &= ~SSB_SPROMCTL_WE;
  278. err = pci_write_config_dword(pdev, SSB_SPROMCTL, spromctl);
  279. if (err)
  280. goto err_ctlreg;
  281. msleep(500);
  282. pr_cont("100%% ]\n");
  283. pr_notice("SPROM written\n");
  284. return 0;
  285. err_ctlreg:
  286. pr_err("Could not access SPROM control register.\n");
  287. return err;
  288. }
  289. static s8 sprom_extract_antgain(u8 sprom_revision, const u16 *in, u16 offset,
  290. u16 mask, u16 shift)
  291. {
  292. u16 v;
  293. u8 gain;
  294. v = in[SPOFF(offset)];
  295. gain = (v & mask) >> shift;
  296. if (gain == 0xFF)
  297. gain = 2; /* If unset use 2dBm */
  298. if (sprom_revision == 1) {
  299. /* Convert to Q5.2 */
  300. gain <<= 2;
  301. } else {
  302. /* Q5.2 Fractional part is stored in 0xC0 */
  303. gain = ((gain & 0xC0) >> 6) | ((gain & 0x3F) << 2);
  304. }
  305. return (s8)gain;
  306. }
  307. static void sprom_extract_r23(struct ssb_sprom *out, const u16 *in)
  308. {
  309. SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
  310. SPEX(opo, SSB_SPROM2_OPO, SSB_SPROM2_OPO_VALUE, 0);
  311. SPEX(pa1lob0, SSB_SPROM2_PA1LOB0, 0xFFFF, 0);
  312. SPEX(pa1lob1, SSB_SPROM2_PA1LOB1, 0xFFFF, 0);
  313. SPEX(pa1lob2, SSB_SPROM2_PA1LOB2, 0xFFFF, 0);
  314. SPEX(pa1hib0, SSB_SPROM2_PA1HIB0, 0xFFFF, 0);
  315. SPEX(pa1hib1, SSB_SPROM2_PA1HIB1, 0xFFFF, 0);
  316. SPEX(pa1hib2, SSB_SPROM2_PA1HIB2, 0xFFFF, 0);
  317. SPEX(maxpwr_ah, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_HI, 0);
  318. SPEX(maxpwr_al, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_LO,
  319. SSB_SPROM2_MAXP_A_LO_SHIFT);
  320. }
  321. static void sprom_extract_r123(struct ssb_sprom *out, const u16 *in)
  322. {
  323. u16 loc[3];
  324. if (out->revision == 3) /* rev 3 moved MAC */
  325. loc[0] = SSB_SPROM3_IL0MAC;
  326. else {
  327. loc[0] = SSB_SPROM1_IL0MAC;
  328. loc[1] = SSB_SPROM1_ET0MAC;
  329. loc[2] = SSB_SPROM1_ET1MAC;
  330. }
  331. sprom_get_mac(out->il0mac, &in[SPOFF(loc[0])]);
  332. if (out->revision < 3) { /* only rev 1-2 have et0, et1 */
  333. sprom_get_mac(out->et0mac, &in[SPOFF(loc[1])]);
  334. sprom_get_mac(out->et1mac, &in[SPOFF(loc[2])]);
  335. }
  336. SPEX(et0phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0A, 0);
  337. SPEX(et1phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1A,
  338. SSB_SPROM1_ETHPHY_ET1A_SHIFT);
  339. SPEX(et0mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0M, 14);
  340. SPEX(et1mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1M, 15);
  341. SPEX(board_rev, SSB_SPROM1_BINF, SSB_SPROM1_BINF_BREV, 0);
  342. SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
  343. if (out->revision == 1)
  344. SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
  345. SSB_SPROM1_BINF_CCODE_SHIFT);
  346. SPEX(ant_available_a, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTA,
  347. SSB_SPROM1_BINF_ANTA_SHIFT);
  348. SPEX(ant_available_bg, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTBG,
  349. SSB_SPROM1_BINF_ANTBG_SHIFT);
  350. SPEX(pa0b0, SSB_SPROM1_PA0B0, 0xFFFF, 0);
  351. SPEX(pa0b1, SSB_SPROM1_PA0B1, 0xFFFF, 0);
  352. SPEX(pa0b2, SSB_SPROM1_PA0B2, 0xFFFF, 0);
  353. SPEX(pa1b0, SSB_SPROM1_PA1B0, 0xFFFF, 0);
  354. SPEX(pa1b1, SSB_SPROM1_PA1B1, 0xFFFF, 0);
  355. SPEX(pa1b2, SSB_SPROM1_PA1B2, 0xFFFF, 0);
  356. SPEX(gpio0, SSB_SPROM1_GPIOA, SSB_SPROM1_GPIOA_P0, 0);
  357. SPEX(gpio1, SSB_SPROM1_GPIOA, SSB_SPROM1_GPIOA_P1,
  358. SSB_SPROM1_GPIOA_P1_SHIFT);
  359. SPEX(gpio2, SSB_SPROM1_GPIOB, SSB_SPROM1_GPIOB_P2, 0);
  360. SPEX(gpio3, SSB_SPROM1_GPIOB, SSB_SPROM1_GPIOB_P3,
  361. SSB_SPROM1_GPIOB_P3_SHIFT);
  362. SPEX(maxpwr_a, SSB_SPROM1_MAXPWR, SSB_SPROM1_MAXPWR_A,
  363. SSB_SPROM1_MAXPWR_A_SHIFT);
  364. SPEX(maxpwr_bg, SSB_SPROM1_MAXPWR, SSB_SPROM1_MAXPWR_BG, 0);
  365. SPEX(itssi_a, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_A,
  366. SSB_SPROM1_ITSSI_A_SHIFT);
  367. SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG, 0);
  368. SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);
  369. SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8);
  370. SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0);
  371. /* Extract the antenna gain values. */
  372. out->antenna_gain.a0 = sprom_extract_antgain(out->revision, in,
  373. SSB_SPROM1_AGAIN,
  374. SSB_SPROM1_AGAIN_BG,
  375. SSB_SPROM1_AGAIN_BG_SHIFT);
  376. out->antenna_gain.a1 = sprom_extract_antgain(out->revision, in,
  377. SSB_SPROM1_AGAIN,
  378. SSB_SPROM1_AGAIN_A,
  379. SSB_SPROM1_AGAIN_A_SHIFT);
  380. if (out->revision >= 2)
  381. sprom_extract_r23(out, in);
  382. }
  383. /* Revs 4 5 and 8 have partially shared layout */
  384. static void sprom_extract_r458(struct ssb_sprom *out, const u16 *in)
  385. {
  386. SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01,
  387. SSB_SPROM4_TXPID2G0, SSB_SPROM4_TXPID2G0_SHIFT);
  388. SPEX(txpid2g[1], SSB_SPROM4_TXPID2G01,
  389. SSB_SPROM4_TXPID2G1, SSB_SPROM4_TXPID2G1_SHIFT);
  390. SPEX(txpid2g[2], SSB_SPROM4_TXPID2G23,
  391. SSB_SPROM4_TXPID2G2, SSB_SPROM4_TXPID2G2_SHIFT);
  392. SPEX(txpid2g[3], SSB_SPROM4_TXPID2G23,
  393. SSB_SPROM4_TXPID2G3, SSB_SPROM4_TXPID2G3_SHIFT);
  394. SPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01,
  395. SSB_SPROM4_TXPID5GL0, SSB_SPROM4_TXPID5GL0_SHIFT);
  396. SPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01,
  397. SSB_SPROM4_TXPID5GL1, SSB_SPROM4_TXPID5GL1_SHIFT);
  398. SPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23,
  399. SSB_SPROM4_TXPID5GL2, SSB_SPROM4_TXPID5GL2_SHIFT);
  400. SPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23,
  401. SSB_SPROM4_TXPID5GL3, SSB_SPROM4_TXPID5GL3_SHIFT);
  402. SPEX(txpid5g[0], SSB_SPROM4_TXPID5G01,
  403. SSB_SPROM4_TXPID5G0, SSB_SPROM4_TXPID5G0_SHIFT);
  404. SPEX(txpid5g[1], SSB_SPROM4_TXPID5G01,
  405. SSB_SPROM4_TXPID5G1, SSB_SPROM4_TXPID5G1_SHIFT);
  406. SPEX(txpid5g[2], SSB_SPROM4_TXPID5G23,
  407. SSB_SPROM4_TXPID5G2, SSB_SPROM4_TXPID5G2_SHIFT);
  408. SPEX(txpid5g[3], SSB_SPROM4_TXPID5G23,
  409. SSB_SPROM4_TXPID5G3, SSB_SPROM4_TXPID5G3_SHIFT);
  410. SPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01,
  411. SSB_SPROM4_TXPID5GH0, SSB_SPROM4_TXPID5GH0_SHIFT);
  412. SPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01,
  413. SSB_SPROM4_TXPID5GH1, SSB_SPROM4_TXPID5GH1_SHIFT);
  414. SPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23,
  415. SSB_SPROM4_TXPID5GH2, SSB_SPROM4_TXPID5GH2_SHIFT);
  416. SPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23,
  417. SSB_SPROM4_TXPID5GH3, SSB_SPROM4_TXPID5GH3_SHIFT);
  418. }
  419. static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in)
  420. {
  421. static const u16 pwr_info_offset[] = {
  422. SSB_SPROM4_PWR_INFO_CORE0, SSB_SPROM4_PWR_INFO_CORE1,
  423. SSB_SPROM4_PWR_INFO_CORE2, SSB_SPROM4_PWR_INFO_CORE3
  424. };
  425. u16 il0mac_offset;
  426. int i;
  427. BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
  428. ARRAY_SIZE(out->core_pwr_info));
  429. if (out->revision == 4)
  430. il0mac_offset = SSB_SPROM4_IL0MAC;
  431. else
  432. il0mac_offset = SSB_SPROM5_IL0MAC;
  433. sprom_get_mac(out->il0mac, &in[SPOFF(il0mac_offset)]);
  434. SPEX(et0phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET0A, 0);
  435. SPEX(et1phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET1A,
  436. SSB_SPROM4_ETHPHY_ET1A_SHIFT);
  437. SPEX(board_rev, SSB_SPROM4_BOARDREV, 0xFFFF, 0);
  438. SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
  439. if (out->revision == 4) {
  440. SPEX(alpha2[0], SSB_SPROM4_CCODE, 0xff00, 8);
  441. SPEX(alpha2[1], SSB_SPROM4_CCODE, 0x00ff, 0);
  442. SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
  443. SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
  444. SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);
  445. SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);
  446. } else {
  447. SPEX(alpha2[0], SSB_SPROM5_CCODE, 0xff00, 8);
  448. SPEX(alpha2[1], SSB_SPROM5_CCODE, 0x00ff, 0);
  449. SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
  450. SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
  451. SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);
  452. SPEX(boardflags2_hi, SSB_SPROM5_BFL2HI, 0xFFFF, 0);
  453. }
  454. SPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A,
  455. SSB_SPROM4_ANTAVAIL_A_SHIFT);
  456. SPEX(ant_available_bg, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_BG,
  457. SSB_SPROM4_ANTAVAIL_BG_SHIFT);
  458. SPEX(maxpwr_bg, SSB_SPROM4_MAXP_BG, SSB_SPROM4_MAXP_BG_MASK, 0);
  459. SPEX(itssi_bg, SSB_SPROM4_MAXP_BG, SSB_SPROM4_ITSSI_BG,
  460. SSB_SPROM4_ITSSI_BG_SHIFT);
  461. SPEX(maxpwr_a, SSB_SPROM4_MAXP_A, SSB_SPROM4_MAXP_A_MASK, 0);
  462. SPEX(itssi_a, SSB_SPROM4_MAXP_A, SSB_SPROM4_ITSSI_A,
  463. SSB_SPROM4_ITSSI_A_SHIFT);
  464. if (out->revision == 4) {
  465. SPEX(gpio0, SSB_SPROM4_GPIOA, SSB_SPROM4_GPIOA_P0, 0);
  466. SPEX(gpio1, SSB_SPROM4_GPIOA, SSB_SPROM4_GPIOA_P1,
  467. SSB_SPROM4_GPIOA_P1_SHIFT);
  468. SPEX(gpio2, SSB_SPROM4_GPIOB, SSB_SPROM4_GPIOB_P2, 0);
  469. SPEX(gpio3, SSB_SPROM4_GPIOB, SSB_SPROM4_GPIOB_P3,
  470. SSB_SPROM4_GPIOB_P3_SHIFT);
  471. } else {
  472. SPEX(gpio0, SSB_SPROM5_GPIOA, SSB_SPROM5_GPIOA_P0, 0);
  473. SPEX(gpio1, SSB_SPROM5_GPIOA, SSB_SPROM5_GPIOA_P1,
  474. SSB_SPROM5_GPIOA_P1_SHIFT);
  475. SPEX(gpio2, SSB_SPROM5_GPIOB, SSB_SPROM5_GPIOB_P2, 0);
  476. SPEX(gpio3, SSB_SPROM5_GPIOB, SSB_SPROM5_GPIOB_P3,
  477. SSB_SPROM5_GPIOB_P3_SHIFT);
  478. }
  479. /* Extract the antenna gain values. */
  480. out->antenna_gain.a0 = sprom_extract_antgain(out->revision, in,
  481. SSB_SPROM4_AGAIN01,
  482. SSB_SPROM4_AGAIN0,
  483. SSB_SPROM4_AGAIN0_SHIFT);
  484. out->antenna_gain.a1 = sprom_extract_antgain(out->revision, in,
  485. SSB_SPROM4_AGAIN01,
  486. SSB_SPROM4_AGAIN1,
  487. SSB_SPROM4_AGAIN1_SHIFT);
  488. out->antenna_gain.a2 = sprom_extract_antgain(out->revision, in,
  489. SSB_SPROM4_AGAIN23,
  490. SSB_SPROM4_AGAIN2,
  491. SSB_SPROM4_AGAIN2_SHIFT);
  492. out->antenna_gain.a3 = sprom_extract_antgain(out->revision, in,
  493. SSB_SPROM4_AGAIN23,
  494. SSB_SPROM4_AGAIN3,
  495. SSB_SPROM4_AGAIN3_SHIFT);
  496. /* Extract cores power info info */
  497. for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
  498. u16 o = pwr_info_offset[i];
  499. SPEX(core_pwr_info[i].itssi_2g, o + SSB_SPROM4_2G_MAXP_ITSSI,
  500. SSB_SPROM4_2G_ITSSI, SSB_SPROM4_2G_ITSSI_SHIFT);
  501. SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SPROM4_2G_MAXP_ITSSI,
  502. SSB_SPROM4_2G_MAXP, 0);
  503. SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SPROM4_2G_PA_0, ~0, 0);
  504. SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SPROM4_2G_PA_1, ~0, 0);
  505. SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SPROM4_2G_PA_2, ~0, 0);
  506. SPEX(core_pwr_info[i].pa_2g[3], o + SSB_SPROM4_2G_PA_3, ~0, 0);
  507. SPEX(core_pwr_info[i].itssi_5g, o + SSB_SPROM4_5G_MAXP_ITSSI,
  508. SSB_SPROM4_5G_ITSSI, SSB_SPROM4_5G_ITSSI_SHIFT);
  509. SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SPROM4_5G_MAXP_ITSSI,
  510. SSB_SPROM4_5G_MAXP, 0);
  511. SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM4_5GHL_MAXP,
  512. SSB_SPROM4_5GH_MAXP, 0);
  513. SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM4_5GHL_MAXP,
  514. SSB_SPROM4_5GL_MAXP, SSB_SPROM4_5GL_MAXP_SHIFT);
  515. SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SPROM4_5GL_PA_0, ~0, 0);
  516. SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SPROM4_5GL_PA_1, ~0, 0);
  517. SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SPROM4_5GL_PA_2, ~0, 0);
  518. SPEX(core_pwr_info[i].pa_5gl[3], o + SSB_SPROM4_5GL_PA_3, ~0, 0);
  519. SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SPROM4_5G_PA_0, ~0, 0);
  520. SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SPROM4_5G_PA_1, ~0, 0);
  521. SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SPROM4_5G_PA_2, ~0, 0);
  522. SPEX(core_pwr_info[i].pa_5g[3], o + SSB_SPROM4_5G_PA_3, ~0, 0);
  523. SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SPROM4_5GH_PA_0, ~0, 0);
  524. SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SPROM4_5GH_PA_1, ~0, 0);
  525. SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SPROM4_5GH_PA_2, ~0, 0);
  526. SPEX(core_pwr_info[i].pa_5gh[3], o + SSB_SPROM4_5GH_PA_3, ~0, 0);
  527. }
  528. sprom_extract_r458(out, in);
  529. /* TODO - get remaining rev 4 stuff needed */
  530. }
  531. static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
  532. {
  533. int i;
  534. u16 o;
  535. static const u16 pwr_info_offset[] = {
  536. SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
  537. SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
  538. };
  539. BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
  540. ARRAY_SIZE(out->core_pwr_info));
  541. /* extract the MAC address */
  542. sprom_get_mac(out->il0mac, &in[SPOFF(SSB_SPROM8_IL0MAC)]);
  543. SPEX(board_rev, SSB_SPROM8_BOARDREV, 0xFFFF, 0);
  544. SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
  545. SPEX(alpha2[0], SSB_SPROM8_CCODE, 0xff00, 8);
  546. SPEX(alpha2[1], SSB_SPROM8_CCODE, 0x00ff, 0);
  547. SPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0);
  548. SPEX(boardflags_hi, SSB_SPROM8_BFLHI, 0xFFFF, 0);
  549. SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, 0xFFFF, 0);
  550. SPEX(boardflags2_hi, SSB_SPROM8_BFL2HI, 0xFFFF, 0);
  551. SPEX(ant_available_a, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_A,
  552. SSB_SPROM8_ANTAVAIL_A_SHIFT);
  553. SPEX(ant_available_bg, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_BG,
  554. SSB_SPROM8_ANTAVAIL_BG_SHIFT);
  555. SPEX(maxpwr_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_MAXP_BG_MASK, 0);
  556. SPEX(itssi_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_ITSSI_BG,
  557. SSB_SPROM8_ITSSI_BG_SHIFT);
  558. SPEX(maxpwr_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_MAXP_A_MASK, 0);
  559. SPEX(itssi_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_ITSSI_A,
  560. SSB_SPROM8_ITSSI_A_SHIFT);
  561. SPEX(maxpwr_ah, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AH_MASK, 0);
  562. SPEX(maxpwr_al, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AL_MASK,
  563. SSB_SPROM8_MAXP_AL_SHIFT);
  564. SPEX(gpio0, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P0, 0);
  565. SPEX(gpio1, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P1,
  566. SSB_SPROM8_GPIOA_P1_SHIFT);
  567. SPEX(gpio2, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P2, 0);
  568. SPEX(gpio3, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P3,
  569. SSB_SPROM8_GPIOB_P3_SHIFT);
  570. SPEX(tri2g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI2G, 0);
  571. SPEX(tri5g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI5G,
  572. SSB_SPROM8_TRI5G_SHIFT);
  573. SPEX(tri5gl, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GL, 0);
  574. SPEX(tri5gh, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GH,
  575. SSB_SPROM8_TRI5GH_SHIFT);
  576. SPEX(rxpo2g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO2G, 0);
  577. SPEX(rxpo5g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO5G,
  578. SSB_SPROM8_RXPO5G_SHIFT);
  579. SPEX(rssismf2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMF2G, 0);
  580. SPEX(rssismc2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMC2G,
  581. SSB_SPROM8_RSSISMC2G_SHIFT);
  582. SPEX(rssisav2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISAV2G,
  583. SSB_SPROM8_RSSISAV2G_SHIFT);
  584. SPEX(bxa2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_BXA2G,
  585. SSB_SPROM8_BXA2G_SHIFT);
  586. SPEX(rssismf5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMF5G, 0);
  587. SPEX(rssismc5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMC5G,
  588. SSB_SPROM8_RSSISMC5G_SHIFT);
  589. SPEX(rssisav5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISAV5G,
  590. SSB_SPROM8_RSSISAV5G_SHIFT);
  591. SPEX(bxa5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_BXA5G,
  592. SSB_SPROM8_BXA5G_SHIFT);
  593. SPEX(pa0b0, SSB_SPROM8_PA0B0, 0xFFFF, 0);
  594. SPEX(pa0b1, SSB_SPROM8_PA0B1, 0xFFFF, 0);
  595. SPEX(pa0b2, SSB_SPROM8_PA0B2, 0xFFFF, 0);
  596. SPEX(pa1b0, SSB_SPROM8_PA1B0, 0xFFFF, 0);
  597. SPEX(pa1b1, SSB_SPROM8_PA1B1, 0xFFFF, 0);
  598. SPEX(pa1b2, SSB_SPROM8_PA1B2, 0xFFFF, 0);
  599. SPEX(pa1lob0, SSB_SPROM8_PA1LOB0, 0xFFFF, 0);
  600. SPEX(pa1lob1, SSB_SPROM8_PA1LOB1, 0xFFFF, 0);
  601. SPEX(pa1lob2, SSB_SPROM8_PA1LOB2, 0xFFFF, 0);
  602. SPEX(pa1hib0, SSB_SPROM8_PA1HIB0, 0xFFFF, 0);
  603. SPEX(pa1hib1, SSB_SPROM8_PA1HIB1, 0xFFFF, 0);
  604. SPEX(pa1hib2, SSB_SPROM8_PA1HIB2, 0xFFFF, 0);
  605. SPEX(cck2gpo, SSB_SPROM8_CCK2GPO, 0xFFFF, 0);
  606. SPEX32(ofdm2gpo, SSB_SPROM8_OFDM2GPO, 0xFFFFFFFF, 0);
  607. SPEX32(ofdm5glpo, SSB_SPROM8_OFDM5GLPO, 0xFFFFFFFF, 0);
  608. SPEX32(ofdm5gpo, SSB_SPROM8_OFDM5GPO, 0xFFFFFFFF, 0);
  609. SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
  610. /* Extract the antenna gain values. */
  611. out->antenna_gain.a0 = sprom_extract_antgain(out->revision, in,
  612. SSB_SPROM8_AGAIN01,
  613. SSB_SPROM8_AGAIN0,
  614. SSB_SPROM8_AGAIN0_SHIFT);
  615. out->antenna_gain.a1 = sprom_extract_antgain(out->revision, in,
  616. SSB_SPROM8_AGAIN01,
  617. SSB_SPROM8_AGAIN1,
  618. SSB_SPROM8_AGAIN1_SHIFT);
  619. out->antenna_gain.a2 = sprom_extract_antgain(out->revision, in,
  620. SSB_SPROM8_AGAIN23,
  621. SSB_SPROM8_AGAIN2,
  622. SSB_SPROM8_AGAIN2_SHIFT);
  623. out->antenna_gain.a3 = sprom_extract_antgain(out->revision, in,
  624. SSB_SPROM8_AGAIN23,
  625. SSB_SPROM8_AGAIN3,
  626. SSB_SPROM8_AGAIN3_SHIFT);
  627. /* Extract cores power info info */
  628. for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
  629. o = pwr_info_offset[i];
  630. SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
  631. SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
  632. SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
  633. SSB_SPROM8_2G_MAXP, 0);
  634. SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
  635. SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
  636. SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
  637. SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
  638. SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
  639. SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
  640. SSB_SPROM8_5G_MAXP, 0);
  641. SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
  642. SSB_SPROM8_5GH_MAXP, 0);
  643. SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
  644. SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
  645. SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
  646. SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
  647. SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
  648. SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
  649. SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
  650. SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
  651. SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
  652. SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
  653. SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
  654. }
  655. /* Extract FEM info */
  656. SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
  657. SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
  658. SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G,
  659. SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
  660. SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G,
  661. SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
  662. SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G,
  663. SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
  664. SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G,
  665. SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
  666. SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G,
  667. SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
  668. SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G,
  669. SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
  670. SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G,
  671. SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
  672. SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G,
  673. SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
  674. SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
  675. SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
  676. SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
  677. SSB_SPROM8_LEDDC_ON_SHIFT);
  678. SPEX(leddc_off_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_OFF,
  679. SSB_SPROM8_LEDDC_OFF_SHIFT);
  680. SPEX(txchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_TXCHAIN,
  681. SSB_SPROM8_TXRXC_TXCHAIN_SHIFT);
  682. SPEX(rxchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_RXCHAIN,
  683. SSB_SPROM8_TXRXC_RXCHAIN_SHIFT);
  684. SPEX(antswitch, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_SWITCH,
  685. SSB_SPROM8_TXRXC_SWITCH_SHIFT);
  686. SPEX(opo, SSB_SPROM8_OFDM2GPO, 0x00ff, 0);
  687. SPEX_ARRAY8(mcs2gpo, SSB_SPROM8_2G_MCSPO, ~0, 0);
  688. SPEX_ARRAY8(mcs5gpo, SSB_SPROM8_5G_MCSPO, ~0, 0);
  689. SPEX_ARRAY8(mcs5glpo, SSB_SPROM8_5GL_MCSPO, ~0, 0);
  690. SPEX_ARRAY8(mcs5ghpo, SSB_SPROM8_5GH_MCSPO, ~0, 0);
  691. SPEX(rawtempsense, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_RAWTEMP,
  692. SSB_SPROM8_RAWTS_RAWTEMP_SHIFT);
  693. SPEX(measpower, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_MEASPOWER,
  694. SSB_SPROM8_RAWTS_MEASPOWER_SHIFT);
  695. SPEX(tempsense_slope, SSB_SPROM8_OPT_CORRX,
  696. SSB_SPROM8_OPT_CORRX_TEMP_SLOPE,
  697. SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT);
  698. SPEX(tempcorrx, SSB_SPROM8_OPT_CORRX, SSB_SPROM8_OPT_CORRX_TEMPCORRX,
  699. SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT);
  700. SPEX(tempsense_option, SSB_SPROM8_OPT_CORRX,
  701. SSB_SPROM8_OPT_CORRX_TEMP_OPTION,
  702. SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT);
  703. SPEX(freqoffset_corr, SSB_SPROM8_HWIQ_IQSWP,
  704. SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR,
  705. SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT);
  706. SPEX(iqcal_swp_dis, SSB_SPROM8_HWIQ_IQSWP,
  707. SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP,
  708. SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT);
  709. SPEX(hw_iqcal_en, SSB_SPROM8_HWIQ_IQSWP, SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL,
  710. SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT);
  711. SPEX(bw40po, SSB_SPROM8_BW40PO, ~0, 0);
  712. SPEX(cddpo, SSB_SPROM8_CDDPO, ~0, 0);
  713. SPEX(stbcpo, SSB_SPROM8_STBCPO, ~0, 0);
  714. SPEX(bwduppo, SSB_SPROM8_BWDUPPO, ~0, 0);
  715. SPEX(tempthresh, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_TRESH,
  716. SSB_SPROM8_THERMAL_TRESH_SHIFT);
  717. SPEX(tempoffset, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_OFFSET,
  718. SSB_SPROM8_THERMAL_OFFSET_SHIFT);
  719. SPEX(phycal_tempdelta, SSB_SPROM8_TEMPDELTA,
  720. SSB_SPROM8_TEMPDELTA_PHYCAL,
  721. SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT);
  722. SPEX(temps_period, SSB_SPROM8_TEMPDELTA, SSB_SPROM8_TEMPDELTA_PERIOD,
  723. SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT);
  724. SPEX(temps_hysteresis, SSB_SPROM8_TEMPDELTA,
  725. SSB_SPROM8_TEMPDELTA_HYSTERESIS,
  726. SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT);
  727. sprom_extract_r458(out, in);
  728. /* TODO - get remaining rev 8 stuff needed */
  729. }
  730. static int sprom_extract(struct ssb_bus *bus, struct ssb_sprom *out,
  731. const u16 *in, u16 size)
  732. {
  733. memset(out, 0, sizeof(*out));
  734. out->revision = in[size - 1] & 0x00FF;
  735. pr_debug("SPROM revision %d detected\n", out->revision);
  736. memset(out->et0mac, 0xFF, 6); /* preset et0 and et1 mac */
  737. memset(out->et1mac, 0xFF, 6);
  738. if ((bus->chip_id & 0xFF00) == 0x4400) {
  739. /* Workaround: The BCM44XX chip has a stupid revision
  740. * number stored in the SPROM.
  741. * Always extract r1. */
  742. out->revision = 1;
  743. pr_debug("SPROM treated as revision %d\n", out->revision);
  744. }
  745. switch (out->revision) {
  746. case 1:
  747. case 2:
  748. case 3:
  749. sprom_extract_r123(out, in);
  750. break;
  751. case 4:
  752. case 5:
  753. sprom_extract_r45(out, in);
  754. break;
  755. case 8:
  756. sprom_extract_r8(out, in);
  757. break;
  758. default:
  759. pr_warn("Unsupported SPROM revision %d detected. Will extract v1\n",
  760. out->revision);
  761. out->revision = 1;
  762. sprom_extract_r123(out, in);
  763. }
  764. if (out->boardflags_lo == 0xFFFF)
  765. out->boardflags_lo = 0; /* per specs */
  766. if (out->boardflags_hi == 0xFFFF)
  767. out->boardflags_hi = 0; /* per specs */
  768. return 0;
  769. }
  770. static int ssb_pci_sprom_get(struct ssb_bus *bus,
  771. struct ssb_sprom *sprom)
  772. {
  773. int err;
  774. u16 *buf;
  775. if (!ssb_is_sprom_available(bus)) {
  776. pr_err("No SPROM available!\n");
  777. return -ENODEV;
  778. }
  779. if (bus->chipco.dev) { /* can be unavailable! */
  780. /*
  781. * get SPROM offset: SSB_SPROM_BASE1 except for
  782. * chipcommon rev >= 31 or chip ID is 0x4312 and
  783. * chipcommon status & 3 == 2
  784. */
  785. if (bus->chipco.dev->id.revision >= 31)
  786. bus->sprom_offset = SSB_SPROM_BASE31;
  787. else if (bus->chip_id == 0x4312 &&
  788. (bus->chipco.status & 0x03) == 2)
  789. bus->sprom_offset = SSB_SPROM_BASE31;
  790. else
  791. bus->sprom_offset = SSB_SPROM_BASE1;
  792. } else {
  793. bus->sprom_offset = SSB_SPROM_BASE1;
  794. }
  795. pr_debug("SPROM offset is 0x%x\n", bus->sprom_offset);
  796. buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
  797. if (!buf)
  798. return -ENOMEM;
  799. bus->sprom_size = SSB_SPROMSIZE_WORDS_R123;
  800. sprom_do_read(bus, buf);
  801. err = sprom_check_crc(buf, bus->sprom_size);
  802. if (err) {
  803. /* try for a 440 byte SPROM - revision 4 and higher */
  804. kfree(buf);
  805. buf = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
  806. GFP_KERNEL);
  807. if (!buf)
  808. return -ENOMEM;
  809. bus->sprom_size = SSB_SPROMSIZE_WORDS_R4;
  810. sprom_do_read(bus, buf);
  811. err = sprom_check_crc(buf, bus->sprom_size);
  812. if (err) {
  813. /* All CRC attempts failed.
  814. * Maybe there is no SPROM on the device?
  815. * Now we ask the arch code if there is some sprom
  816. * available for this device in some other storage */
  817. err = ssb_fill_sprom_with_fallback(bus, sprom);
  818. if (err) {
  819. pr_warn("WARNING: Using fallback SPROM failed (err %d)\n",
  820. err);
  821. goto out_free;
  822. } else {
  823. pr_debug("Using SPROM revision %d provided by platform\n",
  824. sprom->revision);
  825. err = 0;
  826. goto out_free;
  827. }
  828. pr_warn("WARNING: Invalid SPROM CRC (corrupt SPROM)\n");
  829. }
  830. }
  831. err = sprom_extract(bus, sprom, buf, bus->sprom_size);
  832. out_free:
  833. kfree(buf);
  834. return err;
  835. }
  836. static void ssb_pci_get_boardinfo(struct ssb_bus *bus,
  837. struct ssb_boardinfo *bi)
  838. {
  839. bi->vendor = bus->host_pci->subsystem_vendor;
  840. bi->type = bus->host_pci->subsystem_device;
  841. }
  842. int ssb_pci_get_invariants(struct ssb_bus *bus,
  843. struct ssb_init_invariants *iv)
  844. {
  845. int err;
  846. err = ssb_pci_sprom_get(bus, &iv->sprom);
  847. if (err)
  848. goto out;
  849. ssb_pci_get_boardinfo(bus, &iv->boardinfo);
  850. out:
  851. return err;
  852. }
  853. static int ssb_pci_assert_buspower(struct ssb_bus *bus)
  854. {
  855. if (likely(bus->powered_up))
  856. return 0;
  857. pr_err("FATAL ERROR: Bus powered down while accessing PCI MMIO space\n");
  858. if (bus->power_warn_count <= 10) {
  859. bus->power_warn_count++;
  860. dump_stack();
  861. }
  862. return -ENODEV;
  863. }
  864. static u8 ssb_pci_read8(struct ssb_device *dev, u16 offset)
  865. {
  866. struct ssb_bus *bus = dev->bus;
  867. if (unlikely(ssb_pci_assert_buspower(bus)))
  868. return 0xFF;
  869. if (unlikely(bus->mapped_device != dev)) {
  870. if (unlikely(ssb_pci_switch_core(bus, dev)))
  871. return 0xFF;
  872. }
  873. return ioread8(bus->mmio + offset);
  874. }
  875. static u16 ssb_pci_read16(struct ssb_device *dev, u16 offset)
  876. {
  877. struct ssb_bus *bus = dev->bus;
  878. if (unlikely(ssb_pci_assert_buspower(bus)))
  879. return 0xFFFF;
  880. if (unlikely(bus->mapped_device != dev)) {
  881. if (unlikely(ssb_pci_switch_core(bus, dev)))
  882. return 0xFFFF;
  883. }
  884. return ioread16(bus->mmio + offset);
  885. }
  886. static u32 ssb_pci_read32(struct ssb_device *dev, u16 offset)
  887. {
  888. struct ssb_bus *bus = dev->bus;
  889. if (unlikely(ssb_pci_assert_buspower(bus)))
  890. return 0xFFFFFFFF;
  891. if (unlikely(bus->mapped_device != dev)) {
  892. if (unlikely(ssb_pci_switch_core(bus, dev)))
  893. return 0xFFFFFFFF;
  894. }
  895. return ioread32(bus->mmio + offset);
  896. }
  897. #ifdef CONFIG_SSB_BLOCKIO
  898. static void ssb_pci_block_read(struct ssb_device *dev, void *buffer,
  899. size_t count, u16 offset, u8 reg_width)
  900. {
  901. struct ssb_bus *bus = dev->bus;
  902. void __iomem *addr = bus->mmio + offset;
  903. if (unlikely(ssb_pci_assert_buspower(bus)))
  904. goto error;
  905. if (unlikely(bus->mapped_device != dev)) {
  906. if (unlikely(ssb_pci_switch_core(bus, dev)))
  907. goto error;
  908. }
  909. switch (reg_width) {
  910. case sizeof(u8):
  911. ioread8_rep(addr, buffer, count);
  912. break;
  913. case sizeof(u16):
  914. WARN_ON(count & 1);
  915. ioread16_rep(addr, buffer, count >> 1);
  916. break;
  917. case sizeof(u32):
  918. WARN_ON(count & 3);
  919. ioread32_rep(addr, buffer, count >> 2);
  920. break;
  921. default:
  922. WARN_ON(1);
  923. }
  924. return;
  925. error:
  926. memset(buffer, 0xFF, count);
  927. }
  928. #endif /* CONFIG_SSB_BLOCKIO */
  929. static void ssb_pci_write8(struct ssb_device *dev, u16 offset, u8 value)
  930. {
  931. struct ssb_bus *bus = dev->bus;
  932. if (unlikely(ssb_pci_assert_buspower(bus)))
  933. return;
  934. if (unlikely(bus->mapped_device != dev)) {
  935. if (unlikely(ssb_pci_switch_core(bus, dev)))
  936. return;
  937. }
  938. iowrite8(value, bus->mmio + offset);
  939. }
  940. static void ssb_pci_write16(struct ssb_device *dev, u16 offset, u16 value)
  941. {
  942. struct ssb_bus *bus = dev->bus;
  943. if (unlikely(ssb_pci_assert_buspower(bus)))
  944. return;
  945. if (unlikely(bus->mapped_device != dev)) {
  946. if (unlikely(ssb_pci_switch_core(bus, dev)))
  947. return;
  948. }
  949. iowrite16(value, bus->mmio + offset);
  950. }
  951. static void ssb_pci_write32(struct ssb_device *dev, u16 offset, u32 value)
  952. {
  953. struct ssb_bus *bus = dev->bus;
  954. if (unlikely(ssb_pci_assert_buspower(bus)))
  955. return;
  956. if (unlikely(bus->mapped_device != dev)) {
  957. if (unlikely(ssb_pci_switch_core(bus, dev)))
  958. return;
  959. }
  960. iowrite32(value, bus->mmio + offset);
  961. }
  962. #ifdef CONFIG_SSB_BLOCKIO
  963. static void ssb_pci_block_write(struct ssb_device *dev, const void *buffer,
  964. size_t count, u16 offset, u8 reg_width)
  965. {
  966. struct ssb_bus *bus = dev->bus;
  967. void __iomem *addr = bus->mmio + offset;
  968. if (unlikely(ssb_pci_assert_buspower(bus)))
  969. return;
  970. if (unlikely(bus->mapped_device != dev)) {
  971. if (unlikely(ssb_pci_switch_core(bus, dev)))
  972. return;
  973. }
  974. switch (reg_width) {
  975. case sizeof(u8):
  976. iowrite8_rep(addr, buffer, count);
  977. break;
  978. case sizeof(u16):
  979. WARN_ON(count & 1);
  980. iowrite16_rep(addr, buffer, count >> 1);
  981. break;
  982. case sizeof(u32):
  983. WARN_ON(count & 3);
  984. iowrite32_rep(addr, buffer, count >> 2);
  985. break;
  986. default:
  987. WARN_ON(1);
  988. }
  989. }
  990. #endif /* CONFIG_SSB_BLOCKIO */
  991. /* Not "static", as it's used in main.c */
  992. const struct ssb_bus_ops ssb_pci_ops = {
  993. .read8 = ssb_pci_read8,
  994. .read16 = ssb_pci_read16,
  995. .read32 = ssb_pci_read32,
  996. .write8 = ssb_pci_write8,
  997. .write16 = ssb_pci_write16,
  998. .write32 = ssb_pci_write32,
  999. #ifdef CONFIG_SSB_BLOCKIO
  1000. .block_read = ssb_pci_block_read,
  1001. .block_write = ssb_pci_block_write,
  1002. #endif
  1003. };
  1004. static ssize_t ssb_pci_attr_sprom_show(struct device *pcidev,
  1005. struct device_attribute *attr,
  1006. char *buf)
  1007. {
  1008. struct pci_dev *pdev = container_of(pcidev, struct pci_dev, dev);
  1009. struct ssb_bus *bus;
  1010. bus = ssb_pci_dev_to_bus(pdev);
  1011. if (!bus)
  1012. return -ENODEV;
  1013. return ssb_attr_sprom_show(bus, buf, sprom_do_read);
  1014. }
  1015. static ssize_t ssb_pci_attr_sprom_store(struct device *pcidev,
  1016. struct device_attribute *attr,
  1017. const char *buf, size_t count)
  1018. {
  1019. struct pci_dev *pdev = container_of(pcidev, struct pci_dev, dev);
  1020. struct ssb_bus *bus;
  1021. bus = ssb_pci_dev_to_bus(pdev);
  1022. if (!bus)
  1023. return -ENODEV;
  1024. return ssb_attr_sprom_store(bus, buf, count,
  1025. sprom_check_crc, sprom_do_write);
  1026. }
  1027. static DEVICE_ATTR(ssb_sprom, 0600,
  1028. ssb_pci_attr_sprom_show,
  1029. ssb_pci_attr_sprom_store);
  1030. void ssb_pci_exit(struct ssb_bus *bus)
  1031. {
  1032. struct pci_dev *pdev;
  1033. if (bus->bustype != SSB_BUSTYPE_PCI)
  1034. return;
  1035. pdev = bus->host_pci;
  1036. device_remove_file(&pdev->dev, &dev_attr_ssb_sprom);
  1037. }
  1038. int ssb_pci_init(struct ssb_bus *bus)
  1039. {
  1040. struct pci_dev *pdev;
  1041. if (bus->bustype != SSB_BUSTYPE_PCI)
  1042. return 0;
  1043. pdev = bus->host_pci;
  1044. mutex_init(&bus->sprom_mutex);
  1045. return device_create_file(&pdev->dev, &dev_attr_ssb_sprom);
  1046. }