main.c 30 KB

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  1. /*
  2. * Sonics Silicon Backplane
  3. * Subsystem core
  4. *
  5. * Copyright 2005, Broadcom Corporation
  6. * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
  7. *
  8. * Licensed under the GNU/GPL. See COPYING for details.
  9. */
  10. #include "ssb_private.h"
  11. #include <linux/delay.h>
  12. #include <linux/io.h>
  13. #include <linux/module.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/ssb/ssb.h>
  16. #include <linux/ssb/ssb_regs.h>
  17. #include <linux/ssb/ssb_driver_gige.h>
  18. #include <linux/dma-mapping.h>
  19. #include <linux/pci.h>
  20. #include <linux/mmc/sdio_func.h>
  21. #include <linux/slab.h>
  22. #include <pcmcia/cistpl.h>
  23. #include <pcmcia/ds.h>
  24. MODULE_DESCRIPTION("Sonics Silicon Backplane driver");
  25. MODULE_LICENSE("GPL");
  26. /* Temporary list of yet-to-be-attached buses */
  27. static LIST_HEAD(attach_queue);
  28. /* List if running buses */
  29. static LIST_HEAD(buses);
  30. /* Software ID counter */
  31. static unsigned int next_busnumber;
  32. /* buses_mutes locks the two buslists and the next_busnumber.
  33. * Don't lock this directly, but use ssb_buses_[un]lock() below. */
  34. static DEFINE_MUTEX(buses_mutex);
  35. /* There are differences in the codeflow, if the bus is
  36. * initialized from early boot, as various needed services
  37. * are not available early. This is a mechanism to delay
  38. * these initializations to after early boot has finished.
  39. * It's also used to avoid mutex locking, as that's not
  40. * available and needed early. */
  41. static bool ssb_is_early_boot = 1;
  42. static void ssb_buses_lock(void);
  43. static void ssb_buses_unlock(void);
  44. #ifdef CONFIG_SSB_PCIHOST
  45. struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev)
  46. {
  47. struct ssb_bus *bus;
  48. ssb_buses_lock();
  49. list_for_each_entry(bus, &buses, list) {
  50. if (bus->bustype == SSB_BUSTYPE_PCI &&
  51. bus->host_pci == pdev)
  52. goto found;
  53. }
  54. bus = NULL;
  55. found:
  56. ssb_buses_unlock();
  57. return bus;
  58. }
  59. #endif /* CONFIG_SSB_PCIHOST */
  60. #ifdef CONFIG_SSB_PCMCIAHOST
  61. struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev)
  62. {
  63. struct ssb_bus *bus;
  64. ssb_buses_lock();
  65. list_for_each_entry(bus, &buses, list) {
  66. if (bus->bustype == SSB_BUSTYPE_PCMCIA &&
  67. bus->host_pcmcia == pdev)
  68. goto found;
  69. }
  70. bus = NULL;
  71. found:
  72. ssb_buses_unlock();
  73. return bus;
  74. }
  75. #endif /* CONFIG_SSB_PCMCIAHOST */
  76. int ssb_for_each_bus_call(unsigned long data,
  77. int (*func)(struct ssb_bus *bus, unsigned long data))
  78. {
  79. struct ssb_bus *bus;
  80. int res;
  81. ssb_buses_lock();
  82. list_for_each_entry(bus, &buses, list) {
  83. res = func(bus, data);
  84. if (res >= 0) {
  85. ssb_buses_unlock();
  86. return res;
  87. }
  88. }
  89. ssb_buses_unlock();
  90. return -ENODEV;
  91. }
  92. static struct ssb_device *ssb_device_get(struct ssb_device *dev)
  93. {
  94. if (dev)
  95. get_device(dev->dev);
  96. return dev;
  97. }
  98. static void ssb_device_put(struct ssb_device *dev)
  99. {
  100. if (dev)
  101. put_device(dev->dev);
  102. }
  103. static int ssb_device_resume(struct device *dev)
  104. {
  105. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  106. struct ssb_driver *ssb_drv;
  107. int err = 0;
  108. if (dev->driver) {
  109. ssb_drv = drv_to_ssb_drv(dev->driver);
  110. if (ssb_drv && ssb_drv->resume)
  111. err = ssb_drv->resume(ssb_dev);
  112. if (err)
  113. goto out;
  114. }
  115. out:
  116. return err;
  117. }
  118. static int ssb_device_suspend(struct device *dev, pm_message_t state)
  119. {
  120. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  121. struct ssb_driver *ssb_drv;
  122. int err = 0;
  123. if (dev->driver) {
  124. ssb_drv = drv_to_ssb_drv(dev->driver);
  125. if (ssb_drv && ssb_drv->suspend)
  126. err = ssb_drv->suspend(ssb_dev, state);
  127. if (err)
  128. goto out;
  129. }
  130. out:
  131. return err;
  132. }
  133. int ssb_bus_resume(struct ssb_bus *bus)
  134. {
  135. int err;
  136. /* Reset HW state information in memory, so that HW is
  137. * completely reinitialized. */
  138. bus->mapped_device = NULL;
  139. #ifdef CONFIG_SSB_DRIVER_PCICORE
  140. bus->pcicore.setup_done = 0;
  141. #endif
  142. err = ssb_bus_powerup(bus, 0);
  143. if (err)
  144. return err;
  145. err = ssb_pcmcia_hardware_setup(bus);
  146. if (err) {
  147. ssb_bus_may_powerdown(bus);
  148. return err;
  149. }
  150. ssb_chipco_resume(&bus->chipco);
  151. ssb_bus_may_powerdown(bus);
  152. return 0;
  153. }
  154. EXPORT_SYMBOL(ssb_bus_resume);
  155. int ssb_bus_suspend(struct ssb_bus *bus)
  156. {
  157. ssb_chipco_suspend(&bus->chipco);
  158. ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
  159. return 0;
  160. }
  161. EXPORT_SYMBOL(ssb_bus_suspend);
  162. #ifdef CONFIG_SSB_SPROM
  163. /** ssb_devices_freeze - Freeze all devices on the bus.
  164. *
  165. * After freezing no device driver will be handling a device
  166. * on this bus anymore. ssb_devices_thaw() must be called after
  167. * a successful freeze to reactivate the devices.
  168. *
  169. * @bus: The bus.
  170. * @ctx: Context structure. Pass this to ssb_devices_thaw().
  171. */
  172. int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx)
  173. {
  174. struct ssb_device *sdev;
  175. struct ssb_driver *sdrv;
  176. unsigned int i;
  177. memset(ctx, 0, sizeof(*ctx));
  178. ctx->bus = bus;
  179. WARN_ON(bus->nr_devices > ARRAY_SIZE(ctx->device_frozen));
  180. for (i = 0; i < bus->nr_devices; i++) {
  181. sdev = ssb_device_get(&bus->devices[i]);
  182. if (!sdev->dev || !sdev->dev->driver ||
  183. !device_is_registered(sdev->dev)) {
  184. ssb_device_put(sdev);
  185. continue;
  186. }
  187. sdrv = drv_to_ssb_drv(sdev->dev->driver);
  188. if (WARN_ON(!sdrv->remove))
  189. continue;
  190. sdrv->remove(sdev);
  191. ctx->device_frozen[i] = 1;
  192. }
  193. return 0;
  194. }
  195. /** ssb_devices_thaw - Unfreeze all devices on the bus.
  196. *
  197. * This will re-attach the device drivers and re-init the devices.
  198. *
  199. * @ctx: The context structure from ssb_devices_freeze()
  200. */
  201. int ssb_devices_thaw(struct ssb_freeze_context *ctx)
  202. {
  203. struct ssb_bus *bus = ctx->bus;
  204. struct ssb_device *sdev;
  205. struct ssb_driver *sdrv;
  206. unsigned int i;
  207. int err, result = 0;
  208. for (i = 0; i < bus->nr_devices; i++) {
  209. if (!ctx->device_frozen[i])
  210. continue;
  211. sdev = &bus->devices[i];
  212. if (WARN_ON(!sdev->dev || !sdev->dev->driver))
  213. continue;
  214. sdrv = drv_to_ssb_drv(sdev->dev->driver);
  215. if (WARN_ON(!sdrv || !sdrv->probe))
  216. continue;
  217. err = sdrv->probe(sdev, &sdev->id);
  218. if (err) {
  219. dev_err(sdev->dev,
  220. "Failed to thaw device %s\n",
  221. dev_name(sdev->dev));
  222. result = err;
  223. }
  224. ssb_device_put(sdev);
  225. }
  226. return result;
  227. }
  228. #endif /* CONFIG_SSB_SPROM */
  229. static void ssb_device_shutdown(struct device *dev)
  230. {
  231. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  232. struct ssb_driver *ssb_drv;
  233. if (!dev->driver)
  234. return;
  235. ssb_drv = drv_to_ssb_drv(dev->driver);
  236. if (ssb_drv && ssb_drv->shutdown)
  237. ssb_drv->shutdown(ssb_dev);
  238. }
  239. static int ssb_device_remove(struct device *dev)
  240. {
  241. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  242. struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
  243. if (ssb_drv && ssb_drv->remove)
  244. ssb_drv->remove(ssb_dev);
  245. ssb_device_put(ssb_dev);
  246. return 0;
  247. }
  248. static int ssb_device_probe(struct device *dev)
  249. {
  250. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  251. struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
  252. int err = 0;
  253. ssb_device_get(ssb_dev);
  254. if (ssb_drv && ssb_drv->probe)
  255. err = ssb_drv->probe(ssb_dev, &ssb_dev->id);
  256. if (err)
  257. ssb_device_put(ssb_dev);
  258. return err;
  259. }
  260. static int ssb_match_devid(const struct ssb_device_id *tabid,
  261. const struct ssb_device_id *devid)
  262. {
  263. if ((tabid->vendor != devid->vendor) &&
  264. tabid->vendor != SSB_ANY_VENDOR)
  265. return 0;
  266. if ((tabid->coreid != devid->coreid) &&
  267. tabid->coreid != SSB_ANY_ID)
  268. return 0;
  269. if ((tabid->revision != devid->revision) &&
  270. tabid->revision != SSB_ANY_REV)
  271. return 0;
  272. return 1;
  273. }
  274. static int ssb_bus_match(struct device *dev, struct device_driver *drv)
  275. {
  276. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  277. struct ssb_driver *ssb_drv = drv_to_ssb_drv(drv);
  278. const struct ssb_device_id *id;
  279. for (id = ssb_drv->id_table;
  280. id->vendor || id->coreid || id->revision;
  281. id++) {
  282. if (ssb_match_devid(id, &ssb_dev->id))
  283. return 1; /* found */
  284. }
  285. return 0;
  286. }
  287. static int ssb_device_uevent(struct device *dev, struct kobj_uevent_env *env)
  288. {
  289. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  290. if (!dev)
  291. return -ENODEV;
  292. return add_uevent_var(env,
  293. "MODALIAS=ssb:v%04Xid%04Xrev%02X",
  294. ssb_dev->id.vendor, ssb_dev->id.coreid,
  295. ssb_dev->id.revision);
  296. }
  297. #define ssb_config_attr(attrib, field, format_string) \
  298. static ssize_t \
  299. attrib##_show(struct device *dev, struct device_attribute *attr, char *buf) \
  300. { \
  301. return sprintf(buf, format_string, dev_to_ssb_dev(dev)->field); \
  302. } \
  303. static DEVICE_ATTR_RO(attrib);
  304. ssb_config_attr(core_num, core_index, "%u\n")
  305. ssb_config_attr(coreid, id.coreid, "0x%04x\n")
  306. ssb_config_attr(vendor, id.vendor, "0x%04x\n")
  307. ssb_config_attr(revision, id.revision, "%u\n")
  308. ssb_config_attr(irq, irq, "%u\n")
  309. static ssize_t
  310. name_show(struct device *dev, struct device_attribute *attr, char *buf)
  311. {
  312. return sprintf(buf, "%s\n",
  313. ssb_core_name(dev_to_ssb_dev(dev)->id.coreid));
  314. }
  315. static DEVICE_ATTR_RO(name);
  316. static struct attribute *ssb_device_attrs[] = {
  317. &dev_attr_name.attr,
  318. &dev_attr_core_num.attr,
  319. &dev_attr_coreid.attr,
  320. &dev_attr_vendor.attr,
  321. &dev_attr_revision.attr,
  322. &dev_attr_irq.attr,
  323. NULL,
  324. };
  325. ATTRIBUTE_GROUPS(ssb_device);
  326. static struct bus_type ssb_bustype = {
  327. .name = "ssb",
  328. .match = ssb_bus_match,
  329. .probe = ssb_device_probe,
  330. .remove = ssb_device_remove,
  331. .shutdown = ssb_device_shutdown,
  332. .suspend = ssb_device_suspend,
  333. .resume = ssb_device_resume,
  334. .uevent = ssb_device_uevent,
  335. .dev_groups = ssb_device_groups,
  336. };
  337. static void ssb_buses_lock(void)
  338. {
  339. /* See the comment at the ssb_is_early_boot definition */
  340. if (!ssb_is_early_boot)
  341. mutex_lock(&buses_mutex);
  342. }
  343. static void ssb_buses_unlock(void)
  344. {
  345. /* See the comment at the ssb_is_early_boot definition */
  346. if (!ssb_is_early_boot)
  347. mutex_unlock(&buses_mutex);
  348. }
  349. static void ssb_devices_unregister(struct ssb_bus *bus)
  350. {
  351. struct ssb_device *sdev;
  352. int i;
  353. for (i = bus->nr_devices - 1; i >= 0; i--) {
  354. sdev = &(bus->devices[i]);
  355. if (sdev->dev)
  356. device_unregister(sdev->dev);
  357. }
  358. #ifdef CONFIG_SSB_EMBEDDED
  359. if (bus->bustype == SSB_BUSTYPE_SSB)
  360. platform_device_unregister(bus->watchdog);
  361. #endif
  362. }
  363. void ssb_bus_unregister(struct ssb_bus *bus)
  364. {
  365. int err;
  366. err = ssb_gpio_unregister(bus);
  367. if (err == -EBUSY)
  368. pr_debug("Some GPIOs are still in use\n");
  369. else if (err)
  370. pr_debug("Can not unregister GPIO driver: %i\n", err);
  371. ssb_buses_lock();
  372. ssb_devices_unregister(bus);
  373. list_del(&bus->list);
  374. ssb_buses_unlock();
  375. ssb_pcmcia_exit(bus);
  376. ssb_pci_exit(bus);
  377. ssb_iounmap(bus);
  378. }
  379. EXPORT_SYMBOL(ssb_bus_unregister);
  380. static void ssb_release_dev(struct device *dev)
  381. {
  382. struct __ssb_dev_wrapper *devwrap;
  383. devwrap = container_of(dev, struct __ssb_dev_wrapper, dev);
  384. kfree(devwrap);
  385. }
  386. static int ssb_devices_register(struct ssb_bus *bus)
  387. {
  388. struct ssb_device *sdev;
  389. struct device *dev;
  390. struct __ssb_dev_wrapper *devwrap;
  391. int i, err = 0;
  392. int dev_idx = 0;
  393. for (i = 0; i < bus->nr_devices; i++) {
  394. sdev = &(bus->devices[i]);
  395. /* We don't register SSB-system devices to the kernel,
  396. * as the drivers for them are built into SSB. */
  397. switch (sdev->id.coreid) {
  398. case SSB_DEV_CHIPCOMMON:
  399. case SSB_DEV_PCI:
  400. case SSB_DEV_PCIE:
  401. case SSB_DEV_PCMCIA:
  402. case SSB_DEV_MIPS:
  403. case SSB_DEV_MIPS_3302:
  404. case SSB_DEV_EXTIF:
  405. continue;
  406. }
  407. devwrap = kzalloc(sizeof(*devwrap), GFP_KERNEL);
  408. if (!devwrap) {
  409. err = -ENOMEM;
  410. goto error;
  411. }
  412. dev = &devwrap->dev;
  413. devwrap->sdev = sdev;
  414. dev->release = ssb_release_dev;
  415. dev->bus = &ssb_bustype;
  416. dev_set_name(dev, "ssb%u:%d", bus->busnumber, dev_idx);
  417. switch (bus->bustype) {
  418. case SSB_BUSTYPE_PCI:
  419. #ifdef CONFIG_SSB_PCIHOST
  420. sdev->irq = bus->host_pci->irq;
  421. dev->parent = &bus->host_pci->dev;
  422. sdev->dma_dev = dev->parent;
  423. #endif
  424. break;
  425. case SSB_BUSTYPE_PCMCIA:
  426. #ifdef CONFIG_SSB_PCMCIAHOST
  427. sdev->irq = bus->host_pcmcia->irq;
  428. dev->parent = &bus->host_pcmcia->dev;
  429. #endif
  430. break;
  431. case SSB_BUSTYPE_SDIO:
  432. #ifdef CONFIG_SSB_SDIOHOST
  433. dev->parent = &bus->host_sdio->dev;
  434. #endif
  435. break;
  436. case SSB_BUSTYPE_SSB:
  437. dev->dma_mask = &dev->coherent_dma_mask;
  438. sdev->dma_dev = dev;
  439. break;
  440. }
  441. sdev->dev = dev;
  442. err = device_register(dev);
  443. if (err) {
  444. pr_err("Could not register %s\n", dev_name(dev));
  445. /* Set dev to NULL to not unregister
  446. * dev on error unwinding. */
  447. sdev->dev = NULL;
  448. put_device(dev);
  449. goto error;
  450. }
  451. dev_idx++;
  452. }
  453. #ifdef CONFIG_SSB_DRIVER_MIPS
  454. if (bus->mipscore.pflash.present) {
  455. err = platform_device_register(&ssb_pflash_dev);
  456. if (err)
  457. pr_err("Error registering parallel flash\n");
  458. }
  459. #endif
  460. #ifdef CONFIG_SSB_SFLASH
  461. if (bus->mipscore.sflash.present) {
  462. err = platform_device_register(&ssb_sflash_dev);
  463. if (err)
  464. pr_err("Error registering serial flash\n");
  465. }
  466. #endif
  467. return 0;
  468. error:
  469. /* Unwind the already registered devices. */
  470. ssb_devices_unregister(bus);
  471. return err;
  472. }
  473. /* Needs ssb_buses_lock() */
  474. static int ssb_attach_queued_buses(void)
  475. {
  476. struct ssb_bus *bus, *n;
  477. int err = 0;
  478. int drop_them_all = 0;
  479. list_for_each_entry_safe(bus, n, &attach_queue, list) {
  480. if (drop_them_all) {
  481. list_del(&bus->list);
  482. continue;
  483. }
  484. /* Can't init the PCIcore in ssb_bus_register(), as that
  485. * is too early in boot for embedded systems
  486. * (no udelay() available). So do it here in attach stage.
  487. */
  488. err = ssb_bus_powerup(bus, 0);
  489. if (err)
  490. goto error;
  491. ssb_pcicore_init(&bus->pcicore);
  492. if (bus->bustype == SSB_BUSTYPE_SSB)
  493. ssb_watchdog_register(bus);
  494. err = ssb_gpio_init(bus);
  495. if (err == -ENOTSUPP)
  496. pr_debug("GPIO driver not activated\n");
  497. else if (err)
  498. pr_debug("Error registering GPIO driver: %i\n", err);
  499. ssb_bus_may_powerdown(bus);
  500. err = ssb_devices_register(bus);
  501. error:
  502. if (err) {
  503. drop_them_all = 1;
  504. list_del(&bus->list);
  505. continue;
  506. }
  507. list_move_tail(&bus->list, &buses);
  508. }
  509. return err;
  510. }
  511. static int ssb_fetch_invariants(struct ssb_bus *bus,
  512. ssb_invariants_func_t get_invariants)
  513. {
  514. struct ssb_init_invariants iv;
  515. int err;
  516. memset(&iv, 0, sizeof(iv));
  517. err = get_invariants(bus, &iv);
  518. if (err)
  519. goto out;
  520. memcpy(&bus->boardinfo, &iv.boardinfo, sizeof(iv.boardinfo));
  521. memcpy(&bus->sprom, &iv.sprom, sizeof(iv.sprom));
  522. bus->has_cardbus_slot = iv.has_cardbus_slot;
  523. out:
  524. return err;
  525. }
  526. static int __maybe_unused
  527. ssb_bus_register(struct ssb_bus *bus,
  528. ssb_invariants_func_t get_invariants,
  529. unsigned long baseaddr)
  530. {
  531. int err;
  532. spin_lock_init(&bus->bar_lock);
  533. INIT_LIST_HEAD(&bus->list);
  534. #ifdef CONFIG_SSB_EMBEDDED
  535. spin_lock_init(&bus->gpio_lock);
  536. #endif
  537. /* Powerup the bus */
  538. err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
  539. if (err)
  540. goto out;
  541. /* Init SDIO-host device (if any), before the scan */
  542. err = ssb_sdio_init(bus);
  543. if (err)
  544. goto err_disable_xtal;
  545. ssb_buses_lock();
  546. bus->busnumber = next_busnumber;
  547. /* Scan for devices (cores) */
  548. err = ssb_bus_scan(bus, baseaddr);
  549. if (err)
  550. goto err_sdio_exit;
  551. /* Init PCI-host device (if any) */
  552. err = ssb_pci_init(bus);
  553. if (err)
  554. goto err_unmap;
  555. /* Init PCMCIA-host device (if any) */
  556. err = ssb_pcmcia_init(bus);
  557. if (err)
  558. goto err_pci_exit;
  559. /* Initialize basic system devices (if available) */
  560. err = ssb_bus_powerup(bus, 0);
  561. if (err)
  562. goto err_pcmcia_exit;
  563. ssb_chipcommon_init(&bus->chipco);
  564. ssb_extif_init(&bus->extif);
  565. ssb_mipscore_init(&bus->mipscore);
  566. err = ssb_fetch_invariants(bus, get_invariants);
  567. if (err) {
  568. ssb_bus_may_powerdown(bus);
  569. goto err_pcmcia_exit;
  570. }
  571. ssb_bus_may_powerdown(bus);
  572. /* Queue it for attach.
  573. * See the comment at the ssb_is_early_boot definition. */
  574. list_add_tail(&bus->list, &attach_queue);
  575. if (!ssb_is_early_boot) {
  576. /* This is not early boot, so we must attach the bus now */
  577. err = ssb_attach_queued_buses();
  578. if (err)
  579. goto err_dequeue;
  580. }
  581. next_busnumber++;
  582. ssb_buses_unlock();
  583. out:
  584. return err;
  585. err_dequeue:
  586. list_del(&bus->list);
  587. err_pcmcia_exit:
  588. ssb_pcmcia_exit(bus);
  589. err_pci_exit:
  590. ssb_pci_exit(bus);
  591. err_unmap:
  592. ssb_iounmap(bus);
  593. err_sdio_exit:
  594. ssb_sdio_exit(bus);
  595. err_disable_xtal:
  596. ssb_buses_unlock();
  597. ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
  598. return err;
  599. }
  600. #ifdef CONFIG_SSB_PCIHOST
  601. int ssb_bus_pcibus_register(struct ssb_bus *bus, struct pci_dev *host_pci)
  602. {
  603. int err;
  604. bus->bustype = SSB_BUSTYPE_PCI;
  605. bus->host_pci = host_pci;
  606. bus->ops = &ssb_pci_ops;
  607. err = ssb_bus_register(bus, ssb_pci_get_invariants, 0);
  608. if (!err) {
  609. dev_info(&host_pci->dev,
  610. "Sonics Silicon Backplane found on PCI device %s\n",
  611. dev_name(&host_pci->dev));
  612. } else {
  613. dev_err(&host_pci->dev,
  614. "Failed to register PCI version of SSB with error %d\n",
  615. err);
  616. }
  617. return err;
  618. }
  619. #endif /* CONFIG_SSB_PCIHOST */
  620. #ifdef CONFIG_SSB_PCMCIAHOST
  621. int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
  622. struct pcmcia_device *pcmcia_dev,
  623. unsigned long baseaddr)
  624. {
  625. int err;
  626. bus->bustype = SSB_BUSTYPE_PCMCIA;
  627. bus->host_pcmcia = pcmcia_dev;
  628. bus->ops = &ssb_pcmcia_ops;
  629. err = ssb_bus_register(bus, ssb_pcmcia_get_invariants, baseaddr);
  630. if (!err) {
  631. dev_info(&pcmcia_dev->dev,
  632. "Sonics Silicon Backplane found on PCMCIA device %s\n",
  633. pcmcia_dev->devname);
  634. }
  635. return err;
  636. }
  637. #endif /* CONFIG_SSB_PCMCIAHOST */
  638. #ifdef CONFIG_SSB_SDIOHOST
  639. int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func,
  640. unsigned int quirks)
  641. {
  642. int err;
  643. bus->bustype = SSB_BUSTYPE_SDIO;
  644. bus->host_sdio = func;
  645. bus->ops = &ssb_sdio_ops;
  646. bus->quirks = quirks;
  647. err = ssb_bus_register(bus, ssb_sdio_get_invariants, ~0);
  648. if (!err) {
  649. dev_info(&func->dev,
  650. "Sonics Silicon Backplane found on SDIO device %s\n",
  651. sdio_func_id(func));
  652. }
  653. return err;
  654. }
  655. EXPORT_SYMBOL(ssb_bus_sdiobus_register);
  656. #endif /* CONFIG_SSB_PCMCIAHOST */
  657. #ifdef CONFIG_SSB_HOST_SOC
  658. int ssb_bus_host_soc_register(struct ssb_bus *bus, unsigned long baseaddr)
  659. {
  660. int err;
  661. bus->bustype = SSB_BUSTYPE_SSB;
  662. bus->ops = &ssb_host_soc_ops;
  663. err = ssb_bus_register(bus, ssb_host_soc_get_invariants, baseaddr);
  664. if (!err) {
  665. pr_info("Sonics Silicon Backplane found at address 0x%08lX\n",
  666. baseaddr);
  667. }
  668. return err;
  669. }
  670. #endif
  671. int __ssb_driver_register(struct ssb_driver *drv, struct module *owner)
  672. {
  673. drv->drv.name = drv->name;
  674. drv->drv.bus = &ssb_bustype;
  675. drv->drv.owner = owner;
  676. return driver_register(&drv->drv);
  677. }
  678. EXPORT_SYMBOL(__ssb_driver_register);
  679. void ssb_driver_unregister(struct ssb_driver *drv)
  680. {
  681. driver_unregister(&drv->drv);
  682. }
  683. EXPORT_SYMBOL(ssb_driver_unregister);
  684. void ssb_set_devtypedata(struct ssb_device *dev, void *data)
  685. {
  686. struct ssb_bus *bus = dev->bus;
  687. struct ssb_device *ent;
  688. int i;
  689. for (i = 0; i < bus->nr_devices; i++) {
  690. ent = &(bus->devices[i]);
  691. if (ent->id.vendor != dev->id.vendor)
  692. continue;
  693. if (ent->id.coreid != dev->id.coreid)
  694. continue;
  695. ent->devtypedata = data;
  696. }
  697. }
  698. EXPORT_SYMBOL(ssb_set_devtypedata);
  699. static u32 clkfactor_f6_resolve(u32 v)
  700. {
  701. /* map the magic values */
  702. switch (v) {
  703. case SSB_CHIPCO_CLK_F6_2:
  704. return 2;
  705. case SSB_CHIPCO_CLK_F6_3:
  706. return 3;
  707. case SSB_CHIPCO_CLK_F6_4:
  708. return 4;
  709. case SSB_CHIPCO_CLK_F6_5:
  710. return 5;
  711. case SSB_CHIPCO_CLK_F6_6:
  712. return 6;
  713. case SSB_CHIPCO_CLK_F6_7:
  714. return 7;
  715. }
  716. return 0;
  717. }
  718. /* Calculate the speed the backplane would run at a given set of clockcontrol values */
  719. u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m)
  720. {
  721. u32 n1, n2, clock, m1, m2, m3, mc;
  722. n1 = (n & SSB_CHIPCO_CLK_N1);
  723. n2 = ((n & SSB_CHIPCO_CLK_N2) >> SSB_CHIPCO_CLK_N2_SHIFT);
  724. switch (plltype) {
  725. case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
  726. if (m & SSB_CHIPCO_CLK_T6_MMASK)
  727. return SSB_CHIPCO_CLK_T6_M1;
  728. return SSB_CHIPCO_CLK_T6_M0;
  729. case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
  730. case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
  731. case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
  732. case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
  733. n1 = clkfactor_f6_resolve(n1);
  734. n2 += SSB_CHIPCO_CLK_F5_BIAS;
  735. break;
  736. case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */
  737. n1 += SSB_CHIPCO_CLK_T2_BIAS;
  738. n2 += SSB_CHIPCO_CLK_T2_BIAS;
  739. WARN_ON(!((n1 >= 2) && (n1 <= 7)));
  740. WARN_ON(!((n2 >= 5) && (n2 <= 23)));
  741. break;
  742. case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */
  743. return 100000000;
  744. default:
  745. WARN_ON(1);
  746. }
  747. switch (plltype) {
  748. case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
  749. case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
  750. clock = SSB_CHIPCO_CLK_BASE2 * n1 * n2;
  751. break;
  752. default:
  753. clock = SSB_CHIPCO_CLK_BASE1 * n1 * n2;
  754. }
  755. if (!clock)
  756. return 0;
  757. m1 = (m & SSB_CHIPCO_CLK_M1);
  758. m2 = ((m & SSB_CHIPCO_CLK_M2) >> SSB_CHIPCO_CLK_M2_SHIFT);
  759. m3 = ((m & SSB_CHIPCO_CLK_M3) >> SSB_CHIPCO_CLK_M3_SHIFT);
  760. mc = ((m & SSB_CHIPCO_CLK_MC) >> SSB_CHIPCO_CLK_MC_SHIFT);
  761. switch (plltype) {
  762. case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
  763. case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
  764. case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
  765. case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
  766. m1 = clkfactor_f6_resolve(m1);
  767. if ((plltype == SSB_PLLTYPE_1) ||
  768. (plltype == SSB_PLLTYPE_3))
  769. m2 += SSB_CHIPCO_CLK_F5_BIAS;
  770. else
  771. m2 = clkfactor_f6_resolve(m2);
  772. m3 = clkfactor_f6_resolve(m3);
  773. switch (mc) {
  774. case SSB_CHIPCO_CLK_MC_BYPASS:
  775. return clock;
  776. case SSB_CHIPCO_CLK_MC_M1:
  777. return (clock / m1);
  778. case SSB_CHIPCO_CLK_MC_M1M2:
  779. return (clock / (m1 * m2));
  780. case SSB_CHIPCO_CLK_MC_M1M2M3:
  781. return (clock / (m1 * m2 * m3));
  782. case SSB_CHIPCO_CLK_MC_M1M3:
  783. return (clock / (m1 * m3));
  784. }
  785. return 0;
  786. case SSB_PLLTYPE_2:
  787. m1 += SSB_CHIPCO_CLK_T2_BIAS;
  788. m2 += SSB_CHIPCO_CLK_T2M2_BIAS;
  789. m3 += SSB_CHIPCO_CLK_T2_BIAS;
  790. WARN_ON(!((m1 >= 2) && (m1 <= 7)));
  791. WARN_ON(!((m2 >= 3) && (m2 <= 10)));
  792. WARN_ON(!((m3 >= 2) && (m3 <= 7)));
  793. if (!(mc & SSB_CHIPCO_CLK_T2MC_M1BYP))
  794. clock /= m1;
  795. if (!(mc & SSB_CHIPCO_CLK_T2MC_M2BYP))
  796. clock /= m2;
  797. if (!(mc & SSB_CHIPCO_CLK_T2MC_M3BYP))
  798. clock /= m3;
  799. return clock;
  800. default:
  801. WARN_ON(1);
  802. }
  803. return 0;
  804. }
  805. /* Get the current speed the backplane is running at */
  806. u32 ssb_clockspeed(struct ssb_bus *bus)
  807. {
  808. u32 rate;
  809. u32 plltype;
  810. u32 clkctl_n, clkctl_m;
  811. if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
  812. return ssb_pmu_get_controlclock(&bus->chipco);
  813. if (ssb_extif_available(&bus->extif))
  814. ssb_extif_get_clockcontrol(&bus->extif, &plltype,
  815. &clkctl_n, &clkctl_m);
  816. else if (bus->chipco.dev)
  817. ssb_chipco_get_clockcontrol(&bus->chipco, &plltype,
  818. &clkctl_n, &clkctl_m);
  819. else
  820. return 0;
  821. if (bus->chip_id == 0x5365) {
  822. rate = 100000000;
  823. } else {
  824. rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
  825. if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */
  826. rate /= 2;
  827. }
  828. return rate;
  829. }
  830. EXPORT_SYMBOL(ssb_clockspeed);
  831. static u32 ssb_tmslow_reject_bitmask(struct ssb_device *dev)
  832. {
  833. u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
  834. /* The REJECT bit seems to be different for Backplane rev 2.3 */
  835. switch (rev) {
  836. case SSB_IDLOW_SSBREV_22:
  837. case SSB_IDLOW_SSBREV_24:
  838. case SSB_IDLOW_SSBREV_26:
  839. return SSB_TMSLOW_REJECT;
  840. case SSB_IDLOW_SSBREV_23:
  841. return SSB_TMSLOW_REJECT_23;
  842. case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */
  843. case SSB_IDLOW_SSBREV_27: /* same here */
  844. return SSB_TMSLOW_REJECT; /* this is a guess */
  845. case SSB_IDLOW_SSBREV:
  846. break;
  847. default:
  848. WARN(1, KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
  849. }
  850. return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
  851. }
  852. int ssb_device_is_enabled(struct ssb_device *dev)
  853. {
  854. u32 val;
  855. u32 reject;
  856. reject = ssb_tmslow_reject_bitmask(dev);
  857. val = ssb_read32(dev, SSB_TMSLOW);
  858. val &= SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET | reject;
  859. return (val == SSB_TMSLOW_CLOCK);
  860. }
  861. EXPORT_SYMBOL(ssb_device_is_enabled);
  862. static void ssb_flush_tmslow(struct ssb_device *dev)
  863. {
  864. /* Make _really_ sure the device has finished the TMSLOW
  865. * register write transaction, as we risk running into
  866. * a machine check exception otherwise.
  867. * Do this by reading the register back to commit the
  868. * PCI write and delay an additional usec for the device
  869. * to react to the change. */
  870. ssb_read32(dev, SSB_TMSLOW);
  871. udelay(1);
  872. }
  873. void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags)
  874. {
  875. u32 val;
  876. ssb_device_disable(dev, core_specific_flags);
  877. ssb_write32(dev, SSB_TMSLOW,
  878. SSB_TMSLOW_RESET | SSB_TMSLOW_CLOCK |
  879. SSB_TMSLOW_FGC | core_specific_flags);
  880. ssb_flush_tmslow(dev);
  881. /* Clear SERR if set. This is a hw bug workaround. */
  882. if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_SERR)
  883. ssb_write32(dev, SSB_TMSHIGH, 0);
  884. val = ssb_read32(dev, SSB_IMSTATE);
  885. if (val & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
  886. val &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
  887. ssb_write32(dev, SSB_IMSTATE, val);
  888. }
  889. ssb_write32(dev, SSB_TMSLOW,
  890. SSB_TMSLOW_CLOCK | SSB_TMSLOW_FGC |
  891. core_specific_flags);
  892. ssb_flush_tmslow(dev);
  893. ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_CLOCK |
  894. core_specific_flags);
  895. ssb_flush_tmslow(dev);
  896. }
  897. EXPORT_SYMBOL(ssb_device_enable);
  898. /* Wait for bitmask in a register to get set or cleared.
  899. * timeout is in units of ten-microseconds */
  900. static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask,
  901. int timeout, int set)
  902. {
  903. int i;
  904. u32 val;
  905. for (i = 0; i < timeout; i++) {
  906. val = ssb_read32(dev, reg);
  907. if (set) {
  908. if ((val & bitmask) == bitmask)
  909. return 0;
  910. } else {
  911. if (!(val & bitmask))
  912. return 0;
  913. }
  914. udelay(10);
  915. }
  916. dev_err(dev->dev,
  917. "Timeout waiting for bitmask %08X on register %04X to %s\n",
  918. bitmask, reg, set ? "set" : "clear");
  919. return -ETIMEDOUT;
  920. }
  921. void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
  922. {
  923. u32 reject, val;
  924. if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
  925. return;
  926. reject = ssb_tmslow_reject_bitmask(dev);
  927. if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) {
  928. ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
  929. ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1);
  930. ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
  931. if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
  932. val = ssb_read32(dev, SSB_IMSTATE);
  933. val |= SSB_IMSTATE_REJECT;
  934. ssb_write32(dev, SSB_IMSTATE, val);
  935. ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000,
  936. 0);
  937. }
  938. ssb_write32(dev, SSB_TMSLOW,
  939. SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
  940. reject | SSB_TMSLOW_RESET |
  941. core_specific_flags);
  942. ssb_flush_tmslow(dev);
  943. if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
  944. val = ssb_read32(dev, SSB_IMSTATE);
  945. val &= ~SSB_IMSTATE_REJECT;
  946. ssb_write32(dev, SSB_IMSTATE, val);
  947. }
  948. }
  949. ssb_write32(dev, SSB_TMSLOW,
  950. reject | SSB_TMSLOW_RESET |
  951. core_specific_flags);
  952. ssb_flush_tmslow(dev);
  953. }
  954. EXPORT_SYMBOL(ssb_device_disable);
  955. /* Some chipsets need routing known for PCIe and 64-bit DMA */
  956. static bool ssb_dma_translation_special_bit(struct ssb_device *dev)
  957. {
  958. u16 chip_id = dev->bus->chip_id;
  959. if (dev->id.coreid == SSB_DEV_80211) {
  960. return (chip_id == 0x4322 || chip_id == 43221 ||
  961. chip_id == 43231 || chip_id == 43222);
  962. }
  963. return false;
  964. }
  965. u32 ssb_dma_translation(struct ssb_device *dev)
  966. {
  967. switch (dev->bus->bustype) {
  968. case SSB_BUSTYPE_SSB:
  969. return 0;
  970. case SSB_BUSTYPE_PCI:
  971. if (pci_is_pcie(dev->bus->host_pci) &&
  972. ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) {
  973. return SSB_PCIE_DMA_H32;
  974. } else {
  975. if (ssb_dma_translation_special_bit(dev))
  976. return SSB_PCIE_DMA_H32;
  977. else
  978. return SSB_PCI_DMA;
  979. }
  980. default:
  981. __ssb_dma_not_implemented(dev);
  982. }
  983. return 0;
  984. }
  985. EXPORT_SYMBOL(ssb_dma_translation);
  986. int ssb_bus_may_powerdown(struct ssb_bus *bus)
  987. {
  988. struct ssb_chipcommon *cc;
  989. int err = 0;
  990. /* On buses where more than one core may be working
  991. * at a time, we must not powerdown stuff if there are
  992. * still cores that may want to run. */
  993. if (bus->bustype == SSB_BUSTYPE_SSB)
  994. goto out;
  995. cc = &bus->chipco;
  996. if (!cc->dev)
  997. goto out;
  998. if (cc->dev->id.revision < 5)
  999. goto out;
  1000. ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW);
  1001. err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
  1002. if (err)
  1003. goto error;
  1004. out:
  1005. bus->powered_up = 0;
  1006. return err;
  1007. error:
  1008. pr_err("Bus powerdown failed\n");
  1009. goto out;
  1010. }
  1011. EXPORT_SYMBOL(ssb_bus_may_powerdown);
  1012. int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
  1013. {
  1014. int err;
  1015. enum ssb_clkmode mode;
  1016. err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
  1017. if (err)
  1018. goto error;
  1019. bus->powered_up = 1;
  1020. mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
  1021. ssb_chipco_set_clockmode(&bus->chipco, mode);
  1022. return 0;
  1023. error:
  1024. pr_err("Bus powerup failed\n");
  1025. return err;
  1026. }
  1027. EXPORT_SYMBOL(ssb_bus_powerup);
  1028. static void ssb_broadcast_value(struct ssb_device *dev,
  1029. u32 address, u32 data)
  1030. {
  1031. #ifdef CONFIG_SSB_DRIVER_PCICORE
  1032. /* This is used for both, PCI and ChipCommon core, so be careful. */
  1033. BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
  1034. BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
  1035. #endif
  1036. ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address);
  1037. ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */
  1038. ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data);
  1039. ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */
  1040. }
  1041. void ssb_commit_settings(struct ssb_bus *bus)
  1042. {
  1043. struct ssb_device *dev;
  1044. #ifdef CONFIG_SSB_DRIVER_PCICORE
  1045. dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
  1046. #else
  1047. dev = bus->chipco.dev;
  1048. #endif
  1049. if (WARN_ON(!dev))
  1050. return;
  1051. /* This forces an update of the cached registers. */
  1052. ssb_broadcast_value(dev, 0xFD8, 0);
  1053. }
  1054. EXPORT_SYMBOL(ssb_commit_settings);
  1055. u32 ssb_admatch_base(u32 adm)
  1056. {
  1057. u32 base = 0;
  1058. switch (adm & SSB_ADM_TYPE) {
  1059. case SSB_ADM_TYPE0:
  1060. base = (adm & SSB_ADM_BASE0);
  1061. break;
  1062. case SSB_ADM_TYPE1:
  1063. WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
  1064. base = (adm & SSB_ADM_BASE1);
  1065. break;
  1066. case SSB_ADM_TYPE2:
  1067. WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
  1068. base = (adm & SSB_ADM_BASE2);
  1069. break;
  1070. default:
  1071. WARN_ON(1);
  1072. }
  1073. return base;
  1074. }
  1075. EXPORT_SYMBOL(ssb_admatch_base);
  1076. u32 ssb_admatch_size(u32 adm)
  1077. {
  1078. u32 size = 0;
  1079. switch (adm & SSB_ADM_TYPE) {
  1080. case SSB_ADM_TYPE0:
  1081. size = ((adm & SSB_ADM_SZ0) >> SSB_ADM_SZ0_SHIFT);
  1082. break;
  1083. case SSB_ADM_TYPE1:
  1084. WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
  1085. size = ((adm & SSB_ADM_SZ1) >> SSB_ADM_SZ1_SHIFT);
  1086. break;
  1087. case SSB_ADM_TYPE2:
  1088. WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
  1089. size = ((adm & SSB_ADM_SZ2) >> SSB_ADM_SZ2_SHIFT);
  1090. break;
  1091. default:
  1092. WARN_ON(1);
  1093. }
  1094. size = (1 << (size + 1));
  1095. return size;
  1096. }
  1097. EXPORT_SYMBOL(ssb_admatch_size);
  1098. static int __init ssb_modinit(void)
  1099. {
  1100. int err;
  1101. /* See the comment at the ssb_is_early_boot definition */
  1102. ssb_is_early_boot = 0;
  1103. err = bus_register(&ssb_bustype);
  1104. if (err)
  1105. return err;
  1106. /* Maybe we already registered some buses at early boot.
  1107. * Check for this and attach them
  1108. */
  1109. ssb_buses_lock();
  1110. err = ssb_attach_queued_buses();
  1111. ssb_buses_unlock();
  1112. if (err) {
  1113. bus_unregister(&ssb_bustype);
  1114. goto out;
  1115. }
  1116. err = b43_pci_ssb_bridge_init();
  1117. if (err) {
  1118. pr_err("Broadcom 43xx PCI-SSB-bridge initialization failed\n");
  1119. /* don't fail SSB init because of this */
  1120. err = 0;
  1121. }
  1122. err = ssb_host_pcmcia_init();
  1123. if (err) {
  1124. pr_err("PCMCIA host initialization failed\n");
  1125. /* don't fail SSB init because of this */
  1126. err = 0;
  1127. }
  1128. err = ssb_gige_init();
  1129. if (err) {
  1130. pr_err("SSB Broadcom Gigabit Ethernet driver initialization failed\n");
  1131. /* don't fail SSB init because of this */
  1132. err = 0;
  1133. }
  1134. out:
  1135. return err;
  1136. }
  1137. /* ssb must be initialized after PCI but before the ssb drivers.
  1138. * That means we must use some initcall between subsys_initcall
  1139. * and device_initcall. */
  1140. fs_initcall(ssb_modinit);
  1141. static void __exit ssb_modexit(void)
  1142. {
  1143. ssb_gige_exit();
  1144. ssb_host_pcmcia_exit();
  1145. b43_pci_ssb_bridge_exit();
  1146. bus_unregister(&ssb_bustype);
  1147. }
  1148. module_exit(ssb_modexit)