driver_pcicore.c 19 KB

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  1. /*
  2. * Sonics Silicon Backplane
  3. * Broadcom PCI-core driver
  4. *
  5. * Copyright 2005, Broadcom Corporation
  6. * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
  7. *
  8. * Licensed under the GNU/GPL. See COPYING for details.
  9. */
  10. #include "ssb_private.h"
  11. #include <linux/ssb/ssb.h>
  12. #include <linux/pci.h>
  13. #include <linux/export.h>
  14. #include <linux/delay.h>
  15. #include <linux/ssb/ssb_embedded.h>
  16. static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address);
  17. static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data);
  18. static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address);
  19. static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
  20. u8 address, u16 data);
  21. static inline
  22. u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
  23. {
  24. return ssb_read32(pc->dev, offset);
  25. }
  26. static inline
  27. void pcicore_write32(struct ssb_pcicore *pc, u16 offset, u32 value)
  28. {
  29. ssb_write32(pc->dev, offset, value);
  30. }
  31. static inline
  32. u16 pcicore_read16(struct ssb_pcicore *pc, u16 offset)
  33. {
  34. return ssb_read16(pc->dev, offset);
  35. }
  36. static inline
  37. void pcicore_write16(struct ssb_pcicore *pc, u16 offset, u16 value)
  38. {
  39. ssb_write16(pc->dev, offset, value);
  40. }
  41. /**************************************************
  42. * Code for hostmode operation.
  43. **************************************************/
  44. #ifdef CONFIG_SSB_PCICORE_HOSTMODE
  45. #include <asm/paccess.h>
  46. /* Probe a 32bit value on the bus and catch bus exceptions.
  47. * Returns nonzero on a bus exception.
  48. * This is MIPS specific */
  49. #define mips_busprobe32(val, addr) get_dbe((val), ((u32 *)(addr)))
  50. /* Assume one-hot slot wiring */
  51. #define SSB_PCI_SLOT_MAX 16
  52. /* Global lock is OK, as we won't have more than one extpci anyway. */
  53. static DEFINE_SPINLOCK(cfgspace_lock);
  54. /* Core to access the external PCI config space. Can only have one. */
  55. static struct ssb_pcicore *extpci_core;
  56. static u32 get_cfgspace_addr(struct ssb_pcicore *pc,
  57. unsigned int bus, unsigned int dev,
  58. unsigned int func, unsigned int off)
  59. {
  60. u32 addr = 0;
  61. u32 tmp;
  62. /* We do only have one cardbus device behind the bridge. */
  63. if (pc->cardbusmode && (dev > 1))
  64. goto out;
  65. if (bus == 0) {
  66. /* Type 0 transaction */
  67. if (unlikely(dev >= SSB_PCI_SLOT_MAX))
  68. goto out;
  69. /* Slide the window */
  70. tmp = SSB_PCICORE_SBTOPCI_CFG0;
  71. tmp |= ((1 << (dev + 16)) & SSB_PCICORE_SBTOPCI1_MASK);
  72. pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, tmp);
  73. /* Calculate the address */
  74. addr = SSB_PCI_CFG;
  75. addr |= ((1 << (dev + 16)) & ~SSB_PCICORE_SBTOPCI1_MASK);
  76. addr |= (func << 8);
  77. addr |= (off & ~3);
  78. } else {
  79. /* Type 1 transaction */
  80. pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
  81. SSB_PCICORE_SBTOPCI_CFG1);
  82. /* Calculate the address */
  83. addr = SSB_PCI_CFG;
  84. addr |= (bus << 16);
  85. addr |= (dev << 11);
  86. addr |= (func << 8);
  87. addr |= (off & ~3);
  88. }
  89. out:
  90. return addr;
  91. }
  92. static int ssb_extpci_read_config(struct ssb_pcicore *pc,
  93. unsigned int bus, unsigned int dev,
  94. unsigned int func, unsigned int off,
  95. void *buf, int len)
  96. {
  97. int err = -EINVAL;
  98. u32 addr, val;
  99. void __iomem *mmio;
  100. WARN_ON(!pc->hostmode);
  101. if (unlikely(len != 1 && len != 2 && len != 4))
  102. goto out;
  103. addr = get_cfgspace_addr(pc, bus, dev, func, off);
  104. if (unlikely(!addr))
  105. goto out;
  106. err = -ENOMEM;
  107. mmio = ioremap(addr, len);
  108. if (!mmio)
  109. goto out;
  110. if (mips_busprobe32(val, mmio)) {
  111. val = 0xffffffff;
  112. goto unmap;
  113. }
  114. val = readl(mmio);
  115. val >>= (8 * (off & 3));
  116. switch (len) {
  117. case 1:
  118. *((u8 *)buf) = (u8)val;
  119. break;
  120. case 2:
  121. *((u16 *)buf) = (u16)val;
  122. break;
  123. case 4:
  124. *((u32 *)buf) = (u32)val;
  125. break;
  126. }
  127. err = 0;
  128. unmap:
  129. iounmap(mmio);
  130. out:
  131. return err;
  132. }
  133. static int ssb_extpci_write_config(struct ssb_pcicore *pc,
  134. unsigned int bus, unsigned int dev,
  135. unsigned int func, unsigned int off,
  136. const void *buf, int len)
  137. {
  138. int err = -EINVAL;
  139. u32 addr, val = 0;
  140. void __iomem *mmio;
  141. WARN_ON(!pc->hostmode);
  142. if (unlikely(len != 1 && len != 2 && len != 4))
  143. goto out;
  144. addr = get_cfgspace_addr(pc, bus, dev, func, off);
  145. if (unlikely(!addr))
  146. goto out;
  147. err = -ENOMEM;
  148. mmio = ioremap(addr, len);
  149. if (!mmio)
  150. goto out;
  151. if (mips_busprobe32(val, mmio)) {
  152. val = 0xffffffff;
  153. goto unmap;
  154. }
  155. switch (len) {
  156. case 1:
  157. val = readl(mmio);
  158. val &= ~(0xFF << (8 * (off & 3)));
  159. val |= *((const u8 *)buf) << (8 * (off & 3));
  160. break;
  161. case 2:
  162. val = readl(mmio);
  163. val &= ~(0xFFFF << (8 * (off & 3)));
  164. val |= *((const u16 *)buf) << (8 * (off & 3));
  165. break;
  166. case 4:
  167. val = *((const u32 *)buf);
  168. break;
  169. }
  170. writel(val, mmio);
  171. err = 0;
  172. unmap:
  173. iounmap(mmio);
  174. out:
  175. return err;
  176. }
  177. static int ssb_pcicore_read_config(struct pci_bus *bus, unsigned int devfn,
  178. int reg, int size, u32 *val)
  179. {
  180. unsigned long flags;
  181. int err;
  182. spin_lock_irqsave(&cfgspace_lock, flags);
  183. err = ssb_extpci_read_config(extpci_core, bus->number, PCI_SLOT(devfn),
  184. PCI_FUNC(devfn), reg, val, size);
  185. spin_unlock_irqrestore(&cfgspace_lock, flags);
  186. return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
  187. }
  188. static int ssb_pcicore_write_config(struct pci_bus *bus, unsigned int devfn,
  189. int reg, int size, u32 val)
  190. {
  191. unsigned long flags;
  192. int err;
  193. spin_lock_irqsave(&cfgspace_lock, flags);
  194. err = ssb_extpci_write_config(extpci_core, bus->number, PCI_SLOT(devfn),
  195. PCI_FUNC(devfn), reg, &val, size);
  196. spin_unlock_irqrestore(&cfgspace_lock, flags);
  197. return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
  198. }
  199. static struct pci_ops ssb_pcicore_pciops = {
  200. .read = ssb_pcicore_read_config,
  201. .write = ssb_pcicore_write_config,
  202. };
  203. static struct resource ssb_pcicore_mem_resource = {
  204. .name = "SSB PCIcore external memory",
  205. .start = SSB_PCI_DMA,
  206. .end = SSB_PCI_DMA + SSB_PCI_DMA_SZ - 1,
  207. .flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED,
  208. };
  209. static struct resource ssb_pcicore_io_resource = {
  210. .name = "SSB PCIcore external I/O",
  211. .start = 0x100,
  212. .end = 0x7FF,
  213. .flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED,
  214. };
  215. static struct pci_controller ssb_pcicore_controller = {
  216. .pci_ops = &ssb_pcicore_pciops,
  217. .io_resource = &ssb_pcicore_io_resource,
  218. .mem_resource = &ssb_pcicore_mem_resource,
  219. };
  220. /* This function is called when doing a pci_enable_device().
  221. * We must first check if the device is a device on the PCI-core bridge. */
  222. int ssb_pcicore_plat_dev_init(struct pci_dev *d)
  223. {
  224. if (d->bus->ops != &ssb_pcicore_pciops) {
  225. /* This is not a device on the PCI-core bridge. */
  226. return -ENODEV;
  227. }
  228. dev_info(&d->dev, "PCI: Fixing up device %s\n", pci_name(d));
  229. /* Fix up interrupt lines */
  230. d->irq = ssb_mips_irq(extpci_core->dev) + 2;
  231. pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
  232. return 0;
  233. }
  234. /* Early PCI fixup for a device on the PCI-core bridge. */
  235. static void ssb_pcicore_fixup_pcibridge(struct pci_dev *dev)
  236. {
  237. u8 lat;
  238. if (dev->bus->ops != &ssb_pcicore_pciops) {
  239. /* This is not a device on the PCI-core bridge. */
  240. return;
  241. }
  242. if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
  243. return;
  244. dev_info(&dev->dev, "PCI: Fixing up bridge %s\n", pci_name(dev));
  245. /* Enable PCI bridge bus mastering and memory space */
  246. pci_set_master(dev);
  247. if (pcibios_enable_device(dev, ~0) < 0) {
  248. dev_err(&dev->dev, "PCI: SSB bridge enable failed\n");
  249. return;
  250. }
  251. /* Enable PCI bridge BAR1 prefetch and burst */
  252. pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
  253. /* Make sure our latency is high enough to handle the devices behind us */
  254. lat = 168;
  255. dev_info(&dev->dev,
  256. "PCI: Fixing latency timer of device %s to %u\n",
  257. pci_name(dev), lat);
  258. pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
  259. }
  260. DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_pcicore_fixup_pcibridge);
  261. /* PCI device IRQ mapping. */
  262. int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
  263. {
  264. if (dev->bus->ops != &ssb_pcicore_pciops) {
  265. /* This is not a device on the PCI-core bridge. */
  266. return -ENODEV;
  267. }
  268. return ssb_mips_irq(extpci_core->dev) + 2;
  269. }
  270. static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
  271. {
  272. u32 val;
  273. if (WARN_ON(extpci_core))
  274. return;
  275. extpci_core = pc;
  276. dev_dbg(pc->dev->dev, "PCIcore in host mode found\n");
  277. /* Reset devices on the external PCI bus */
  278. val = SSB_PCICORE_CTL_RST_OE;
  279. val |= SSB_PCICORE_CTL_CLK_OE;
  280. pcicore_write32(pc, SSB_PCICORE_CTL, val);
  281. val |= SSB_PCICORE_CTL_CLK; /* Clock on */
  282. pcicore_write32(pc, SSB_PCICORE_CTL, val);
  283. udelay(150); /* Assertion time demanded by the PCI standard */
  284. val |= SSB_PCICORE_CTL_RST; /* Deassert RST# */
  285. pcicore_write32(pc, SSB_PCICORE_CTL, val);
  286. val = SSB_PCICORE_ARBCTL_INTERN;
  287. pcicore_write32(pc, SSB_PCICORE_ARBCTL, val);
  288. udelay(1); /* Assertion time demanded by the PCI standard */
  289. if (pc->dev->bus->has_cardbus_slot) {
  290. dev_dbg(pc->dev->dev, "CardBus slot detected\n");
  291. pc->cardbusmode = 1;
  292. /* GPIO 1 resets the bridge */
  293. ssb_gpio_out(pc->dev->bus, 1, 1);
  294. ssb_gpio_outen(pc->dev->bus, 1, 1);
  295. pcicore_write16(pc, SSB_PCICORE_SPROM(0),
  296. pcicore_read16(pc, SSB_PCICORE_SPROM(0))
  297. | 0x0400);
  298. }
  299. /* 64MB I/O window */
  300. pcicore_write32(pc, SSB_PCICORE_SBTOPCI0,
  301. SSB_PCICORE_SBTOPCI_IO);
  302. /* 64MB config space */
  303. pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
  304. SSB_PCICORE_SBTOPCI_CFG0);
  305. /* 1GB memory window */
  306. pcicore_write32(pc, SSB_PCICORE_SBTOPCI2,
  307. SSB_PCICORE_SBTOPCI_MEM | SSB_PCI_DMA);
  308. /*
  309. * Accessing PCI config without a proper delay after devices reset (not
  310. * GPIO reset) was causing reboots on WRT300N v1.0 (BCM4704).
  311. * Tested delay 850 us lowered reboot chance to 50-80%, 1000 us fixed it
  312. * completely. Flushing all writes was also tested but with no luck.
  313. * The same problem was reported for WRT350N v1 (BCM4705), so we just
  314. * sleep here unconditionally.
  315. */
  316. usleep_range(1000, 2000);
  317. /* Enable PCI bridge BAR0 prefetch and burst */
  318. val = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
  319. ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 2);
  320. /* Clear error conditions */
  321. val = 0;
  322. ssb_extpci_write_config(pc, 0, 0, 0, PCI_STATUS, &val, 2);
  323. /* Enable PCI interrupts */
  324. pcicore_write32(pc, SSB_PCICORE_IMASK,
  325. SSB_PCICORE_IMASK_INTA);
  326. /* Ok, ready to run, register it to the system.
  327. * The following needs change, if we want to port hostmode
  328. * to non-MIPS platform. */
  329. ssb_pcicore_controller.io_map_base = (unsigned long)ioremap(SSB_PCI_MEM, 0x04000000);
  330. set_io_port_base(ssb_pcicore_controller.io_map_base);
  331. /* Give some time to the PCI controller to configure itself with the new
  332. * values. Not waiting at this point causes crashes of the machine. */
  333. mdelay(10);
  334. register_pci_controller(&ssb_pcicore_controller);
  335. }
  336. static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
  337. {
  338. struct ssb_bus *bus = pc->dev->bus;
  339. u16 chipid_top;
  340. u32 tmp;
  341. chipid_top = (bus->chip_id & 0xFF00);
  342. if (chipid_top != 0x4700 &&
  343. chipid_top != 0x5300)
  344. return 0;
  345. if (bus->sprom.boardflags_lo & SSB_PCICORE_BFL_NOPCI)
  346. return 0;
  347. /* The 200-pin BCM4712 package does not bond out PCI. Even when
  348. * PCI is bonded out, some boards may leave the pins floating. */
  349. if (bus->chip_id == 0x4712) {
  350. if (bus->chip_package == SSB_CHIPPACK_BCM4712S)
  351. return 0;
  352. if (bus->chip_package == SSB_CHIPPACK_BCM4712M)
  353. return 0;
  354. }
  355. if (bus->chip_id == 0x5350)
  356. return 0;
  357. return !mips_busprobe32(tmp, (bus->mmio + (pc->dev->core_index * SSB_CORE_SIZE)));
  358. }
  359. #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
  360. /**************************************************
  361. * Workarounds.
  362. **************************************************/
  363. static void ssb_pcicore_fix_sprom_core_index(struct ssb_pcicore *pc)
  364. {
  365. u16 tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(0));
  366. if (((tmp & 0xF000) >> 12) != pc->dev->core_index) {
  367. tmp &= ~0xF000;
  368. tmp |= (pc->dev->core_index << 12);
  369. pcicore_write16(pc, SSB_PCICORE_SPROM(0), tmp);
  370. }
  371. }
  372. static u8 ssb_pcicore_polarity_workaround(struct ssb_pcicore *pc)
  373. {
  374. return (ssb_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
  375. }
  376. static void ssb_pcicore_serdes_workaround(struct ssb_pcicore *pc)
  377. {
  378. const u8 serdes_pll_device = 0x1D;
  379. const u8 serdes_rx_device = 0x1F;
  380. u16 tmp;
  381. ssb_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
  382. ssb_pcicore_polarity_workaround(pc));
  383. tmp = ssb_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
  384. if (tmp & 0x4000)
  385. ssb_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
  386. }
  387. static void ssb_pcicore_pci_setup_workarounds(struct ssb_pcicore *pc)
  388. {
  389. struct ssb_device *pdev = pc->dev;
  390. struct ssb_bus *bus = pdev->bus;
  391. u32 tmp;
  392. tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
  393. tmp |= SSB_PCICORE_SBTOPCI_PREF;
  394. tmp |= SSB_PCICORE_SBTOPCI_BURST;
  395. pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
  396. if (pdev->id.revision < 5) {
  397. tmp = ssb_read32(pdev, SSB_IMCFGLO);
  398. tmp &= ~SSB_IMCFGLO_SERTO;
  399. tmp |= 2;
  400. tmp &= ~SSB_IMCFGLO_REQTO;
  401. tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
  402. ssb_write32(pdev, SSB_IMCFGLO, tmp);
  403. ssb_commit_settings(bus);
  404. } else if (pdev->id.revision >= 11) {
  405. tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
  406. tmp |= SSB_PCICORE_SBTOPCI_MRM;
  407. pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
  408. }
  409. }
  410. static void ssb_pcicore_pcie_setup_workarounds(struct ssb_pcicore *pc)
  411. {
  412. u32 tmp;
  413. u8 rev = pc->dev->id.revision;
  414. if (rev == 0 || rev == 1) {
  415. /* TLP Workaround register. */
  416. tmp = ssb_pcie_read(pc, 0x4);
  417. tmp |= 0x8;
  418. ssb_pcie_write(pc, 0x4, tmp);
  419. }
  420. if (rev == 1) {
  421. /* DLLP Link Control register. */
  422. tmp = ssb_pcie_read(pc, 0x100);
  423. tmp |= 0x40;
  424. ssb_pcie_write(pc, 0x100, tmp);
  425. }
  426. if (rev == 0) {
  427. const u8 serdes_rx_device = 0x1F;
  428. ssb_pcie_mdio_write(pc, serdes_rx_device,
  429. 2 /* Timer */, 0x8128);
  430. ssb_pcie_mdio_write(pc, serdes_rx_device,
  431. 6 /* CDR */, 0x0100);
  432. ssb_pcie_mdio_write(pc, serdes_rx_device,
  433. 7 /* CDR BW */, 0x1466);
  434. } else if (rev == 3 || rev == 4 || rev == 5) {
  435. /* TODO: DLLP Power Management Threshold */
  436. ssb_pcicore_serdes_workaround(pc);
  437. /* TODO: ASPM */
  438. } else if (rev == 7) {
  439. /* TODO: No PLL down */
  440. }
  441. if (rev >= 6) {
  442. /* Miscellaneous Configuration Fixup */
  443. tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(5));
  444. if (!(tmp & 0x8000))
  445. pcicore_write16(pc, SSB_PCICORE_SPROM(5),
  446. tmp | 0x8000);
  447. }
  448. }
  449. /**************************************************
  450. * Generic and Clientmode operation code.
  451. **************************************************/
  452. static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
  453. {
  454. struct ssb_device *pdev = pc->dev;
  455. struct ssb_bus *bus = pdev->bus;
  456. if (bus->bustype == SSB_BUSTYPE_PCI)
  457. ssb_pcicore_fix_sprom_core_index(pc);
  458. /* Disable PCI interrupts. */
  459. ssb_write32(pdev, SSB_INTVEC, 0);
  460. /* Additional PCIe always once-executed workarounds */
  461. if (pc->dev->id.coreid == SSB_DEV_PCIE) {
  462. ssb_pcicore_serdes_workaround(pc);
  463. /* TODO: ASPM */
  464. /* TODO: Clock Request Update */
  465. }
  466. }
  467. void ssb_pcicore_init(struct ssb_pcicore *pc)
  468. {
  469. struct ssb_device *dev = pc->dev;
  470. if (!dev)
  471. return;
  472. if (!ssb_device_is_enabled(dev))
  473. ssb_device_enable(dev, 0);
  474. #ifdef CONFIG_SSB_PCICORE_HOSTMODE
  475. pc->hostmode = pcicore_is_in_hostmode(pc);
  476. if (pc->hostmode)
  477. ssb_pcicore_init_hostmode(pc);
  478. #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
  479. if (!pc->hostmode)
  480. ssb_pcicore_init_clientmode(pc);
  481. }
  482. static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address)
  483. {
  484. pcicore_write32(pc, 0x130, address);
  485. return pcicore_read32(pc, 0x134);
  486. }
  487. static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data)
  488. {
  489. pcicore_write32(pc, 0x130, address);
  490. pcicore_write32(pc, 0x134, data);
  491. }
  492. static void ssb_pcie_mdio_set_phy(struct ssb_pcicore *pc, u8 phy)
  493. {
  494. const u16 mdio_control = 0x128;
  495. const u16 mdio_data = 0x12C;
  496. u32 v;
  497. int i;
  498. v = (1 << 30); /* Start of Transaction */
  499. v |= (1 << 28); /* Write Transaction */
  500. v |= (1 << 17); /* Turnaround */
  501. v |= (0x1F << 18);
  502. v |= (phy << 4);
  503. pcicore_write32(pc, mdio_data, v);
  504. udelay(10);
  505. for (i = 0; i < 200; i++) {
  506. v = pcicore_read32(pc, mdio_control);
  507. if (v & 0x100 /* Trans complete */)
  508. break;
  509. msleep(1);
  510. }
  511. }
  512. static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address)
  513. {
  514. const u16 mdio_control = 0x128;
  515. const u16 mdio_data = 0x12C;
  516. int max_retries = 10;
  517. u16 ret = 0;
  518. u32 v;
  519. int i;
  520. v = 0x80; /* Enable Preamble Sequence */
  521. v |= 0x2; /* MDIO Clock Divisor */
  522. pcicore_write32(pc, mdio_control, v);
  523. if (pc->dev->id.revision >= 10) {
  524. max_retries = 200;
  525. ssb_pcie_mdio_set_phy(pc, device);
  526. }
  527. v = (1 << 30); /* Start of Transaction */
  528. v |= (1 << 29); /* Read Transaction */
  529. v |= (1 << 17); /* Turnaround */
  530. if (pc->dev->id.revision < 10)
  531. v |= (u32)device << 22;
  532. v |= (u32)address << 18;
  533. pcicore_write32(pc, mdio_data, v);
  534. /* Wait for the device to complete the transaction */
  535. udelay(10);
  536. for (i = 0; i < max_retries; i++) {
  537. v = pcicore_read32(pc, mdio_control);
  538. if (v & 0x100 /* Trans complete */) {
  539. udelay(10);
  540. ret = pcicore_read32(pc, mdio_data);
  541. break;
  542. }
  543. msleep(1);
  544. }
  545. pcicore_write32(pc, mdio_control, 0);
  546. return ret;
  547. }
  548. static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
  549. u8 address, u16 data)
  550. {
  551. const u16 mdio_control = 0x128;
  552. const u16 mdio_data = 0x12C;
  553. int max_retries = 10;
  554. u32 v;
  555. int i;
  556. v = 0x80; /* Enable Preamble Sequence */
  557. v |= 0x2; /* MDIO Clock Divisor */
  558. pcicore_write32(pc, mdio_control, v);
  559. if (pc->dev->id.revision >= 10) {
  560. max_retries = 200;
  561. ssb_pcie_mdio_set_phy(pc, device);
  562. }
  563. v = (1 << 30); /* Start of Transaction */
  564. v |= (1 << 28); /* Write Transaction */
  565. v |= (1 << 17); /* Turnaround */
  566. if (pc->dev->id.revision < 10)
  567. v |= (u32)device << 22;
  568. v |= (u32)address << 18;
  569. v |= data;
  570. pcicore_write32(pc, mdio_data, v);
  571. /* Wait for the device to complete the transaction */
  572. udelay(10);
  573. for (i = 0; i < max_retries; i++) {
  574. v = pcicore_read32(pc, mdio_control);
  575. if (v & 0x100 /* Trans complete */)
  576. break;
  577. msleep(1);
  578. }
  579. pcicore_write32(pc, mdio_control, 0);
  580. }
  581. int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
  582. struct ssb_device *dev)
  583. {
  584. struct ssb_device *pdev = pc->dev;
  585. struct ssb_bus *bus;
  586. int err = 0;
  587. u32 tmp;
  588. if (dev->bus->bustype != SSB_BUSTYPE_PCI) {
  589. /* This SSB device is not on a PCI host-bus. So the IRQs are
  590. * not routed through the PCI core.
  591. * So we must not enable routing through the PCI core. */
  592. goto out;
  593. }
  594. if (!pdev)
  595. goto out;
  596. bus = pdev->bus;
  597. might_sleep_if(pdev->id.coreid != SSB_DEV_PCI);
  598. /* Enable interrupts for this device. */
  599. if ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE)) {
  600. u32 coremask;
  601. /* Calculate the "coremask" for the device. */
  602. coremask = (1 << dev->core_index);
  603. WARN_ON(bus->bustype != SSB_BUSTYPE_PCI);
  604. err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp);
  605. if (err)
  606. goto out;
  607. tmp |= coremask << 8;
  608. err = pci_write_config_dword(bus->host_pci, SSB_PCI_IRQMASK, tmp);
  609. if (err)
  610. goto out;
  611. } else {
  612. u32 intvec;
  613. intvec = ssb_read32(pdev, SSB_INTVEC);
  614. tmp = ssb_read32(dev, SSB_TPSFLAG);
  615. tmp &= SSB_TPSFLAG_BPFLAG;
  616. intvec |= (1 << tmp);
  617. ssb_write32(pdev, SSB_INTVEC, intvec);
  618. }
  619. /* Setup PCIcore operation. */
  620. if (pc->setup_done)
  621. goto out;
  622. if (pdev->id.coreid == SSB_DEV_PCI) {
  623. ssb_pcicore_pci_setup_workarounds(pc);
  624. } else {
  625. WARN_ON(pdev->id.coreid != SSB_DEV_PCIE);
  626. ssb_pcicore_pcie_setup_workarounds(pc);
  627. }
  628. pc->setup_done = 1;
  629. out:
  630. return err;
  631. }
  632. EXPORT_SYMBOL(ssb_pcicore_dev_irqvecs_enable);