driver_mipscore.c 8.8 KB

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  1. /*
  2. * Sonics Silicon Backplane
  3. * Broadcom MIPS core driver
  4. *
  5. * Copyright 2005, Broadcom Corporation
  6. * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
  7. *
  8. * Licensed under the GNU/GPL. See COPYING for details.
  9. */
  10. #include "ssb_private.h"
  11. #include <linux/ssb/ssb.h>
  12. #include <linux/mtd/physmap.h>
  13. #include <linux/serial.h>
  14. #include <linux/serial_core.h>
  15. #include <linux/serial_reg.h>
  16. #include <linux/time.h>
  17. #ifdef CONFIG_BCM47XX
  18. #include <linux/bcm47xx_nvram.h>
  19. #endif
  20. static const char * const part_probes[] = { "bcm47xxpart", NULL };
  21. static struct physmap_flash_data ssb_pflash_data = {
  22. .part_probe_types = part_probes,
  23. };
  24. static struct resource ssb_pflash_resource = {
  25. .name = "ssb_pflash",
  26. .flags = IORESOURCE_MEM,
  27. };
  28. struct platform_device ssb_pflash_dev = {
  29. .name = "physmap-flash",
  30. .dev = {
  31. .platform_data = &ssb_pflash_data,
  32. },
  33. .resource = &ssb_pflash_resource,
  34. .num_resources = 1,
  35. };
  36. static inline u32 mips_read32(struct ssb_mipscore *mcore,
  37. u16 offset)
  38. {
  39. return ssb_read32(mcore->dev, offset);
  40. }
  41. static inline void mips_write32(struct ssb_mipscore *mcore,
  42. u16 offset,
  43. u32 value)
  44. {
  45. ssb_write32(mcore->dev, offset, value);
  46. }
  47. static const u32 ipsflag_irq_mask[] = {
  48. 0,
  49. SSB_IPSFLAG_IRQ1,
  50. SSB_IPSFLAG_IRQ2,
  51. SSB_IPSFLAG_IRQ3,
  52. SSB_IPSFLAG_IRQ4,
  53. };
  54. static const u32 ipsflag_irq_shift[] = {
  55. 0,
  56. SSB_IPSFLAG_IRQ1_SHIFT,
  57. SSB_IPSFLAG_IRQ2_SHIFT,
  58. SSB_IPSFLAG_IRQ3_SHIFT,
  59. SSB_IPSFLAG_IRQ4_SHIFT,
  60. };
  61. static inline u32 ssb_irqflag(struct ssb_device *dev)
  62. {
  63. u32 tpsflag = ssb_read32(dev, SSB_TPSFLAG);
  64. if (tpsflag)
  65. return ssb_read32(dev, SSB_TPSFLAG) & SSB_TPSFLAG_BPFLAG;
  66. else
  67. /* not irq supported */
  68. return 0x3f;
  69. }
  70. static struct ssb_device *find_device(struct ssb_device *rdev, int irqflag)
  71. {
  72. struct ssb_bus *bus = rdev->bus;
  73. int i;
  74. for (i = 0; i < bus->nr_devices; i++) {
  75. struct ssb_device *dev;
  76. dev = &(bus->devices[i]);
  77. if (ssb_irqflag(dev) == irqflag)
  78. return dev;
  79. }
  80. return NULL;
  81. }
  82. /* Get the MIPS IRQ assignment for a specified device.
  83. * If unassigned, 0 is returned.
  84. * If disabled, 5 is returned.
  85. * If not supported, 6 is returned.
  86. */
  87. unsigned int ssb_mips_irq(struct ssb_device *dev)
  88. {
  89. struct ssb_bus *bus = dev->bus;
  90. struct ssb_device *mdev = bus->mipscore.dev;
  91. u32 irqflag;
  92. u32 ipsflag;
  93. u32 tmp;
  94. unsigned int irq;
  95. irqflag = ssb_irqflag(dev);
  96. if (irqflag == 0x3f)
  97. return 6;
  98. ipsflag = ssb_read32(bus->mipscore.dev, SSB_IPSFLAG);
  99. for (irq = 1; irq <= 4; irq++) {
  100. tmp = ((ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq]);
  101. if (tmp == irqflag)
  102. break;
  103. }
  104. if (irq == 5) {
  105. if ((1 << irqflag) & ssb_read32(mdev, SSB_INTVEC))
  106. irq = 0;
  107. }
  108. return irq;
  109. }
  110. static void clear_irq(struct ssb_bus *bus, unsigned int irq)
  111. {
  112. struct ssb_device *dev = bus->mipscore.dev;
  113. /* Clear the IRQ in the MIPScore backplane registers */
  114. if (irq == 0) {
  115. ssb_write32(dev, SSB_INTVEC, 0);
  116. } else {
  117. ssb_write32(dev, SSB_IPSFLAG,
  118. ssb_read32(dev, SSB_IPSFLAG) |
  119. ipsflag_irq_mask[irq]);
  120. }
  121. }
  122. static void set_irq(struct ssb_device *dev, unsigned int irq)
  123. {
  124. unsigned int oldirq = ssb_mips_irq(dev);
  125. struct ssb_bus *bus = dev->bus;
  126. struct ssb_device *mdev = bus->mipscore.dev;
  127. u32 irqflag = ssb_irqflag(dev);
  128. BUG_ON(oldirq == 6);
  129. dev->irq = irq + 2;
  130. /* clear the old irq */
  131. if (oldirq == 0)
  132. ssb_write32(mdev, SSB_INTVEC, (~(1 << irqflag) & ssb_read32(mdev, SSB_INTVEC)));
  133. else if (oldirq != 5)
  134. clear_irq(bus, oldirq);
  135. /* assign the new one */
  136. if (irq == 0) {
  137. ssb_write32(mdev, SSB_INTVEC, ((1 << irqflag) | ssb_read32(mdev, SSB_INTVEC)));
  138. } else {
  139. u32 ipsflag = ssb_read32(mdev, SSB_IPSFLAG);
  140. if ((ipsflag & ipsflag_irq_mask[irq]) != ipsflag_irq_mask[irq]) {
  141. u32 oldipsflag = (ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq];
  142. struct ssb_device *olddev = find_device(dev, oldipsflag);
  143. if (olddev)
  144. set_irq(olddev, 0);
  145. }
  146. irqflag <<= ipsflag_irq_shift[irq];
  147. irqflag |= (ipsflag & ~ipsflag_irq_mask[irq]);
  148. ssb_write32(mdev, SSB_IPSFLAG, irqflag);
  149. }
  150. dev_dbg(dev->dev, "set_irq: core 0x%04x, irq %d => %d\n",
  151. dev->id.coreid, oldirq+2, irq+2);
  152. }
  153. static void print_irq(struct ssb_device *dev, unsigned int irq)
  154. {
  155. static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
  156. dev_dbg(dev->dev,
  157. "core 0x%04x, irq : %s%s %s%s %s%s %s%s %s%s %s%s %s%s\n",
  158. dev->id.coreid,
  159. irq_name[0], irq == 0 ? "*" : " ",
  160. irq_name[1], irq == 1 ? "*" : " ",
  161. irq_name[2], irq == 2 ? "*" : " ",
  162. irq_name[3], irq == 3 ? "*" : " ",
  163. irq_name[4], irq == 4 ? "*" : " ",
  164. irq_name[5], irq == 5 ? "*" : " ",
  165. irq_name[6], irq == 6 ? "*" : " ");
  166. }
  167. static void dump_irq(struct ssb_bus *bus)
  168. {
  169. int i;
  170. for (i = 0; i < bus->nr_devices; i++) {
  171. struct ssb_device *dev;
  172. dev = &(bus->devices[i]);
  173. print_irq(dev, ssb_mips_irq(dev));
  174. }
  175. }
  176. static void ssb_mips_serial_init(struct ssb_mipscore *mcore)
  177. {
  178. struct ssb_bus *bus = mcore->dev->bus;
  179. if (ssb_extif_available(&bus->extif))
  180. mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports);
  181. else if (ssb_chipco_available(&bus->chipco))
  182. mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);
  183. else
  184. mcore->nr_serial_ports = 0;
  185. }
  186. static void ssb_mips_flash_detect(struct ssb_mipscore *mcore)
  187. {
  188. struct ssb_bus *bus = mcore->dev->bus;
  189. struct ssb_sflash *sflash = &mcore->sflash;
  190. struct ssb_pflash *pflash = &mcore->pflash;
  191. /* When there is no chipcommon on the bus there is 4MB flash */
  192. if (!ssb_chipco_available(&bus->chipco)) {
  193. pflash->present = true;
  194. pflash->buswidth = 2;
  195. pflash->window = SSB_FLASH1;
  196. pflash->window_size = SSB_FLASH1_SZ;
  197. goto ssb_pflash;
  198. }
  199. /* There is ChipCommon, so use it to read info about flash */
  200. switch (bus->chipco.capabilities & SSB_CHIPCO_CAP_FLASHT) {
  201. case SSB_CHIPCO_FLASHT_STSER:
  202. case SSB_CHIPCO_FLASHT_ATSER:
  203. dev_dbg(mcore->dev->dev, "Found serial flash\n");
  204. ssb_sflash_init(&bus->chipco);
  205. break;
  206. case SSB_CHIPCO_FLASHT_PARA:
  207. dev_dbg(mcore->dev->dev, "Found parallel flash\n");
  208. pflash->present = true;
  209. pflash->window = SSB_FLASH2;
  210. pflash->window_size = SSB_FLASH2_SZ;
  211. if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
  212. & SSB_CHIPCO_CFG_DS16) == 0)
  213. pflash->buswidth = 1;
  214. else
  215. pflash->buswidth = 2;
  216. break;
  217. }
  218. ssb_pflash:
  219. if (sflash->present) {
  220. #ifdef CONFIG_BCM47XX
  221. bcm47xx_nvram_init_from_mem(sflash->window, sflash->size);
  222. #endif
  223. } else if (pflash->present) {
  224. #ifdef CONFIG_BCM47XX
  225. bcm47xx_nvram_init_from_mem(pflash->window, pflash->window_size);
  226. #endif
  227. ssb_pflash_data.width = pflash->buswidth;
  228. ssb_pflash_resource.start = pflash->window;
  229. ssb_pflash_resource.end = pflash->window + pflash->window_size;
  230. }
  231. }
  232. u32 ssb_cpu_clock(struct ssb_mipscore *mcore)
  233. {
  234. struct ssb_bus *bus = mcore->dev->bus;
  235. u32 pll_type, n, m, rate = 0;
  236. if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
  237. return ssb_pmu_get_cpu_clock(&bus->chipco);
  238. if (ssb_extif_available(&bus->extif)) {
  239. ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
  240. } else if (ssb_chipco_available(&bus->chipco)) {
  241. ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m);
  242. } else
  243. return 0;
  244. if ((pll_type == SSB_PLLTYPE_5) || (bus->chip_id == 0x5365)) {
  245. rate = 200000000;
  246. } else {
  247. rate = ssb_calc_clock_rate(pll_type, n, m);
  248. }
  249. if (pll_type == SSB_PLLTYPE_6) {
  250. rate *= 2;
  251. }
  252. return rate;
  253. }
  254. void ssb_mipscore_init(struct ssb_mipscore *mcore)
  255. {
  256. struct ssb_bus *bus;
  257. struct ssb_device *dev;
  258. unsigned long hz, ns;
  259. unsigned int irq, i;
  260. if (!mcore->dev)
  261. return; /* We don't have a MIPS core */
  262. dev_dbg(mcore->dev->dev, "Initializing MIPS core...\n");
  263. bus = mcore->dev->bus;
  264. hz = ssb_clockspeed(bus);
  265. if (!hz)
  266. hz = 100000000;
  267. ns = 1000000000 / hz;
  268. if (ssb_extif_available(&bus->extif))
  269. ssb_extif_timing_init(&bus->extif, ns);
  270. else if (ssb_chipco_available(&bus->chipco))
  271. ssb_chipco_timing_init(&bus->chipco, ns);
  272. /* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
  273. for (irq = 2, i = 0; i < bus->nr_devices; i++) {
  274. int mips_irq;
  275. dev = &(bus->devices[i]);
  276. mips_irq = ssb_mips_irq(dev);
  277. if (mips_irq > 4)
  278. dev->irq = 0;
  279. else
  280. dev->irq = mips_irq + 2;
  281. if (dev->irq > 5)
  282. continue;
  283. switch (dev->id.coreid) {
  284. case SSB_DEV_USB11_HOST:
  285. /* shouldn't need a separate irq line for non-4710, most of them have a proper
  286. * external usb controller on the pci */
  287. if ((bus->chip_id == 0x4710) && (irq <= 4)) {
  288. set_irq(dev, irq++);
  289. }
  290. break;
  291. case SSB_DEV_PCI:
  292. case SSB_DEV_ETHERNET:
  293. case SSB_DEV_ETHERNET_GBIT:
  294. case SSB_DEV_80211:
  295. case SSB_DEV_USB20_HOST:
  296. /* These devices get their own IRQ line if available, the rest goes on IRQ0 */
  297. if (irq <= 4) {
  298. set_irq(dev, irq++);
  299. break;
  300. }
  301. fallthrough;
  302. case SSB_DEV_EXTIF:
  303. set_irq(dev, 0);
  304. break;
  305. }
  306. }
  307. dev_dbg(mcore->dev->dev, "after irq reconfiguration\n");
  308. dump_irq(bus);
  309. ssb_mips_serial_init(mcore);
  310. ssb_mips_flash_detect(mcore);
  311. }