driver_gige.c 7.3 KB

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  1. /*
  2. * Sonics Silicon Backplane
  3. * Broadcom Gigabit Ethernet core driver
  4. *
  5. * Copyright 2008, Broadcom Corporation
  6. * Copyright 2008, Michael Buesch <m@bues.ch>
  7. *
  8. * Licensed under the GNU/GPL. See COPYING for details.
  9. */
  10. #include <linux/ssb/ssb.h>
  11. #include <linux/ssb/ssb_driver_gige.h>
  12. #include <linux/export.h>
  13. #include <linux/pci.h>
  14. #include <linux/pci_regs.h>
  15. #include <linux/slab.h>
  16. /*
  17. MODULE_DESCRIPTION("SSB Broadcom Gigabit Ethernet driver");
  18. MODULE_AUTHOR("Michael Buesch");
  19. MODULE_LICENSE("GPL");
  20. */
  21. static const struct ssb_device_id ssb_gige_tbl[] = {
  22. SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_ETHERNET_GBIT, SSB_ANY_REV),
  23. {},
  24. };
  25. /* MODULE_DEVICE_TABLE(ssb, ssb_gige_tbl); */
  26. static inline u8 gige_read8(struct ssb_gige *dev, u16 offset)
  27. {
  28. return ssb_read8(dev->dev, offset);
  29. }
  30. static inline u16 gige_read16(struct ssb_gige *dev, u16 offset)
  31. {
  32. return ssb_read16(dev->dev, offset);
  33. }
  34. static inline u32 gige_read32(struct ssb_gige *dev, u16 offset)
  35. {
  36. return ssb_read32(dev->dev, offset);
  37. }
  38. static inline void gige_write8(struct ssb_gige *dev,
  39. u16 offset, u8 value)
  40. {
  41. ssb_write8(dev->dev, offset, value);
  42. }
  43. static inline void gige_write16(struct ssb_gige *dev,
  44. u16 offset, u16 value)
  45. {
  46. ssb_write16(dev->dev, offset, value);
  47. }
  48. static inline void gige_write32(struct ssb_gige *dev,
  49. u16 offset, u32 value)
  50. {
  51. ssb_write32(dev->dev, offset, value);
  52. }
  53. static inline
  54. u8 gige_pcicfg_read8(struct ssb_gige *dev, unsigned int offset)
  55. {
  56. BUG_ON(offset >= 256);
  57. return gige_read8(dev, SSB_GIGE_PCICFG + offset);
  58. }
  59. static inline
  60. u16 gige_pcicfg_read16(struct ssb_gige *dev, unsigned int offset)
  61. {
  62. BUG_ON(offset >= 256);
  63. return gige_read16(dev, SSB_GIGE_PCICFG + offset);
  64. }
  65. static inline
  66. u32 gige_pcicfg_read32(struct ssb_gige *dev, unsigned int offset)
  67. {
  68. BUG_ON(offset >= 256);
  69. return gige_read32(dev, SSB_GIGE_PCICFG + offset);
  70. }
  71. static inline
  72. void gige_pcicfg_write8(struct ssb_gige *dev,
  73. unsigned int offset, u8 value)
  74. {
  75. BUG_ON(offset >= 256);
  76. gige_write8(dev, SSB_GIGE_PCICFG + offset, value);
  77. }
  78. static inline
  79. void gige_pcicfg_write16(struct ssb_gige *dev,
  80. unsigned int offset, u16 value)
  81. {
  82. BUG_ON(offset >= 256);
  83. gige_write16(dev, SSB_GIGE_PCICFG + offset, value);
  84. }
  85. static inline
  86. void gige_pcicfg_write32(struct ssb_gige *dev,
  87. unsigned int offset, u32 value)
  88. {
  89. BUG_ON(offset >= 256);
  90. gige_write32(dev, SSB_GIGE_PCICFG + offset, value);
  91. }
  92. static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,
  93. int reg, int size, u32 *val)
  94. {
  95. struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
  96. unsigned long flags;
  97. if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0))
  98. return PCIBIOS_DEVICE_NOT_FOUND;
  99. if (reg >= 256)
  100. return PCIBIOS_DEVICE_NOT_FOUND;
  101. spin_lock_irqsave(&dev->lock, flags);
  102. switch (size) {
  103. case 1:
  104. *val = gige_pcicfg_read8(dev, reg);
  105. break;
  106. case 2:
  107. *val = gige_pcicfg_read16(dev, reg);
  108. break;
  109. case 4:
  110. *val = gige_pcicfg_read32(dev, reg);
  111. break;
  112. default:
  113. WARN_ON(1);
  114. }
  115. spin_unlock_irqrestore(&dev->lock, flags);
  116. return PCIBIOS_SUCCESSFUL;
  117. }
  118. static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,
  119. int reg, int size, u32 val)
  120. {
  121. struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
  122. unsigned long flags;
  123. if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0))
  124. return PCIBIOS_DEVICE_NOT_FOUND;
  125. if (reg >= 256)
  126. return PCIBIOS_DEVICE_NOT_FOUND;
  127. spin_lock_irqsave(&dev->lock, flags);
  128. switch (size) {
  129. case 1:
  130. gige_pcicfg_write8(dev, reg, val);
  131. break;
  132. case 2:
  133. gige_pcicfg_write16(dev, reg, val);
  134. break;
  135. case 4:
  136. gige_pcicfg_write32(dev, reg, val);
  137. break;
  138. default:
  139. WARN_ON(1);
  140. }
  141. spin_unlock_irqrestore(&dev->lock, flags);
  142. return PCIBIOS_SUCCESSFUL;
  143. }
  144. static int ssb_gige_probe(struct ssb_device *sdev,
  145. const struct ssb_device_id *id)
  146. {
  147. struct ssb_gige *dev;
  148. u32 base, tmslow, tmshigh;
  149. dev = kzalloc(sizeof(*dev), GFP_KERNEL);
  150. if (!dev)
  151. return -ENOMEM;
  152. dev->dev = sdev;
  153. spin_lock_init(&dev->lock);
  154. dev->pci_controller.pci_ops = &dev->pci_ops;
  155. dev->pci_controller.io_resource = &dev->io_resource;
  156. dev->pci_controller.mem_resource = &dev->mem_resource;
  157. dev->pci_controller.io_map_base = 0x800;
  158. dev->pci_ops.read = ssb_gige_pci_read_config;
  159. dev->pci_ops.write = ssb_gige_pci_write_config;
  160. dev->io_resource.name = SSB_GIGE_IO_RES_NAME;
  161. dev->io_resource.start = 0x800;
  162. dev->io_resource.end = 0x8FF;
  163. dev->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
  164. if (!ssb_device_is_enabled(sdev))
  165. ssb_device_enable(sdev, 0);
  166. /* Setup BAR0. This is a 64k MMIO region. */
  167. base = ssb_admatch_base(ssb_read32(sdev, SSB_ADMATCH1));
  168. gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_0, base);
  169. gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_1, 0);
  170. dev->mem_resource.name = SSB_GIGE_MEM_RES_NAME;
  171. dev->mem_resource.start = base;
  172. dev->mem_resource.end = base + 0x10000 - 1;
  173. dev->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
  174. /* Enable the memory region. */
  175. gige_pcicfg_write16(dev, PCI_COMMAND,
  176. gige_pcicfg_read16(dev, PCI_COMMAND)
  177. | PCI_COMMAND_MEMORY);
  178. /* Write flushing is controlled by the Flush Status Control register.
  179. * We want to flush every register write with a timeout and we want
  180. * to disable the IRQ mask while flushing to avoid concurrency.
  181. * Note that automatic write flushing does _not_ work from
  182. * an IRQ handler. The driver must flush manually by reading a register.
  183. */
  184. gige_write32(dev, SSB_GIGE_SHIM_FLUSHSTAT, 0x00000068);
  185. /* Check if we have an RGMII or GMII PHY-bus.
  186. * On RGMII do not bypass the DLLs */
  187. tmslow = ssb_read32(sdev, SSB_TMSLOW);
  188. tmshigh = ssb_read32(sdev, SSB_TMSHIGH);
  189. if (tmshigh & SSB_GIGE_TMSHIGH_RGMII) {
  190. tmslow &= ~SSB_GIGE_TMSLOW_TXBYPASS;
  191. tmslow &= ~SSB_GIGE_TMSLOW_RXBYPASS;
  192. dev->has_rgmii = 1;
  193. } else {
  194. tmslow |= SSB_GIGE_TMSLOW_TXBYPASS;
  195. tmslow |= SSB_GIGE_TMSLOW_RXBYPASS;
  196. dev->has_rgmii = 0;
  197. }
  198. tmslow |= SSB_GIGE_TMSLOW_DLLEN;
  199. ssb_write32(sdev, SSB_TMSLOW, tmslow);
  200. ssb_set_drvdata(sdev, dev);
  201. register_pci_controller(&dev->pci_controller);
  202. return 0;
  203. }
  204. bool pdev_is_ssb_gige_core(struct pci_dev *pdev)
  205. {
  206. if (!pdev->resource[0].name)
  207. return false;
  208. return (strcmp(pdev->resource[0].name, SSB_GIGE_MEM_RES_NAME) == 0);
  209. }
  210. EXPORT_SYMBOL(pdev_is_ssb_gige_core);
  211. int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
  212. struct pci_dev *pdev)
  213. {
  214. struct ssb_gige *dev = ssb_get_drvdata(sdev);
  215. struct resource *res;
  216. if (pdev->bus->ops != &dev->pci_ops) {
  217. /* The PCI device is not on this SSB GigE bridge device. */
  218. return -ENODEV;
  219. }
  220. /* Fixup the PCI resources. */
  221. res = &(pdev->resource[0]);
  222. res->flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
  223. res->name = dev->mem_resource.name;
  224. res->start = dev->mem_resource.start;
  225. res->end = dev->mem_resource.end;
  226. /* Fixup interrupt lines. */
  227. pdev->irq = ssb_mips_irq(sdev) + 2;
  228. pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, pdev->irq);
  229. return 0;
  230. }
  231. int ssb_gige_map_irq(struct ssb_device *sdev,
  232. const struct pci_dev *pdev)
  233. {
  234. struct ssb_gige *dev = ssb_get_drvdata(sdev);
  235. if (pdev->bus->ops != &dev->pci_ops) {
  236. /* The PCI device is not on this SSB GigE bridge device. */
  237. return -ENODEV;
  238. }
  239. return ssb_mips_irq(sdev) + 2;
  240. }
  241. static struct ssb_driver ssb_gige_driver = {
  242. .name = "BCM-GigE",
  243. .id_table = ssb_gige_tbl,
  244. .probe = ssb_gige_probe,
  245. };
  246. int ssb_gige_init(void)
  247. {
  248. return ssb_driver_register(&ssb_gige_driver);
  249. }