spi-xlp.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2003-2015 Broadcom Corporation
  4. * All Rights Reserved
  5. */
  6. #include <linux/acpi.h>
  7. #include <linux/clk.h>
  8. #include <linux/kernel.h>
  9. #include <linux/module.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/spi/spi.h>
  12. #include <linux/of.h>
  13. #include <linux/interrupt.h>
  14. /* SPI Configuration Register */
  15. #define XLP_SPI_CONFIG 0x00
  16. #define XLP_SPI_CPHA BIT(0)
  17. #define XLP_SPI_CPOL BIT(1)
  18. #define XLP_SPI_CS_POL BIT(2)
  19. #define XLP_SPI_TXMISO_EN BIT(3)
  20. #define XLP_SPI_TXMOSI_EN BIT(4)
  21. #define XLP_SPI_RXMISO_EN BIT(5)
  22. #define XLP_SPI_CS_LSBFE BIT(10)
  23. #define XLP_SPI_RXCAP_EN BIT(11)
  24. /* SPI Frequency Divider Register */
  25. #define XLP_SPI_FDIV 0x04
  26. /* SPI Command Register */
  27. #define XLP_SPI_CMD 0x08
  28. #define XLP_SPI_CMD_IDLE_MASK 0x0
  29. #define XLP_SPI_CMD_TX_MASK 0x1
  30. #define XLP_SPI_CMD_RX_MASK 0x2
  31. #define XLP_SPI_CMD_TXRX_MASK 0x3
  32. #define XLP_SPI_CMD_CONT BIT(4)
  33. #define XLP_SPI_XFR_BITCNT_SHIFT 16
  34. /* SPI Status Register */
  35. #define XLP_SPI_STATUS 0x0c
  36. #define XLP_SPI_XFR_PENDING BIT(0)
  37. #define XLP_SPI_XFR_DONE BIT(1)
  38. #define XLP_SPI_TX_INT BIT(2)
  39. #define XLP_SPI_RX_INT BIT(3)
  40. #define XLP_SPI_TX_UF BIT(4)
  41. #define XLP_SPI_RX_OF BIT(5)
  42. #define XLP_SPI_STAT_MASK 0x3f
  43. /* SPI Interrupt Enable Register */
  44. #define XLP_SPI_INTR_EN 0x10
  45. #define XLP_SPI_INTR_DONE BIT(0)
  46. #define XLP_SPI_INTR_TXTH BIT(1)
  47. #define XLP_SPI_INTR_RXTH BIT(2)
  48. #define XLP_SPI_INTR_TXUF BIT(3)
  49. #define XLP_SPI_INTR_RXOF BIT(4)
  50. /* SPI FIFO Threshold Register */
  51. #define XLP_SPI_FIFO_THRESH 0x14
  52. /* SPI FIFO Word Count Register */
  53. #define XLP_SPI_FIFO_WCNT 0x18
  54. #define XLP_SPI_RXFIFO_WCNT_MASK 0xf
  55. #define XLP_SPI_TXFIFO_WCNT_MASK 0xf0
  56. #define XLP_SPI_TXFIFO_WCNT_SHIFT 4
  57. /* SPI Transmit Data FIFO Register */
  58. #define XLP_SPI_TXDATA_FIFO 0x1c
  59. /* SPI Receive Data FIFO Register */
  60. #define XLP_SPI_RXDATA_FIFO 0x20
  61. /* SPI System Control Register */
  62. #define XLP_SPI_SYSCTRL 0x100
  63. #define XLP_SPI_SYS_RESET BIT(0)
  64. #define XLP_SPI_SYS_CLKDIS BIT(1)
  65. #define XLP_SPI_SYS_PMEN BIT(8)
  66. #define SPI_CS_OFFSET 0x40
  67. #define XLP_SPI_TXRXTH 0x80
  68. #define XLP_SPI_FIFO_SIZE 8
  69. #define XLP_SPI_MAX_CS 4
  70. #define XLP_SPI_DEFAULT_FREQ 133333333
  71. #define XLP_SPI_FDIV_MIN 4
  72. #define XLP_SPI_FDIV_MAX 65535
  73. /*
  74. * SPI can transfer only 28 bytes properly at a time. So split the
  75. * transfer into 28 bytes size.
  76. */
  77. #define XLP_SPI_XFER_SIZE 28
  78. struct xlp_spi_priv {
  79. struct device dev; /* device structure */
  80. void __iomem *base; /* spi registers base address */
  81. const u8 *tx_buf; /* tx data buffer */
  82. u8 *rx_buf; /* rx data buffer */
  83. int tx_len; /* tx xfer length */
  84. int rx_len; /* rx xfer length */
  85. int txerrors; /* TXFIFO underflow count */
  86. int rxerrors; /* RXFIFO overflow count */
  87. int cs; /* slave device chip select */
  88. u32 spi_clk; /* spi clock frequency */
  89. bool cmd_cont; /* cs active */
  90. struct completion done; /* completion notification */
  91. };
  92. static inline u32 xlp_spi_reg_read(struct xlp_spi_priv *priv,
  93. int cs, int regoff)
  94. {
  95. return readl(priv->base + regoff + cs * SPI_CS_OFFSET);
  96. }
  97. static inline void xlp_spi_reg_write(struct xlp_spi_priv *priv, int cs,
  98. int regoff, u32 val)
  99. {
  100. writel(val, priv->base + regoff + cs * SPI_CS_OFFSET);
  101. }
  102. static inline void xlp_spi_sysctl_write(struct xlp_spi_priv *priv,
  103. int regoff, u32 val)
  104. {
  105. writel(val, priv->base + regoff);
  106. }
  107. /*
  108. * Setup global SPI_SYSCTRL register for all SPI channels.
  109. */
  110. static void xlp_spi_sysctl_setup(struct xlp_spi_priv *xspi)
  111. {
  112. int cs;
  113. for (cs = 0; cs < XLP_SPI_MAX_CS; cs++)
  114. xlp_spi_sysctl_write(xspi, XLP_SPI_SYSCTRL,
  115. XLP_SPI_SYS_RESET << cs);
  116. xlp_spi_sysctl_write(xspi, XLP_SPI_SYSCTRL, XLP_SPI_SYS_PMEN);
  117. }
  118. static int xlp_spi_setup(struct spi_device *spi)
  119. {
  120. struct xlp_spi_priv *xspi;
  121. u32 fdiv, cfg;
  122. int cs;
  123. xspi = spi_master_get_devdata(spi->master);
  124. cs = spi->chip_select;
  125. /*
  126. * The value of fdiv must be between 4 and 65535.
  127. */
  128. fdiv = DIV_ROUND_UP(xspi->spi_clk, spi->max_speed_hz);
  129. if (fdiv > XLP_SPI_FDIV_MAX)
  130. fdiv = XLP_SPI_FDIV_MAX;
  131. else if (fdiv < XLP_SPI_FDIV_MIN)
  132. fdiv = XLP_SPI_FDIV_MIN;
  133. xlp_spi_reg_write(xspi, cs, XLP_SPI_FDIV, fdiv);
  134. xlp_spi_reg_write(xspi, cs, XLP_SPI_FIFO_THRESH, XLP_SPI_TXRXTH);
  135. cfg = xlp_spi_reg_read(xspi, cs, XLP_SPI_CONFIG);
  136. if (spi->mode & SPI_CPHA)
  137. cfg |= XLP_SPI_CPHA;
  138. else
  139. cfg &= ~XLP_SPI_CPHA;
  140. if (spi->mode & SPI_CPOL)
  141. cfg |= XLP_SPI_CPOL;
  142. else
  143. cfg &= ~XLP_SPI_CPOL;
  144. if (!(spi->mode & SPI_CS_HIGH))
  145. cfg |= XLP_SPI_CS_POL;
  146. else
  147. cfg &= ~XLP_SPI_CS_POL;
  148. if (spi->mode & SPI_LSB_FIRST)
  149. cfg |= XLP_SPI_CS_LSBFE;
  150. else
  151. cfg &= ~XLP_SPI_CS_LSBFE;
  152. cfg |= XLP_SPI_TXMOSI_EN | XLP_SPI_RXMISO_EN;
  153. if (fdiv == 4)
  154. cfg |= XLP_SPI_RXCAP_EN;
  155. xlp_spi_reg_write(xspi, cs, XLP_SPI_CONFIG, cfg);
  156. return 0;
  157. }
  158. static void xlp_spi_read_rxfifo(struct xlp_spi_priv *xspi)
  159. {
  160. u32 rx_data, rxfifo_cnt;
  161. int i, j, nbytes;
  162. rxfifo_cnt = xlp_spi_reg_read(xspi, xspi->cs, XLP_SPI_FIFO_WCNT);
  163. rxfifo_cnt &= XLP_SPI_RXFIFO_WCNT_MASK;
  164. while (rxfifo_cnt) {
  165. rx_data = xlp_spi_reg_read(xspi, xspi->cs, XLP_SPI_RXDATA_FIFO);
  166. j = 0;
  167. nbytes = min(xspi->rx_len, 4);
  168. for (i = nbytes - 1; i >= 0; i--, j++)
  169. xspi->rx_buf[i] = (rx_data >> (j * 8)) & 0xff;
  170. xspi->rx_len -= nbytes;
  171. xspi->rx_buf += nbytes;
  172. rxfifo_cnt--;
  173. }
  174. }
  175. static void xlp_spi_fill_txfifo(struct xlp_spi_priv *xspi)
  176. {
  177. u32 tx_data, txfifo_cnt;
  178. int i, j, nbytes;
  179. txfifo_cnt = xlp_spi_reg_read(xspi, xspi->cs, XLP_SPI_FIFO_WCNT);
  180. txfifo_cnt &= XLP_SPI_TXFIFO_WCNT_MASK;
  181. txfifo_cnt >>= XLP_SPI_TXFIFO_WCNT_SHIFT;
  182. while (xspi->tx_len && (txfifo_cnt < XLP_SPI_FIFO_SIZE)) {
  183. j = 0;
  184. tx_data = 0;
  185. nbytes = min(xspi->tx_len, 4);
  186. for (i = nbytes - 1; i >= 0; i--, j++)
  187. tx_data |= xspi->tx_buf[i] << (j * 8);
  188. xlp_spi_reg_write(xspi, xspi->cs, XLP_SPI_TXDATA_FIFO, tx_data);
  189. xspi->tx_len -= nbytes;
  190. xspi->tx_buf += nbytes;
  191. txfifo_cnt++;
  192. }
  193. }
  194. static irqreturn_t xlp_spi_interrupt(int irq, void *dev_id)
  195. {
  196. struct xlp_spi_priv *xspi = dev_id;
  197. u32 stat;
  198. stat = xlp_spi_reg_read(xspi, xspi->cs, XLP_SPI_STATUS) &
  199. XLP_SPI_STAT_MASK;
  200. if (!stat)
  201. return IRQ_NONE;
  202. if (stat & XLP_SPI_TX_INT) {
  203. if (xspi->tx_len)
  204. xlp_spi_fill_txfifo(xspi);
  205. if (stat & XLP_SPI_TX_UF)
  206. xspi->txerrors++;
  207. }
  208. if (stat & XLP_SPI_RX_INT) {
  209. if (xspi->rx_len)
  210. xlp_spi_read_rxfifo(xspi);
  211. if (stat & XLP_SPI_RX_OF)
  212. xspi->rxerrors++;
  213. }
  214. /* write status back to clear interrupts */
  215. xlp_spi_reg_write(xspi, xspi->cs, XLP_SPI_STATUS, stat);
  216. if (stat & XLP_SPI_XFR_DONE)
  217. complete(&xspi->done);
  218. return IRQ_HANDLED;
  219. }
  220. static void xlp_spi_send_cmd(struct xlp_spi_priv *xspi, int xfer_len,
  221. int cmd_cont)
  222. {
  223. u32 cmd = 0;
  224. if (xspi->tx_buf)
  225. cmd |= XLP_SPI_CMD_TX_MASK;
  226. if (xspi->rx_buf)
  227. cmd |= XLP_SPI_CMD_RX_MASK;
  228. if (cmd_cont)
  229. cmd |= XLP_SPI_CMD_CONT;
  230. cmd |= ((xfer_len * 8 - 1) << XLP_SPI_XFR_BITCNT_SHIFT);
  231. xlp_spi_reg_write(xspi, xspi->cs, XLP_SPI_CMD, cmd);
  232. }
  233. static int xlp_spi_xfer_block(struct xlp_spi_priv *xs,
  234. const unsigned char *tx_buf,
  235. unsigned char *rx_buf, int xfer_len, int cmd_cont)
  236. {
  237. int timeout;
  238. u32 intr_mask = 0;
  239. xs->tx_buf = tx_buf;
  240. xs->rx_buf = rx_buf;
  241. xs->tx_len = (xs->tx_buf == NULL) ? 0 : xfer_len;
  242. xs->rx_len = (xs->rx_buf == NULL) ? 0 : xfer_len;
  243. xs->txerrors = xs->rxerrors = 0;
  244. /* fill TXDATA_FIFO, then send the CMD */
  245. if (xs->tx_len)
  246. xlp_spi_fill_txfifo(xs);
  247. xlp_spi_send_cmd(xs, xfer_len, cmd_cont);
  248. /*
  249. * We are getting some spurious tx interrupts, so avoid enabling
  250. * tx interrupts when only rx is in process.
  251. * Enable all the interrupts in tx case.
  252. */
  253. if (xs->tx_len)
  254. intr_mask |= XLP_SPI_INTR_TXTH | XLP_SPI_INTR_TXUF |
  255. XLP_SPI_INTR_RXTH | XLP_SPI_INTR_RXOF;
  256. else
  257. intr_mask |= XLP_SPI_INTR_RXTH | XLP_SPI_INTR_RXOF;
  258. intr_mask |= XLP_SPI_INTR_DONE;
  259. xlp_spi_reg_write(xs, xs->cs, XLP_SPI_INTR_EN, intr_mask);
  260. timeout = wait_for_completion_timeout(&xs->done,
  261. msecs_to_jiffies(1000));
  262. /* Disable interrupts */
  263. xlp_spi_reg_write(xs, xs->cs, XLP_SPI_INTR_EN, 0x0);
  264. if (!timeout) {
  265. dev_err(&xs->dev, "xfer timedout!\n");
  266. goto out;
  267. }
  268. if (xs->txerrors || xs->rxerrors)
  269. dev_err(&xs->dev, "Over/Underflow rx %d tx %d xfer %d!\n",
  270. xs->rxerrors, xs->txerrors, xfer_len);
  271. return xfer_len;
  272. out:
  273. return -ETIMEDOUT;
  274. }
  275. static int xlp_spi_txrx_bufs(struct xlp_spi_priv *xs, struct spi_transfer *t)
  276. {
  277. int bytesleft, sz;
  278. unsigned char *rx_buf;
  279. const unsigned char *tx_buf;
  280. tx_buf = t->tx_buf;
  281. rx_buf = t->rx_buf;
  282. bytesleft = t->len;
  283. while (bytesleft) {
  284. if (bytesleft > XLP_SPI_XFER_SIZE)
  285. sz = xlp_spi_xfer_block(xs, tx_buf, rx_buf,
  286. XLP_SPI_XFER_SIZE, 1);
  287. else
  288. sz = xlp_spi_xfer_block(xs, tx_buf, rx_buf,
  289. bytesleft, xs->cmd_cont);
  290. if (sz < 0)
  291. return sz;
  292. bytesleft -= sz;
  293. if (tx_buf)
  294. tx_buf += sz;
  295. if (rx_buf)
  296. rx_buf += sz;
  297. }
  298. return bytesleft;
  299. }
  300. static int xlp_spi_transfer_one(struct spi_master *master,
  301. struct spi_device *spi,
  302. struct spi_transfer *t)
  303. {
  304. struct xlp_spi_priv *xspi = spi_master_get_devdata(master);
  305. int ret = 0;
  306. xspi->cs = spi->chip_select;
  307. xspi->dev = spi->dev;
  308. if (spi_transfer_is_last(master, t))
  309. xspi->cmd_cont = 0;
  310. else
  311. xspi->cmd_cont = 1;
  312. if (xlp_spi_txrx_bufs(xspi, t))
  313. ret = -EIO;
  314. spi_finalize_current_transfer(master);
  315. return ret;
  316. }
  317. static int xlp_spi_probe(struct platform_device *pdev)
  318. {
  319. struct spi_master *master;
  320. struct xlp_spi_priv *xspi;
  321. struct clk *clk;
  322. int irq, err;
  323. xspi = devm_kzalloc(&pdev->dev, sizeof(*xspi), GFP_KERNEL);
  324. if (!xspi)
  325. return -ENOMEM;
  326. xspi->base = devm_platform_ioremap_resource(pdev, 0);
  327. if (IS_ERR(xspi->base))
  328. return PTR_ERR(xspi->base);
  329. irq = platform_get_irq(pdev, 0);
  330. if (irq < 0)
  331. return irq;
  332. err = devm_request_irq(&pdev->dev, irq, xlp_spi_interrupt, 0,
  333. pdev->name, xspi);
  334. if (err) {
  335. dev_err(&pdev->dev, "unable to request irq %d\n", irq);
  336. return err;
  337. }
  338. clk = devm_clk_get(&pdev->dev, NULL);
  339. if (IS_ERR(clk)) {
  340. dev_err(&pdev->dev, "could not get spi clock\n");
  341. return PTR_ERR(clk);
  342. }
  343. xspi->spi_clk = clk_get_rate(clk);
  344. master = spi_alloc_master(&pdev->dev, 0);
  345. if (!master) {
  346. dev_err(&pdev->dev, "could not alloc master\n");
  347. return -ENOMEM;
  348. }
  349. master->bus_num = 0;
  350. master->num_chipselect = XLP_SPI_MAX_CS;
  351. master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
  352. master->setup = xlp_spi_setup;
  353. master->transfer_one = xlp_spi_transfer_one;
  354. master->dev.of_node = pdev->dev.of_node;
  355. init_completion(&xspi->done);
  356. spi_master_set_devdata(master, xspi);
  357. xlp_spi_sysctl_setup(xspi);
  358. /* register spi controller */
  359. err = devm_spi_register_master(&pdev->dev, master);
  360. if (err) {
  361. dev_err(&pdev->dev, "spi register master failed!\n");
  362. spi_master_put(master);
  363. return err;
  364. }
  365. return 0;
  366. }
  367. #ifdef CONFIG_ACPI
  368. static const struct acpi_device_id xlp_spi_acpi_match[] = {
  369. { "BRCM900D", 0 },
  370. { "CAV900D", 0 },
  371. { },
  372. };
  373. MODULE_DEVICE_TABLE(acpi, xlp_spi_acpi_match);
  374. #endif
  375. static const struct of_device_id xlp_spi_dt_id[] = {
  376. { .compatible = "netlogic,xlp832-spi" },
  377. { },
  378. };
  379. MODULE_DEVICE_TABLE(of, xlp_spi_dt_id);
  380. static struct platform_driver xlp_spi_driver = {
  381. .probe = xlp_spi_probe,
  382. .driver = {
  383. .name = "xlp-spi",
  384. .of_match_table = xlp_spi_dt_id,
  385. .acpi_match_table = ACPI_PTR(xlp_spi_acpi_match),
  386. },
  387. };
  388. module_platform_driver(xlp_spi_driver);
  389. MODULE_AUTHOR("Kamlakant Patel <kamlakant.patel@broadcom.com>");
  390. MODULE_DESCRIPTION("Netlogic XLP SPI controller driver");
  391. MODULE_LICENSE("GPL v2");