spi-xilinx.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Xilinx SPI controller driver (master mode only)
  4. *
  5. * Author: MontaVista Software, Inc.
  6. * source@mvista.com
  7. *
  8. * Copyright (c) 2010 Secret Lab Technologies, Ltd.
  9. * Copyright (c) 2009 Intel Corporation
  10. * 2002-2007 (c) MontaVista Software, Inc.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/of.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/spi/spi.h>
  17. #include <linux/spi/spi_bitbang.h>
  18. #include <linux/spi/xilinx_spi.h>
  19. #include <linux/io.h>
  20. #define XILINX_SPI_MAX_CS 32
  21. #define XILINX_SPI_NAME "xilinx_spi"
  22. /* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e)
  23. * Product Specification", DS464
  24. */
  25. #define XSPI_CR_OFFSET 0x60 /* Control Register */
  26. #define XSPI_CR_LOOP 0x01
  27. #define XSPI_CR_ENABLE 0x02
  28. #define XSPI_CR_MASTER_MODE 0x04
  29. #define XSPI_CR_CPOL 0x08
  30. #define XSPI_CR_CPHA 0x10
  31. #define XSPI_CR_MODE_MASK (XSPI_CR_CPHA | XSPI_CR_CPOL | \
  32. XSPI_CR_LSB_FIRST | XSPI_CR_LOOP)
  33. #define XSPI_CR_TXFIFO_RESET 0x20
  34. #define XSPI_CR_RXFIFO_RESET 0x40
  35. #define XSPI_CR_MANUAL_SSELECT 0x80
  36. #define XSPI_CR_TRANS_INHIBIT 0x100
  37. #define XSPI_CR_LSB_FIRST 0x200
  38. #define XSPI_SR_OFFSET 0x64 /* Status Register */
  39. #define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */
  40. #define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */
  41. #define XSPI_SR_TX_EMPTY_MASK 0x04 /* Transmit FIFO is empty */
  42. #define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */
  43. #define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */
  44. #define XSPI_TXD_OFFSET 0x68 /* Data Transmit Register */
  45. #define XSPI_RXD_OFFSET 0x6c /* Data Receive Register */
  46. #define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */
  47. /* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414
  48. * IPIF registers are 32 bit
  49. */
  50. #define XIPIF_V123B_DGIER_OFFSET 0x1c /* IPIF global int enable reg */
  51. #define XIPIF_V123B_GINTR_ENABLE 0x80000000
  52. #define XIPIF_V123B_IISR_OFFSET 0x20 /* IPIF interrupt status reg */
  53. #define XIPIF_V123B_IIER_OFFSET 0x28 /* IPIF interrupt enable reg */
  54. #define XSPI_INTR_MODE_FAULT 0x01 /* Mode fault error */
  55. #define XSPI_INTR_SLAVE_MODE_FAULT 0x02 /* Selected as slave while
  56. * disabled */
  57. #define XSPI_INTR_TX_EMPTY 0x04 /* TxFIFO is empty */
  58. #define XSPI_INTR_TX_UNDERRUN 0x08 /* TxFIFO was underrun */
  59. #define XSPI_INTR_RX_FULL 0x10 /* RxFIFO is full */
  60. #define XSPI_INTR_RX_OVERRUN 0x20 /* RxFIFO was overrun */
  61. #define XSPI_INTR_TX_HALF_EMPTY 0x40 /* TxFIFO is half empty */
  62. #define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */
  63. #define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */
  64. struct xilinx_spi {
  65. /* bitbang has to be first */
  66. struct spi_bitbang bitbang;
  67. struct completion done;
  68. void __iomem *regs; /* virt. address of the control registers */
  69. int irq;
  70. u8 *rx_ptr; /* pointer in the Tx buffer */
  71. const u8 *tx_ptr; /* pointer in the Rx buffer */
  72. u8 bytes_per_word;
  73. int buffer_size; /* buffer size in words */
  74. u32 cs_inactive; /* Level of the CS pins when inactive*/
  75. unsigned int (*read_fn)(void __iomem *);
  76. void (*write_fn)(u32, void __iomem *);
  77. };
  78. static void xspi_write32(u32 val, void __iomem *addr)
  79. {
  80. iowrite32(val, addr);
  81. }
  82. static unsigned int xspi_read32(void __iomem *addr)
  83. {
  84. return ioread32(addr);
  85. }
  86. static void xspi_write32_be(u32 val, void __iomem *addr)
  87. {
  88. iowrite32be(val, addr);
  89. }
  90. static unsigned int xspi_read32_be(void __iomem *addr)
  91. {
  92. return ioread32be(addr);
  93. }
  94. static void xilinx_spi_tx(struct xilinx_spi *xspi)
  95. {
  96. u32 data = 0;
  97. if (!xspi->tx_ptr) {
  98. xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
  99. return;
  100. }
  101. switch (xspi->bytes_per_word) {
  102. case 1:
  103. data = *(u8 *)(xspi->tx_ptr);
  104. break;
  105. case 2:
  106. data = *(u16 *)(xspi->tx_ptr);
  107. break;
  108. case 4:
  109. data = *(u32 *)(xspi->tx_ptr);
  110. break;
  111. }
  112. xspi->write_fn(data, xspi->regs + XSPI_TXD_OFFSET);
  113. xspi->tx_ptr += xspi->bytes_per_word;
  114. }
  115. static void xilinx_spi_rx(struct xilinx_spi *xspi)
  116. {
  117. u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
  118. if (!xspi->rx_ptr)
  119. return;
  120. switch (xspi->bytes_per_word) {
  121. case 1:
  122. *(u8 *)(xspi->rx_ptr) = data;
  123. break;
  124. case 2:
  125. *(u16 *)(xspi->rx_ptr) = data;
  126. break;
  127. case 4:
  128. *(u32 *)(xspi->rx_ptr) = data;
  129. break;
  130. }
  131. xspi->rx_ptr += xspi->bytes_per_word;
  132. }
  133. static void xspi_init_hw(struct xilinx_spi *xspi)
  134. {
  135. void __iomem *regs_base = xspi->regs;
  136. /* Reset the SPI device */
  137. xspi->write_fn(XIPIF_V123B_RESET_MASK,
  138. regs_base + XIPIF_V123B_RESETR_OFFSET);
  139. /* Enable the transmit empty interrupt, which we use to determine
  140. * progress on the transmission.
  141. */
  142. xspi->write_fn(XSPI_INTR_TX_EMPTY,
  143. regs_base + XIPIF_V123B_IIER_OFFSET);
  144. /* Disable the global IPIF interrupt */
  145. xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET);
  146. /* Deselect the slave on the SPI bus */
  147. xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET);
  148. /* Disable the transmitter, enable Manual Slave Select Assertion,
  149. * put SPI controller into master mode, and enable it */
  150. xspi->write_fn(XSPI_CR_MANUAL_SSELECT | XSPI_CR_MASTER_MODE |
  151. XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET | XSPI_CR_RXFIFO_RESET,
  152. regs_base + XSPI_CR_OFFSET);
  153. }
  154. static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
  155. {
  156. struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
  157. u16 cr;
  158. u32 cs;
  159. if (is_on == BITBANG_CS_INACTIVE) {
  160. /* Deselect the slave on the SPI bus */
  161. xspi->write_fn(xspi->cs_inactive, xspi->regs + XSPI_SSR_OFFSET);
  162. return;
  163. }
  164. /* Set the SPI clock phase and polarity */
  165. cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) & ~XSPI_CR_MODE_MASK;
  166. if (spi->mode & SPI_CPHA)
  167. cr |= XSPI_CR_CPHA;
  168. if (spi->mode & SPI_CPOL)
  169. cr |= XSPI_CR_CPOL;
  170. if (spi->mode & SPI_LSB_FIRST)
  171. cr |= XSPI_CR_LSB_FIRST;
  172. if (spi->mode & SPI_LOOP)
  173. cr |= XSPI_CR_LOOP;
  174. xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
  175. /* We do not check spi->max_speed_hz here as the SPI clock
  176. * frequency is not software programmable (the IP block design
  177. * parameter)
  178. */
  179. cs = xspi->cs_inactive;
  180. cs ^= BIT(spi->chip_select);
  181. /* Activate the chip select */
  182. xspi->write_fn(cs, xspi->regs + XSPI_SSR_OFFSET);
  183. }
  184. /* spi_bitbang requires custom setup_transfer() to be defined if there is a
  185. * custom txrx_bufs().
  186. */
  187. static int xilinx_spi_setup_transfer(struct spi_device *spi,
  188. struct spi_transfer *t)
  189. {
  190. struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
  191. if (spi->mode & SPI_CS_HIGH)
  192. xspi->cs_inactive &= ~BIT(spi->chip_select);
  193. else
  194. xspi->cs_inactive |= BIT(spi->chip_select);
  195. return 0;
  196. }
  197. static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
  198. {
  199. struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
  200. int remaining_words; /* the number of words left to transfer */
  201. bool use_irq = false;
  202. u16 cr = 0;
  203. /* We get here with transmitter inhibited */
  204. xspi->tx_ptr = t->tx_buf;
  205. xspi->rx_ptr = t->rx_buf;
  206. remaining_words = t->len / xspi->bytes_per_word;
  207. if (xspi->irq >= 0 && remaining_words > xspi->buffer_size) {
  208. u32 isr;
  209. use_irq = true;
  210. /* Inhibit irq to avoid spurious irqs on tx_empty*/
  211. cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
  212. xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
  213. xspi->regs + XSPI_CR_OFFSET);
  214. /* ACK old irqs (if any) */
  215. isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET);
  216. if (isr)
  217. xspi->write_fn(isr,
  218. xspi->regs + XIPIF_V123B_IISR_OFFSET);
  219. /* Enable the global IPIF interrupt */
  220. xspi->write_fn(XIPIF_V123B_GINTR_ENABLE,
  221. xspi->regs + XIPIF_V123B_DGIER_OFFSET);
  222. reinit_completion(&xspi->done);
  223. }
  224. while (remaining_words) {
  225. int n_words, tx_words, rx_words;
  226. u32 sr;
  227. int stalled;
  228. n_words = min(remaining_words, xspi->buffer_size);
  229. tx_words = n_words;
  230. while (tx_words--)
  231. xilinx_spi_tx(xspi);
  232. /* Start the transfer by not inhibiting the transmitter any
  233. * longer
  234. */
  235. if (use_irq) {
  236. xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
  237. wait_for_completion(&xspi->done);
  238. /* A transmit has just completed. Process received data
  239. * and check for more data to transmit. Always inhibit
  240. * the transmitter while the Isr refills the transmit
  241. * register/FIFO, or make sure it is stopped if we're
  242. * done.
  243. */
  244. xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
  245. xspi->regs + XSPI_CR_OFFSET);
  246. sr = XSPI_SR_TX_EMPTY_MASK;
  247. } else
  248. sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
  249. /* Read out all the data from the Rx FIFO */
  250. rx_words = n_words;
  251. stalled = 10;
  252. while (rx_words) {
  253. if (rx_words == n_words && !(stalled--) &&
  254. !(sr & XSPI_SR_TX_EMPTY_MASK) &&
  255. (sr & XSPI_SR_RX_EMPTY_MASK)) {
  256. dev_err(&spi->dev,
  257. "Detected stall. Check C_SPI_MODE and C_SPI_MEMORY\n");
  258. xspi_init_hw(xspi);
  259. return -EIO;
  260. }
  261. if ((sr & XSPI_SR_TX_EMPTY_MASK) && (rx_words > 1)) {
  262. xilinx_spi_rx(xspi);
  263. rx_words--;
  264. continue;
  265. }
  266. sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
  267. if (!(sr & XSPI_SR_RX_EMPTY_MASK)) {
  268. xilinx_spi_rx(xspi);
  269. rx_words--;
  270. }
  271. }
  272. remaining_words -= n_words;
  273. }
  274. if (use_irq) {
  275. xspi->write_fn(0, xspi->regs + XIPIF_V123B_DGIER_OFFSET);
  276. xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
  277. }
  278. return t->len;
  279. }
  280. /* This driver supports single master mode only. Hence Tx FIFO Empty
  281. * is the only interrupt we care about.
  282. * Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode
  283. * Fault are not to happen.
  284. */
  285. static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
  286. {
  287. struct xilinx_spi *xspi = dev_id;
  288. u32 ipif_isr;
  289. /* Get the IPIF interrupts, and clear them immediately */
  290. ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET);
  291. xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET);
  292. if (ipif_isr & XSPI_INTR_TX_EMPTY) { /* Transmission completed */
  293. complete(&xspi->done);
  294. return IRQ_HANDLED;
  295. }
  296. return IRQ_NONE;
  297. }
  298. static int xilinx_spi_find_buffer_size(struct xilinx_spi *xspi)
  299. {
  300. u8 sr;
  301. int n_words = 0;
  302. /*
  303. * Before the buffer_size detection we reset the core
  304. * to make sure we start with a clean state.
  305. */
  306. xspi->write_fn(XIPIF_V123B_RESET_MASK,
  307. xspi->regs + XIPIF_V123B_RESETR_OFFSET);
  308. /* Fill the Tx FIFO with as many words as possible */
  309. do {
  310. xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
  311. sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
  312. n_words++;
  313. } while (!(sr & XSPI_SR_TX_FULL_MASK));
  314. return n_words;
  315. }
  316. static const struct of_device_id xilinx_spi_of_match[] = {
  317. { .compatible = "xlnx,axi-quad-spi-1.00.a", },
  318. { .compatible = "xlnx,xps-spi-2.00.a", },
  319. { .compatible = "xlnx,xps-spi-2.00.b", },
  320. {}
  321. };
  322. MODULE_DEVICE_TABLE(of, xilinx_spi_of_match);
  323. static int xilinx_spi_probe(struct platform_device *pdev)
  324. {
  325. struct xilinx_spi *xspi;
  326. struct xspi_platform_data *pdata;
  327. struct resource *res;
  328. int ret, num_cs = 0, bits_per_word;
  329. struct spi_master *master;
  330. u32 tmp;
  331. u8 i;
  332. pdata = dev_get_platdata(&pdev->dev);
  333. if (pdata) {
  334. num_cs = pdata->num_chipselect;
  335. bits_per_word = pdata->bits_per_word;
  336. } else {
  337. of_property_read_u32(pdev->dev.of_node, "xlnx,num-ss-bits",
  338. &num_cs);
  339. ret = of_property_read_u32(pdev->dev.of_node,
  340. "xlnx,num-transfer-bits",
  341. &bits_per_word);
  342. if (ret)
  343. bits_per_word = 8;
  344. }
  345. if (!num_cs) {
  346. dev_err(&pdev->dev,
  347. "Missing slave select configuration data\n");
  348. return -EINVAL;
  349. }
  350. if (num_cs > XILINX_SPI_MAX_CS) {
  351. dev_err(&pdev->dev, "Invalid number of spi slaves\n");
  352. return -EINVAL;
  353. }
  354. master = spi_alloc_master(&pdev->dev, sizeof(struct xilinx_spi));
  355. if (!master)
  356. return -ENODEV;
  357. /* the spi->mode bits understood by this driver: */
  358. master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_LOOP |
  359. SPI_CS_HIGH;
  360. xspi = spi_master_get_devdata(master);
  361. xspi->cs_inactive = 0xffffffff;
  362. xspi->bitbang.master = master;
  363. xspi->bitbang.chipselect = xilinx_spi_chipselect;
  364. xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
  365. xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs;
  366. init_completion(&xspi->done);
  367. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  368. xspi->regs = devm_ioremap_resource(&pdev->dev, res);
  369. if (IS_ERR(xspi->regs)) {
  370. ret = PTR_ERR(xspi->regs);
  371. goto put_master;
  372. }
  373. master->bus_num = pdev->id;
  374. master->num_chipselect = num_cs;
  375. master->dev.of_node = pdev->dev.of_node;
  376. /*
  377. * Detect endianess on the IP via loop bit in CR. Detection
  378. * must be done before reset is sent because incorrect reset
  379. * value generates error interrupt.
  380. * Setup little endian helper functions first and try to use them
  381. * and check if bit was correctly setup or not.
  382. */
  383. xspi->read_fn = xspi_read32;
  384. xspi->write_fn = xspi_write32;
  385. xspi->write_fn(XSPI_CR_LOOP, xspi->regs + XSPI_CR_OFFSET);
  386. tmp = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
  387. tmp &= XSPI_CR_LOOP;
  388. if (tmp != XSPI_CR_LOOP) {
  389. xspi->read_fn = xspi_read32_be;
  390. xspi->write_fn = xspi_write32_be;
  391. }
  392. master->bits_per_word_mask = SPI_BPW_MASK(bits_per_word);
  393. xspi->bytes_per_word = bits_per_word / 8;
  394. xspi->buffer_size = xilinx_spi_find_buffer_size(xspi);
  395. xspi->irq = platform_get_irq(pdev, 0);
  396. if (xspi->irq < 0 && xspi->irq != -ENXIO) {
  397. ret = xspi->irq;
  398. goto put_master;
  399. } else if (xspi->irq >= 0) {
  400. /* Register for SPI Interrupt */
  401. ret = devm_request_irq(&pdev->dev, xspi->irq, xilinx_spi_irq, 0,
  402. dev_name(&pdev->dev), xspi);
  403. if (ret)
  404. goto put_master;
  405. }
  406. /* SPI controller initializations */
  407. xspi_init_hw(xspi);
  408. ret = spi_bitbang_start(&xspi->bitbang);
  409. if (ret) {
  410. dev_err(&pdev->dev, "spi_bitbang_start FAILED\n");
  411. goto put_master;
  412. }
  413. dev_info(&pdev->dev, "at %pR, irq=%d\n", res, xspi->irq);
  414. if (pdata) {
  415. for (i = 0; i < pdata->num_devices; i++)
  416. spi_new_device(master, pdata->devices + i);
  417. }
  418. platform_set_drvdata(pdev, master);
  419. return 0;
  420. put_master:
  421. spi_master_put(master);
  422. return ret;
  423. }
  424. static int xilinx_spi_remove(struct platform_device *pdev)
  425. {
  426. struct spi_master *master = platform_get_drvdata(pdev);
  427. struct xilinx_spi *xspi = spi_master_get_devdata(master);
  428. void __iomem *regs_base = xspi->regs;
  429. spi_bitbang_stop(&xspi->bitbang);
  430. /* Disable all the interrupts just in case */
  431. xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET);
  432. /* Disable the global IPIF interrupt */
  433. xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET);
  434. spi_master_put(xspi->bitbang.master);
  435. return 0;
  436. }
  437. /* work with hotplug and coldplug */
  438. MODULE_ALIAS("platform:" XILINX_SPI_NAME);
  439. static struct platform_driver xilinx_spi_driver = {
  440. .probe = xilinx_spi_probe,
  441. .remove = xilinx_spi_remove,
  442. .driver = {
  443. .name = XILINX_SPI_NAME,
  444. .of_match_table = xilinx_spi_of_match,
  445. },
  446. };
  447. module_platform_driver(xilinx_spi_driver);
  448. MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
  449. MODULE_DESCRIPTION("Xilinx SPI driver");
  450. MODULE_LICENSE("GPL");