spi-slave-mt27xx.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. // Copyright (c) 2018 MediaTek Inc.
  3. #include <linux/clk.h>
  4. #include <linux/device.h>
  5. #include <linux/dma-mapping.h>
  6. #include <linux/err.h>
  7. #include <linux/interrupt.h>
  8. #include <linux/module.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/pm_runtime.h>
  11. #include <linux/spi/spi.h>
  12. #define SPIS_IRQ_EN_REG 0x0
  13. #define SPIS_IRQ_CLR_REG 0x4
  14. #define SPIS_IRQ_ST_REG 0x8
  15. #define SPIS_IRQ_MASK_REG 0xc
  16. #define SPIS_CFG_REG 0x10
  17. #define SPIS_RX_DATA_REG 0x14
  18. #define SPIS_TX_DATA_REG 0x18
  19. #define SPIS_RX_DST_REG 0x1c
  20. #define SPIS_TX_SRC_REG 0x20
  21. #define SPIS_DMA_CFG_REG 0x30
  22. #define SPIS_SOFT_RST_REG 0x40
  23. /* SPIS_IRQ_EN_REG */
  24. #define DMA_DONE_EN BIT(7)
  25. #define DATA_DONE_EN BIT(2)
  26. #define RSTA_DONE_EN BIT(1)
  27. #define CMD_INVALID_EN BIT(0)
  28. /* SPIS_IRQ_ST_REG */
  29. #define DMA_DONE_ST BIT(7)
  30. #define DATA_DONE_ST BIT(2)
  31. #define RSTA_DONE_ST BIT(1)
  32. #define CMD_INVALID_ST BIT(0)
  33. /* SPIS_IRQ_MASK_REG */
  34. #define DMA_DONE_MASK BIT(7)
  35. #define DATA_DONE_MASK BIT(2)
  36. #define RSTA_DONE_MASK BIT(1)
  37. #define CMD_INVALID_MASK BIT(0)
  38. /* SPIS_CFG_REG */
  39. #define SPIS_TX_ENDIAN BIT(7)
  40. #define SPIS_RX_ENDIAN BIT(6)
  41. #define SPIS_TXMSBF BIT(5)
  42. #define SPIS_RXMSBF BIT(4)
  43. #define SPIS_CPHA BIT(3)
  44. #define SPIS_CPOL BIT(2)
  45. #define SPIS_TX_EN BIT(1)
  46. #define SPIS_RX_EN BIT(0)
  47. /* SPIS_DMA_CFG_REG */
  48. #define TX_DMA_TRIG_EN BIT(31)
  49. #define TX_DMA_EN BIT(30)
  50. #define RX_DMA_EN BIT(29)
  51. #define TX_DMA_LEN 0xfffff
  52. /* SPIS_SOFT_RST_REG */
  53. #define SPIS_DMA_ADDR_EN BIT(1)
  54. #define SPIS_SOFT_RST BIT(0)
  55. #define MTK_SPI_SLAVE_MAX_FIFO_SIZE 512U
  56. struct mtk_spi_slave {
  57. struct device *dev;
  58. void __iomem *base;
  59. struct clk *spi_clk;
  60. struct completion xfer_done;
  61. struct spi_transfer *cur_transfer;
  62. bool slave_aborted;
  63. };
  64. static const struct of_device_id mtk_spi_slave_of_match[] = {
  65. { .compatible = "mediatek,mt2712-spi-slave", },
  66. {}
  67. };
  68. MODULE_DEVICE_TABLE(of, mtk_spi_slave_of_match);
  69. static void mtk_spi_slave_disable_dma(struct mtk_spi_slave *mdata)
  70. {
  71. u32 reg_val;
  72. reg_val = readl(mdata->base + SPIS_DMA_CFG_REG);
  73. reg_val &= ~RX_DMA_EN;
  74. reg_val &= ~TX_DMA_EN;
  75. writel(reg_val, mdata->base + SPIS_DMA_CFG_REG);
  76. }
  77. static void mtk_spi_slave_disable_xfer(struct mtk_spi_slave *mdata)
  78. {
  79. u32 reg_val;
  80. reg_val = readl(mdata->base + SPIS_CFG_REG);
  81. reg_val &= ~SPIS_TX_EN;
  82. reg_val &= ~SPIS_RX_EN;
  83. writel(reg_val, mdata->base + SPIS_CFG_REG);
  84. }
  85. static int mtk_spi_slave_wait_for_completion(struct mtk_spi_slave *mdata)
  86. {
  87. if (wait_for_completion_interruptible(&mdata->xfer_done) ||
  88. mdata->slave_aborted) {
  89. dev_err(mdata->dev, "interrupted\n");
  90. return -EINTR;
  91. }
  92. return 0;
  93. }
  94. static int mtk_spi_slave_prepare_message(struct spi_controller *ctlr,
  95. struct spi_message *msg)
  96. {
  97. struct mtk_spi_slave *mdata = spi_controller_get_devdata(ctlr);
  98. struct spi_device *spi = msg->spi;
  99. bool cpha, cpol;
  100. u32 reg_val;
  101. cpha = spi->mode & SPI_CPHA ? 1 : 0;
  102. cpol = spi->mode & SPI_CPOL ? 1 : 0;
  103. reg_val = readl(mdata->base + SPIS_CFG_REG);
  104. if (cpha)
  105. reg_val |= SPIS_CPHA;
  106. else
  107. reg_val &= ~SPIS_CPHA;
  108. if (cpol)
  109. reg_val |= SPIS_CPOL;
  110. else
  111. reg_val &= ~SPIS_CPOL;
  112. if (spi->mode & SPI_LSB_FIRST)
  113. reg_val &= ~(SPIS_TXMSBF | SPIS_RXMSBF);
  114. else
  115. reg_val |= SPIS_TXMSBF | SPIS_RXMSBF;
  116. reg_val &= ~SPIS_TX_ENDIAN;
  117. reg_val &= ~SPIS_RX_ENDIAN;
  118. writel(reg_val, mdata->base + SPIS_CFG_REG);
  119. return 0;
  120. }
  121. static int mtk_spi_slave_fifo_transfer(struct spi_controller *ctlr,
  122. struct spi_device *spi,
  123. struct spi_transfer *xfer)
  124. {
  125. struct mtk_spi_slave *mdata = spi_controller_get_devdata(ctlr);
  126. int reg_val, cnt, remainder, ret;
  127. writel(SPIS_SOFT_RST, mdata->base + SPIS_SOFT_RST_REG);
  128. reg_val = readl(mdata->base + SPIS_CFG_REG);
  129. if (xfer->rx_buf)
  130. reg_val |= SPIS_RX_EN;
  131. if (xfer->tx_buf)
  132. reg_val |= SPIS_TX_EN;
  133. writel(reg_val, mdata->base + SPIS_CFG_REG);
  134. cnt = xfer->len / 4;
  135. if (xfer->tx_buf)
  136. iowrite32_rep(mdata->base + SPIS_TX_DATA_REG,
  137. xfer->tx_buf, cnt);
  138. remainder = xfer->len % 4;
  139. if (xfer->tx_buf && remainder > 0) {
  140. reg_val = 0;
  141. memcpy(&reg_val, xfer->tx_buf + cnt * 4, remainder);
  142. writel(reg_val, mdata->base + SPIS_TX_DATA_REG);
  143. }
  144. ret = mtk_spi_slave_wait_for_completion(mdata);
  145. if (ret) {
  146. mtk_spi_slave_disable_xfer(mdata);
  147. writel(SPIS_SOFT_RST, mdata->base + SPIS_SOFT_RST_REG);
  148. }
  149. return ret;
  150. }
  151. static int mtk_spi_slave_dma_transfer(struct spi_controller *ctlr,
  152. struct spi_device *spi,
  153. struct spi_transfer *xfer)
  154. {
  155. struct mtk_spi_slave *mdata = spi_controller_get_devdata(ctlr);
  156. struct device *dev = mdata->dev;
  157. int reg_val, ret;
  158. writel(SPIS_SOFT_RST, mdata->base + SPIS_SOFT_RST_REG);
  159. if (xfer->tx_buf) {
  160. /* tx_buf is a const void* where we need a void * for
  161. * the dma mapping
  162. */
  163. void *nonconst_tx = (void *)xfer->tx_buf;
  164. xfer->tx_dma = dma_map_single(dev, nonconst_tx,
  165. xfer->len, DMA_TO_DEVICE);
  166. if (dma_mapping_error(dev, xfer->tx_dma)) {
  167. ret = -ENOMEM;
  168. goto disable_transfer;
  169. }
  170. }
  171. if (xfer->rx_buf) {
  172. xfer->rx_dma = dma_map_single(dev, xfer->rx_buf,
  173. xfer->len, DMA_FROM_DEVICE);
  174. if (dma_mapping_error(dev, xfer->rx_dma)) {
  175. ret = -ENOMEM;
  176. goto unmap_txdma;
  177. }
  178. }
  179. writel(xfer->tx_dma, mdata->base + SPIS_TX_SRC_REG);
  180. writel(xfer->rx_dma, mdata->base + SPIS_RX_DST_REG);
  181. writel(SPIS_DMA_ADDR_EN, mdata->base + SPIS_SOFT_RST_REG);
  182. /* enable config reg tx rx_enable */
  183. reg_val = readl(mdata->base + SPIS_CFG_REG);
  184. if (xfer->tx_buf)
  185. reg_val |= SPIS_TX_EN;
  186. if (xfer->rx_buf)
  187. reg_val |= SPIS_RX_EN;
  188. writel(reg_val, mdata->base + SPIS_CFG_REG);
  189. /* config dma */
  190. reg_val = 0;
  191. reg_val |= (xfer->len - 1) & TX_DMA_LEN;
  192. writel(reg_val, mdata->base + SPIS_DMA_CFG_REG);
  193. reg_val = readl(mdata->base + SPIS_DMA_CFG_REG);
  194. if (xfer->tx_buf)
  195. reg_val |= TX_DMA_EN;
  196. if (xfer->rx_buf)
  197. reg_val |= RX_DMA_EN;
  198. reg_val |= TX_DMA_TRIG_EN;
  199. writel(reg_val, mdata->base + SPIS_DMA_CFG_REG);
  200. ret = mtk_spi_slave_wait_for_completion(mdata);
  201. if (ret)
  202. goto unmap_rxdma;
  203. return 0;
  204. unmap_rxdma:
  205. if (xfer->rx_buf)
  206. dma_unmap_single(dev, xfer->rx_dma,
  207. xfer->len, DMA_FROM_DEVICE);
  208. unmap_txdma:
  209. if (xfer->tx_buf)
  210. dma_unmap_single(dev, xfer->tx_dma,
  211. xfer->len, DMA_TO_DEVICE);
  212. disable_transfer:
  213. mtk_spi_slave_disable_dma(mdata);
  214. mtk_spi_slave_disable_xfer(mdata);
  215. writel(SPIS_SOFT_RST, mdata->base + SPIS_SOFT_RST_REG);
  216. return ret;
  217. }
  218. static int mtk_spi_slave_transfer_one(struct spi_controller *ctlr,
  219. struct spi_device *spi,
  220. struct spi_transfer *xfer)
  221. {
  222. struct mtk_spi_slave *mdata = spi_controller_get_devdata(ctlr);
  223. reinit_completion(&mdata->xfer_done);
  224. mdata->slave_aborted = false;
  225. mdata->cur_transfer = xfer;
  226. if (xfer->len > MTK_SPI_SLAVE_MAX_FIFO_SIZE)
  227. return mtk_spi_slave_dma_transfer(ctlr, spi, xfer);
  228. else
  229. return mtk_spi_slave_fifo_transfer(ctlr, spi, xfer);
  230. }
  231. static int mtk_spi_slave_setup(struct spi_device *spi)
  232. {
  233. struct mtk_spi_slave *mdata = spi_controller_get_devdata(spi->master);
  234. u32 reg_val;
  235. reg_val = DMA_DONE_EN | DATA_DONE_EN |
  236. RSTA_DONE_EN | CMD_INVALID_EN;
  237. writel(reg_val, mdata->base + SPIS_IRQ_EN_REG);
  238. reg_val = DMA_DONE_MASK | DATA_DONE_MASK |
  239. RSTA_DONE_MASK | CMD_INVALID_MASK;
  240. writel(reg_val, mdata->base + SPIS_IRQ_MASK_REG);
  241. mtk_spi_slave_disable_dma(mdata);
  242. mtk_spi_slave_disable_xfer(mdata);
  243. return 0;
  244. }
  245. static int mtk_slave_abort(struct spi_controller *ctlr)
  246. {
  247. struct mtk_spi_slave *mdata = spi_controller_get_devdata(ctlr);
  248. mdata->slave_aborted = true;
  249. complete(&mdata->xfer_done);
  250. return 0;
  251. }
  252. static irqreturn_t mtk_spi_slave_interrupt(int irq, void *dev_id)
  253. {
  254. struct spi_controller *ctlr = dev_id;
  255. struct mtk_spi_slave *mdata = spi_controller_get_devdata(ctlr);
  256. struct spi_transfer *trans = mdata->cur_transfer;
  257. u32 int_status, reg_val, cnt, remainder;
  258. int_status = readl(mdata->base + SPIS_IRQ_ST_REG);
  259. writel(int_status, mdata->base + SPIS_IRQ_CLR_REG);
  260. if (!trans)
  261. return IRQ_NONE;
  262. if ((int_status & DMA_DONE_ST) &&
  263. ((int_status & DATA_DONE_ST) ||
  264. (int_status & RSTA_DONE_ST))) {
  265. writel(SPIS_SOFT_RST, mdata->base + SPIS_SOFT_RST_REG);
  266. if (trans->tx_buf)
  267. dma_unmap_single(mdata->dev, trans->tx_dma,
  268. trans->len, DMA_TO_DEVICE);
  269. if (trans->rx_buf)
  270. dma_unmap_single(mdata->dev, trans->rx_dma,
  271. trans->len, DMA_FROM_DEVICE);
  272. mtk_spi_slave_disable_dma(mdata);
  273. mtk_spi_slave_disable_xfer(mdata);
  274. }
  275. if ((!(int_status & DMA_DONE_ST)) &&
  276. ((int_status & DATA_DONE_ST) ||
  277. (int_status & RSTA_DONE_ST))) {
  278. cnt = trans->len / 4;
  279. if (trans->rx_buf)
  280. ioread32_rep(mdata->base + SPIS_RX_DATA_REG,
  281. trans->rx_buf, cnt);
  282. remainder = trans->len % 4;
  283. if (trans->rx_buf && remainder > 0) {
  284. reg_val = readl(mdata->base + SPIS_RX_DATA_REG);
  285. memcpy(trans->rx_buf + (cnt * 4),
  286. &reg_val, remainder);
  287. }
  288. mtk_spi_slave_disable_xfer(mdata);
  289. }
  290. if (int_status & CMD_INVALID_ST) {
  291. dev_warn(&ctlr->dev, "cmd invalid\n");
  292. return IRQ_NONE;
  293. }
  294. mdata->cur_transfer = NULL;
  295. complete(&mdata->xfer_done);
  296. return IRQ_HANDLED;
  297. }
  298. static int mtk_spi_slave_probe(struct platform_device *pdev)
  299. {
  300. struct spi_controller *ctlr;
  301. struct mtk_spi_slave *mdata;
  302. int irq, ret;
  303. ctlr = spi_alloc_slave(&pdev->dev, sizeof(*mdata));
  304. if (!ctlr) {
  305. dev_err(&pdev->dev, "failed to alloc spi slave\n");
  306. return -ENOMEM;
  307. }
  308. ctlr->auto_runtime_pm = true;
  309. ctlr->dev.of_node = pdev->dev.of_node;
  310. ctlr->mode_bits = SPI_CPOL | SPI_CPHA;
  311. ctlr->mode_bits |= SPI_LSB_FIRST;
  312. ctlr->prepare_message = mtk_spi_slave_prepare_message;
  313. ctlr->transfer_one = mtk_spi_slave_transfer_one;
  314. ctlr->setup = mtk_spi_slave_setup;
  315. ctlr->slave_abort = mtk_slave_abort;
  316. mdata = spi_controller_get_devdata(ctlr);
  317. platform_set_drvdata(pdev, ctlr);
  318. init_completion(&mdata->xfer_done);
  319. mdata->dev = &pdev->dev;
  320. mdata->base = devm_platform_ioremap_resource(pdev, 0);
  321. if (IS_ERR(mdata->base)) {
  322. ret = PTR_ERR(mdata->base);
  323. goto err_put_ctlr;
  324. }
  325. irq = platform_get_irq(pdev, 0);
  326. if (irq < 0) {
  327. ret = irq;
  328. goto err_put_ctlr;
  329. }
  330. ret = devm_request_irq(&pdev->dev, irq, mtk_spi_slave_interrupt,
  331. IRQF_TRIGGER_NONE, dev_name(&pdev->dev), ctlr);
  332. if (ret) {
  333. dev_err(&pdev->dev, "failed to register irq (%d)\n", ret);
  334. goto err_put_ctlr;
  335. }
  336. mdata->spi_clk = devm_clk_get(&pdev->dev, "spi");
  337. if (IS_ERR(mdata->spi_clk)) {
  338. ret = PTR_ERR(mdata->spi_clk);
  339. dev_err(&pdev->dev, "failed to get spi-clk: %d\n", ret);
  340. goto err_put_ctlr;
  341. }
  342. ret = clk_prepare_enable(mdata->spi_clk);
  343. if (ret < 0) {
  344. dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret);
  345. goto err_put_ctlr;
  346. }
  347. pm_runtime_enable(&pdev->dev);
  348. ret = devm_spi_register_controller(&pdev->dev, ctlr);
  349. if (ret) {
  350. dev_err(&pdev->dev,
  351. "failed to register slave controller(%d)\n", ret);
  352. clk_disable_unprepare(mdata->spi_clk);
  353. goto err_disable_runtime_pm;
  354. }
  355. clk_disable_unprepare(mdata->spi_clk);
  356. return 0;
  357. err_disable_runtime_pm:
  358. pm_runtime_disable(&pdev->dev);
  359. err_put_ctlr:
  360. spi_controller_put(ctlr);
  361. return ret;
  362. }
  363. static int mtk_spi_slave_remove(struct platform_device *pdev)
  364. {
  365. pm_runtime_disable(&pdev->dev);
  366. return 0;
  367. }
  368. #ifdef CONFIG_PM_SLEEP
  369. static int mtk_spi_slave_suspend(struct device *dev)
  370. {
  371. struct spi_controller *ctlr = dev_get_drvdata(dev);
  372. struct mtk_spi_slave *mdata = spi_controller_get_devdata(ctlr);
  373. int ret;
  374. ret = spi_controller_suspend(ctlr);
  375. if (ret)
  376. return ret;
  377. if (!pm_runtime_suspended(dev))
  378. clk_disable_unprepare(mdata->spi_clk);
  379. return ret;
  380. }
  381. static int mtk_spi_slave_resume(struct device *dev)
  382. {
  383. struct spi_controller *ctlr = dev_get_drvdata(dev);
  384. struct mtk_spi_slave *mdata = spi_controller_get_devdata(ctlr);
  385. int ret;
  386. if (!pm_runtime_suspended(dev)) {
  387. ret = clk_prepare_enable(mdata->spi_clk);
  388. if (ret < 0) {
  389. dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
  390. return ret;
  391. }
  392. }
  393. ret = spi_controller_resume(ctlr);
  394. if (ret < 0)
  395. clk_disable_unprepare(mdata->spi_clk);
  396. return ret;
  397. }
  398. #endif /* CONFIG_PM_SLEEP */
  399. #ifdef CONFIG_PM
  400. static int mtk_spi_slave_runtime_suspend(struct device *dev)
  401. {
  402. struct spi_controller *ctlr = dev_get_drvdata(dev);
  403. struct mtk_spi_slave *mdata = spi_controller_get_devdata(ctlr);
  404. clk_disable_unprepare(mdata->spi_clk);
  405. return 0;
  406. }
  407. static int mtk_spi_slave_runtime_resume(struct device *dev)
  408. {
  409. struct spi_controller *ctlr = dev_get_drvdata(dev);
  410. struct mtk_spi_slave *mdata = spi_controller_get_devdata(ctlr);
  411. int ret;
  412. ret = clk_prepare_enable(mdata->spi_clk);
  413. if (ret < 0) {
  414. dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
  415. return ret;
  416. }
  417. return 0;
  418. }
  419. #endif /* CONFIG_PM */
  420. static const struct dev_pm_ops mtk_spi_slave_pm = {
  421. SET_SYSTEM_SLEEP_PM_OPS(mtk_spi_slave_suspend, mtk_spi_slave_resume)
  422. SET_RUNTIME_PM_OPS(mtk_spi_slave_runtime_suspend,
  423. mtk_spi_slave_runtime_resume, NULL)
  424. };
  425. static struct platform_driver mtk_spi_slave_driver = {
  426. .driver = {
  427. .name = "mtk-spi-slave",
  428. .pm = &mtk_spi_slave_pm,
  429. .of_match_table = mtk_spi_slave_of_match,
  430. },
  431. .probe = mtk_spi_slave_probe,
  432. .remove = mtk_spi_slave_remove,
  433. };
  434. module_platform_driver(mtk_spi_slave_driver);
  435. MODULE_DESCRIPTION("MTK SPI Slave Controller driver");
  436. MODULE_AUTHOR("Leilk Liu <leilk.liu@mediatek.com>");
  437. MODULE_LICENSE("GPL v2");
  438. MODULE_ALIAS("platform:mtk-spi-slave");