spi-sirf.c 35 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * SPI bus driver for CSR SiRFprimaII
  4. *
  5. * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
  6. */
  7. #include <linux/module.h>
  8. #include <linux/kernel.h>
  9. #include <linux/slab.h>
  10. #include <linux/clk.h>
  11. #include <linux/completion.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/io.h>
  14. #include <linux/of.h>
  15. #include <linux/bitops.h>
  16. #include <linux/err.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/of_gpio.h>
  19. #include <linux/spi/spi.h>
  20. #include <linux/spi/spi_bitbang.h>
  21. #include <linux/dmaengine.h>
  22. #include <linux/dma-direction.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/reset.h>
  25. #define DRIVER_NAME "sirfsoc_spi"
  26. /* SPI CTRL register defines */
  27. #define SIRFSOC_SPI_SLV_MODE BIT(16)
  28. #define SIRFSOC_SPI_CMD_MODE BIT(17)
  29. #define SIRFSOC_SPI_CS_IO_OUT BIT(18)
  30. #define SIRFSOC_SPI_CS_IO_MODE BIT(19)
  31. #define SIRFSOC_SPI_CLK_IDLE_STAT BIT(20)
  32. #define SIRFSOC_SPI_CS_IDLE_STAT BIT(21)
  33. #define SIRFSOC_SPI_TRAN_MSB BIT(22)
  34. #define SIRFSOC_SPI_DRV_POS_EDGE BIT(23)
  35. #define SIRFSOC_SPI_CS_HOLD_TIME BIT(24)
  36. #define SIRFSOC_SPI_CLK_SAMPLE_MODE BIT(25)
  37. #define SIRFSOC_SPI_TRAN_DAT_FORMAT_8 (0 << 26)
  38. #define SIRFSOC_SPI_TRAN_DAT_FORMAT_12 (1 << 26)
  39. #define SIRFSOC_SPI_TRAN_DAT_FORMAT_16 (2 << 26)
  40. #define SIRFSOC_SPI_TRAN_DAT_FORMAT_32 (3 << 26)
  41. #define SIRFSOC_SPI_CMD_BYTE_NUM(x) ((x & 3) << 28)
  42. #define SIRFSOC_SPI_ENA_AUTO_CLR BIT(30)
  43. #define SIRFSOC_SPI_MUL_DAT_MODE BIT(31)
  44. /* Interrupt Enable */
  45. #define SIRFSOC_SPI_RX_DONE_INT_EN BIT(0)
  46. #define SIRFSOC_SPI_TX_DONE_INT_EN BIT(1)
  47. #define SIRFSOC_SPI_RX_OFLOW_INT_EN BIT(2)
  48. #define SIRFSOC_SPI_TX_UFLOW_INT_EN BIT(3)
  49. #define SIRFSOC_SPI_RX_IO_DMA_INT_EN BIT(4)
  50. #define SIRFSOC_SPI_TX_IO_DMA_INT_EN BIT(5)
  51. #define SIRFSOC_SPI_RXFIFO_FULL_INT_EN BIT(6)
  52. #define SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN BIT(7)
  53. #define SIRFSOC_SPI_RXFIFO_THD_INT_EN BIT(8)
  54. #define SIRFSOC_SPI_TXFIFO_THD_INT_EN BIT(9)
  55. #define SIRFSOC_SPI_FRM_END_INT_EN BIT(10)
  56. /* Interrupt status */
  57. #define SIRFSOC_SPI_RX_DONE BIT(0)
  58. #define SIRFSOC_SPI_TX_DONE BIT(1)
  59. #define SIRFSOC_SPI_RX_OFLOW BIT(2)
  60. #define SIRFSOC_SPI_TX_UFLOW BIT(3)
  61. #define SIRFSOC_SPI_RX_IO_DMA BIT(4)
  62. #define SIRFSOC_SPI_RX_FIFO_FULL BIT(6)
  63. #define SIRFSOC_SPI_TXFIFO_EMPTY BIT(7)
  64. #define SIRFSOC_SPI_RXFIFO_THD_REACH BIT(8)
  65. #define SIRFSOC_SPI_TXFIFO_THD_REACH BIT(9)
  66. #define SIRFSOC_SPI_FRM_END BIT(10)
  67. /* TX RX enable */
  68. #define SIRFSOC_SPI_RX_EN BIT(0)
  69. #define SIRFSOC_SPI_TX_EN BIT(1)
  70. #define SIRFSOC_SPI_CMD_TX_EN BIT(2)
  71. #define SIRFSOC_SPI_IO_MODE_SEL BIT(0)
  72. #define SIRFSOC_SPI_RX_DMA_FLUSH BIT(2)
  73. /* FIFO OPs */
  74. #define SIRFSOC_SPI_FIFO_RESET BIT(0)
  75. #define SIRFSOC_SPI_FIFO_START BIT(1)
  76. /* FIFO CTRL */
  77. #define SIRFSOC_SPI_FIFO_WIDTH_BYTE (0 << 0)
  78. #define SIRFSOC_SPI_FIFO_WIDTH_WORD (1 << 0)
  79. #define SIRFSOC_SPI_FIFO_WIDTH_DWORD (2 << 0)
  80. /* USP related */
  81. #define SIRFSOC_USP_SYNC_MODE BIT(0)
  82. #define SIRFSOC_USP_SLV_MODE BIT(1)
  83. #define SIRFSOC_USP_LSB BIT(4)
  84. #define SIRFSOC_USP_EN BIT(5)
  85. #define SIRFSOC_USP_RXD_FALLING_EDGE BIT(6)
  86. #define SIRFSOC_USP_TXD_FALLING_EDGE BIT(7)
  87. #define SIRFSOC_USP_CS_HIGH_VALID BIT(9)
  88. #define SIRFSOC_USP_SCLK_IDLE_STAT BIT(11)
  89. #define SIRFSOC_USP_TFS_IO_MODE BIT(14)
  90. #define SIRFSOC_USP_TFS_IO_INPUT BIT(19)
  91. #define SIRFSOC_USP_RXD_DELAY_LEN_MASK 0xFF
  92. #define SIRFSOC_USP_TXD_DELAY_LEN_MASK 0xFF
  93. #define SIRFSOC_USP_RXD_DELAY_OFFSET 0
  94. #define SIRFSOC_USP_TXD_DELAY_OFFSET 8
  95. #define SIRFSOC_USP_RXD_DELAY_LEN 1
  96. #define SIRFSOC_USP_TXD_DELAY_LEN 1
  97. #define SIRFSOC_USP_CLK_DIVISOR_OFFSET 21
  98. #define SIRFSOC_USP_CLK_DIVISOR_MASK 0x3FF
  99. #define SIRFSOC_USP_CLK_10_11_MASK 0x3
  100. #define SIRFSOC_USP_CLK_10_11_OFFSET 30
  101. #define SIRFSOC_USP_CLK_12_15_MASK 0xF
  102. #define SIRFSOC_USP_CLK_12_15_OFFSET 24
  103. #define SIRFSOC_USP_TX_DATA_OFFSET 0
  104. #define SIRFSOC_USP_TX_SYNC_OFFSET 8
  105. #define SIRFSOC_USP_TX_FRAME_OFFSET 16
  106. #define SIRFSOC_USP_TX_SHIFTER_OFFSET 24
  107. #define SIRFSOC_USP_TX_DATA_MASK 0xFF
  108. #define SIRFSOC_USP_TX_SYNC_MASK 0xFF
  109. #define SIRFSOC_USP_TX_FRAME_MASK 0xFF
  110. #define SIRFSOC_USP_TX_SHIFTER_MASK 0x1F
  111. #define SIRFSOC_USP_RX_DATA_OFFSET 0
  112. #define SIRFSOC_USP_RX_FRAME_OFFSET 8
  113. #define SIRFSOC_USP_RX_SHIFTER_OFFSET 16
  114. #define SIRFSOC_USP_RX_DATA_MASK 0xFF
  115. #define SIRFSOC_USP_RX_FRAME_MASK 0xFF
  116. #define SIRFSOC_USP_RX_SHIFTER_MASK 0x1F
  117. #define SIRFSOC_USP_CS_HIGH_VALUE BIT(1)
  118. #define SIRFSOC_SPI_FIFO_SC_OFFSET 0
  119. #define SIRFSOC_SPI_FIFO_LC_OFFSET 10
  120. #define SIRFSOC_SPI_FIFO_HC_OFFSET 20
  121. #define SIRFSOC_SPI_FIFO_FULL_MASK(s) (1 << ((s)->fifo_full_offset))
  122. #define SIRFSOC_SPI_FIFO_EMPTY_MASK(s) (1 << ((s)->fifo_full_offset + 1))
  123. #define SIRFSOC_SPI_FIFO_THD_MASK(s) ((s)->fifo_size - 1)
  124. #define SIRFSOC_SPI_FIFO_THD_OFFSET 2
  125. #define SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(s, val) \
  126. ((val) & (s)->fifo_level_chk_mask)
  127. enum sirf_spi_type {
  128. SIRF_REAL_SPI,
  129. SIRF_USP_SPI_P2,
  130. SIRF_USP_SPI_A7,
  131. };
  132. /*
  133. * only if the rx/tx buffer and transfer size are 4-bytes aligned, we use dma
  134. * due to the limitation of dma controller
  135. */
  136. #define ALIGNED(x) (!((u32)x & 0x3))
  137. #define IS_DMA_VALID(x) (x && ALIGNED(x->tx_buf) && ALIGNED(x->rx_buf) && \
  138. ALIGNED(x->len) && (x->len < 2 * PAGE_SIZE))
  139. #define SIRFSOC_MAX_CMD_BYTES 4
  140. #define SIRFSOC_SPI_DEFAULT_FRQ 1000000
  141. struct sirf_spi_register {
  142. /*SPI and USP-SPI common*/
  143. u32 tx_rx_en;
  144. u32 int_en;
  145. u32 int_st;
  146. u32 tx_dma_io_ctrl;
  147. u32 tx_dma_io_len;
  148. u32 txfifo_ctrl;
  149. u32 txfifo_level_chk;
  150. u32 txfifo_op;
  151. u32 txfifo_st;
  152. u32 txfifo_data;
  153. u32 rx_dma_io_ctrl;
  154. u32 rx_dma_io_len;
  155. u32 rxfifo_ctrl;
  156. u32 rxfifo_level_chk;
  157. u32 rxfifo_op;
  158. u32 rxfifo_st;
  159. u32 rxfifo_data;
  160. /*SPI self*/
  161. u32 spi_ctrl;
  162. u32 spi_cmd;
  163. u32 spi_dummy_delay_ctrl;
  164. /*USP-SPI self*/
  165. u32 usp_mode1;
  166. u32 usp_mode2;
  167. u32 usp_tx_frame_ctrl;
  168. u32 usp_rx_frame_ctrl;
  169. u32 usp_pin_io_data;
  170. u32 usp_risc_dsp_mode;
  171. u32 usp_async_param_reg;
  172. u32 usp_irda_x_mode_div;
  173. u32 usp_sm_cfg;
  174. u32 usp_int_en_clr;
  175. };
  176. static const struct sirf_spi_register real_spi_register = {
  177. .tx_rx_en = 0x8,
  178. .int_en = 0xc,
  179. .int_st = 0x10,
  180. .tx_dma_io_ctrl = 0x100,
  181. .tx_dma_io_len = 0x104,
  182. .txfifo_ctrl = 0x108,
  183. .txfifo_level_chk = 0x10c,
  184. .txfifo_op = 0x110,
  185. .txfifo_st = 0x114,
  186. .txfifo_data = 0x118,
  187. .rx_dma_io_ctrl = 0x120,
  188. .rx_dma_io_len = 0x124,
  189. .rxfifo_ctrl = 0x128,
  190. .rxfifo_level_chk = 0x12c,
  191. .rxfifo_op = 0x130,
  192. .rxfifo_st = 0x134,
  193. .rxfifo_data = 0x138,
  194. .spi_ctrl = 0x0,
  195. .spi_cmd = 0x4,
  196. .spi_dummy_delay_ctrl = 0x144,
  197. };
  198. static const struct sirf_spi_register usp_spi_register = {
  199. .tx_rx_en = 0x10,
  200. .int_en = 0x14,
  201. .int_st = 0x18,
  202. .tx_dma_io_ctrl = 0x100,
  203. .tx_dma_io_len = 0x104,
  204. .txfifo_ctrl = 0x108,
  205. .txfifo_level_chk = 0x10c,
  206. .txfifo_op = 0x110,
  207. .txfifo_st = 0x114,
  208. .txfifo_data = 0x118,
  209. .rx_dma_io_ctrl = 0x120,
  210. .rx_dma_io_len = 0x124,
  211. .rxfifo_ctrl = 0x128,
  212. .rxfifo_level_chk = 0x12c,
  213. .rxfifo_op = 0x130,
  214. .rxfifo_st = 0x134,
  215. .rxfifo_data = 0x138,
  216. .usp_mode1 = 0x0,
  217. .usp_mode2 = 0x4,
  218. .usp_tx_frame_ctrl = 0x8,
  219. .usp_rx_frame_ctrl = 0xc,
  220. .usp_pin_io_data = 0x1c,
  221. .usp_risc_dsp_mode = 0x20,
  222. .usp_async_param_reg = 0x24,
  223. .usp_irda_x_mode_div = 0x28,
  224. .usp_sm_cfg = 0x2c,
  225. .usp_int_en_clr = 0x140,
  226. };
  227. struct sirfsoc_spi {
  228. struct spi_bitbang bitbang;
  229. struct completion rx_done;
  230. struct completion tx_done;
  231. void __iomem *base;
  232. u32 ctrl_freq; /* SPI controller clock speed */
  233. struct clk *clk;
  234. /* rx & tx bufs from the spi_transfer */
  235. const void *tx;
  236. void *rx;
  237. /* place received word into rx buffer */
  238. void (*rx_word) (struct sirfsoc_spi *);
  239. /* get word from tx buffer for sending */
  240. void (*tx_word) (struct sirfsoc_spi *);
  241. /* number of words left to be tranmitted/received */
  242. unsigned int left_tx_word;
  243. unsigned int left_rx_word;
  244. /* rx & tx DMA channels */
  245. struct dma_chan *rx_chan;
  246. struct dma_chan *tx_chan;
  247. dma_addr_t src_start;
  248. dma_addr_t dst_start;
  249. int word_width; /* in bytes */
  250. /*
  251. * if tx size is not more than 4 and rx size is NULL, use
  252. * command model
  253. */
  254. bool tx_by_cmd;
  255. bool hw_cs;
  256. enum sirf_spi_type type;
  257. const struct sirf_spi_register *regs;
  258. unsigned int fifo_size;
  259. /* fifo empty offset is (fifo full offset + 1)*/
  260. unsigned int fifo_full_offset;
  261. /* fifo_level_chk_mask is (fifo_size/4 - 1) */
  262. unsigned int fifo_level_chk_mask;
  263. unsigned int dat_max_frm_len;
  264. };
  265. struct sirf_spi_comp_data {
  266. const struct sirf_spi_register *regs;
  267. enum sirf_spi_type type;
  268. unsigned int dat_max_frm_len;
  269. unsigned int fifo_size;
  270. void (*hwinit)(struct sirfsoc_spi *sspi);
  271. };
  272. static void sirfsoc_usp_hwinit(struct sirfsoc_spi *sspi)
  273. {
  274. /* reset USP and let USP can operate */
  275. writel(readl(sspi->base + sspi->regs->usp_mode1) &
  276. ~SIRFSOC_USP_EN, sspi->base + sspi->regs->usp_mode1);
  277. writel(readl(sspi->base + sspi->regs->usp_mode1) |
  278. SIRFSOC_USP_EN, sspi->base + sspi->regs->usp_mode1);
  279. }
  280. static void spi_sirfsoc_rx_word_u8(struct sirfsoc_spi *sspi)
  281. {
  282. u32 data;
  283. u8 *rx = sspi->rx;
  284. data = readl(sspi->base + sspi->regs->rxfifo_data);
  285. if (rx) {
  286. *rx++ = (u8) data;
  287. sspi->rx = rx;
  288. }
  289. sspi->left_rx_word--;
  290. }
  291. static void spi_sirfsoc_tx_word_u8(struct sirfsoc_spi *sspi)
  292. {
  293. u32 data = 0;
  294. const u8 *tx = sspi->tx;
  295. if (tx) {
  296. data = *tx++;
  297. sspi->tx = tx;
  298. }
  299. writel(data, sspi->base + sspi->regs->txfifo_data);
  300. sspi->left_tx_word--;
  301. }
  302. static void spi_sirfsoc_rx_word_u16(struct sirfsoc_spi *sspi)
  303. {
  304. u32 data;
  305. u16 *rx = sspi->rx;
  306. data = readl(sspi->base + sspi->regs->rxfifo_data);
  307. if (rx) {
  308. *rx++ = (u16) data;
  309. sspi->rx = rx;
  310. }
  311. sspi->left_rx_word--;
  312. }
  313. static void spi_sirfsoc_tx_word_u16(struct sirfsoc_spi *sspi)
  314. {
  315. u32 data = 0;
  316. const u16 *tx = sspi->tx;
  317. if (tx) {
  318. data = *tx++;
  319. sspi->tx = tx;
  320. }
  321. writel(data, sspi->base + sspi->regs->txfifo_data);
  322. sspi->left_tx_word--;
  323. }
  324. static void spi_sirfsoc_rx_word_u32(struct sirfsoc_spi *sspi)
  325. {
  326. u32 data;
  327. u32 *rx = sspi->rx;
  328. data = readl(sspi->base + sspi->regs->rxfifo_data);
  329. if (rx) {
  330. *rx++ = (u32) data;
  331. sspi->rx = rx;
  332. }
  333. sspi->left_rx_word--;
  334. }
  335. static void spi_sirfsoc_tx_word_u32(struct sirfsoc_spi *sspi)
  336. {
  337. u32 data = 0;
  338. const u32 *tx = sspi->tx;
  339. if (tx) {
  340. data = *tx++;
  341. sspi->tx = tx;
  342. }
  343. writel(data, sspi->base + sspi->regs->txfifo_data);
  344. sspi->left_tx_word--;
  345. }
  346. static irqreturn_t spi_sirfsoc_irq(int irq, void *dev_id)
  347. {
  348. struct sirfsoc_spi *sspi = dev_id;
  349. u32 spi_stat;
  350. spi_stat = readl(sspi->base + sspi->regs->int_st);
  351. if (sspi->tx_by_cmd && sspi->type == SIRF_REAL_SPI
  352. && (spi_stat & SIRFSOC_SPI_FRM_END)) {
  353. complete(&sspi->tx_done);
  354. writel(0x0, sspi->base + sspi->regs->int_en);
  355. writel(readl(sspi->base + sspi->regs->int_st),
  356. sspi->base + sspi->regs->int_st);
  357. return IRQ_HANDLED;
  358. }
  359. /* Error Conditions */
  360. if (spi_stat & SIRFSOC_SPI_RX_OFLOW ||
  361. spi_stat & SIRFSOC_SPI_TX_UFLOW) {
  362. complete(&sspi->tx_done);
  363. complete(&sspi->rx_done);
  364. switch (sspi->type) {
  365. case SIRF_REAL_SPI:
  366. case SIRF_USP_SPI_P2:
  367. writel(0x0, sspi->base + sspi->regs->int_en);
  368. break;
  369. case SIRF_USP_SPI_A7:
  370. writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr);
  371. break;
  372. }
  373. writel(readl(sspi->base + sspi->regs->int_st),
  374. sspi->base + sspi->regs->int_st);
  375. return IRQ_HANDLED;
  376. }
  377. if (spi_stat & SIRFSOC_SPI_TXFIFO_EMPTY)
  378. complete(&sspi->tx_done);
  379. while (!(readl(sspi->base + sspi->regs->int_st) &
  380. SIRFSOC_SPI_RX_IO_DMA))
  381. cpu_relax();
  382. complete(&sspi->rx_done);
  383. switch (sspi->type) {
  384. case SIRF_REAL_SPI:
  385. case SIRF_USP_SPI_P2:
  386. writel(0x0, sspi->base + sspi->regs->int_en);
  387. break;
  388. case SIRF_USP_SPI_A7:
  389. writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr);
  390. break;
  391. }
  392. writel(readl(sspi->base + sspi->regs->int_st),
  393. sspi->base + sspi->regs->int_st);
  394. return IRQ_HANDLED;
  395. }
  396. static void spi_sirfsoc_dma_fini_callback(void *data)
  397. {
  398. struct completion *dma_complete = data;
  399. complete(dma_complete);
  400. }
  401. static void spi_sirfsoc_cmd_transfer(struct spi_device *spi,
  402. struct spi_transfer *t)
  403. {
  404. struct sirfsoc_spi *sspi;
  405. int timeout = t->len * 10;
  406. u32 cmd;
  407. sspi = spi_master_get_devdata(spi->master);
  408. writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->txfifo_op);
  409. writel(SIRFSOC_SPI_FIFO_START, sspi->base + sspi->regs->txfifo_op);
  410. memcpy(&cmd, sspi->tx, t->len);
  411. if (sspi->word_width == 1 && !(spi->mode & SPI_LSB_FIRST))
  412. cmd = cpu_to_be32(cmd) >>
  413. ((SIRFSOC_MAX_CMD_BYTES - t->len) * 8);
  414. if (sspi->word_width == 2 && t->len == 4 &&
  415. (!(spi->mode & SPI_LSB_FIRST)))
  416. cmd = ((cmd & 0xffff) << 16) | (cmd >> 16);
  417. writel(cmd, sspi->base + sspi->regs->spi_cmd);
  418. writel(SIRFSOC_SPI_FRM_END_INT_EN,
  419. sspi->base + sspi->regs->int_en);
  420. writel(SIRFSOC_SPI_CMD_TX_EN,
  421. sspi->base + sspi->regs->tx_rx_en);
  422. if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) {
  423. dev_err(&spi->dev, "cmd transfer timeout\n");
  424. return;
  425. }
  426. sspi->left_rx_word -= t->len;
  427. }
  428. static void spi_sirfsoc_dma_transfer(struct spi_device *spi,
  429. struct spi_transfer *t)
  430. {
  431. struct sirfsoc_spi *sspi;
  432. struct dma_async_tx_descriptor *rx_desc, *tx_desc;
  433. int timeout = t->len * 10;
  434. sspi = spi_master_get_devdata(spi->master);
  435. writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->rxfifo_op);
  436. writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->txfifo_op);
  437. switch (sspi->type) {
  438. case SIRF_REAL_SPI:
  439. writel(SIRFSOC_SPI_FIFO_START,
  440. sspi->base + sspi->regs->rxfifo_op);
  441. writel(SIRFSOC_SPI_FIFO_START,
  442. sspi->base + sspi->regs->txfifo_op);
  443. writel(0, sspi->base + sspi->regs->int_en);
  444. break;
  445. case SIRF_USP_SPI_P2:
  446. writel(0x0, sspi->base + sspi->regs->rxfifo_op);
  447. writel(0x0, sspi->base + sspi->regs->txfifo_op);
  448. writel(0, sspi->base + sspi->regs->int_en);
  449. break;
  450. case SIRF_USP_SPI_A7:
  451. writel(0x0, sspi->base + sspi->regs->rxfifo_op);
  452. writel(0x0, sspi->base + sspi->regs->txfifo_op);
  453. writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr);
  454. break;
  455. }
  456. writel(readl(sspi->base + sspi->regs->int_st),
  457. sspi->base + sspi->regs->int_st);
  458. if (sspi->left_tx_word < sspi->dat_max_frm_len) {
  459. switch (sspi->type) {
  460. case SIRF_REAL_SPI:
  461. writel(readl(sspi->base + sspi->regs->spi_ctrl) |
  462. SIRFSOC_SPI_ENA_AUTO_CLR |
  463. SIRFSOC_SPI_MUL_DAT_MODE,
  464. sspi->base + sspi->regs->spi_ctrl);
  465. writel(sspi->left_tx_word - 1,
  466. sspi->base + sspi->regs->tx_dma_io_len);
  467. writel(sspi->left_tx_word - 1,
  468. sspi->base + sspi->regs->rx_dma_io_len);
  469. break;
  470. case SIRF_USP_SPI_P2:
  471. case SIRF_USP_SPI_A7:
  472. /*USP simulate SPI, tx/rx_dma_io_len indicates bytes*/
  473. writel(sspi->left_tx_word * sspi->word_width,
  474. sspi->base + sspi->regs->tx_dma_io_len);
  475. writel(sspi->left_tx_word * sspi->word_width,
  476. sspi->base + sspi->regs->rx_dma_io_len);
  477. break;
  478. }
  479. } else {
  480. if (sspi->type == SIRF_REAL_SPI)
  481. writel(readl(sspi->base + sspi->regs->spi_ctrl),
  482. sspi->base + sspi->regs->spi_ctrl);
  483. writel(0, sspi->base + sspi->regs->tx_dma_io_len);
  484. writel(0, sspi->base + sspi->regs->rx_dma_io_len);
  485. }
  486. sspi->dst_start = dma_map_single(&spi->dev, sspi->rx, t->len,
  487. (t->tx_buf != t->rx_buf) ?
  488. DMA_FROM_DEVICE : DMA_BIDIRECTIONAL);
  489. rx_desc = dmaengine_prep_slave_single(sspi->rx_chan,
  490. sspi->dst_start, t->len, DMA_DEV_TO_MEM,
  491. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  492. rx_desc->callback = spi_sirfsoc_dma_fini_callback;
  493. rx_desc->callback_param = &sspi->rx_done;
  494. sspi->src_start = dma_map_single(&spi->dev, (void *)sspi->tx, t->len,
  495. (t->tx_buf != t->rx_buf) ?
  496. DMA_TO_DEVICE : DMA_BIDIRECTIONAL);
  497. tx_desc = dmaengine_prep_slave_single(sspi->tx_chan,
  498. sspi->src_start, t->len, DMA_MEM_TO_DEV,
  499. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  500. tx_desc->callback = spi_sirfsoc_dma_fini_callback;
  501. tx_desc->callback_param = &sspi->tx_done;
  502. dmaengine_submit(tx_desc);
  503. dmaengine_submit(rx_desc);
  504. dma_async_issue_pending(sspi->tx_chan);
  505. dma_async_issue_pending(sspi->rx_chan);
  506. writel(SIRFSOC_SPI_RX_EN | SIRFSOC_SPI_TX_EN,
  507. sspi->base + sspi->regs->tx_rx_en);
  508. if (sspi->type == SIRF_USP_SPI_P2 ||
  509. sspi->type == SIRF_USP_SPI_A7) {
  510. writel(SIRFSOC_SPI_FIFO_START,
  511. sspi->base + sspi->regs->rxfifo_op);
  512. writel(SIRFSOC_SPI_FIFO_START,
  513. sspi->base + sspi->regs->txfifo_op);
  514. }
  515. if (wait_for_completion_timeout(&sspi->rx_done, timeout) == 0) {
  516. dev_err(&spi->dev, "transfer timeout\n");
  517. dmaengine_terminate_all(sspi->rx_chan);
  518. } else
  519. sspi->left_rx_word = 0;
  520. /*
  521. * we only wait tx-done event if transferring by DMA. for PIO,
  522. * we get rx data by writing tx data, so if rx is done, tx has
  523. * done earlier
  524. */
  525. if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) {
  526. dev_err(&spi->dev, "transfer timeout\n");
  527. if (sspi->type == SIRF_USP_SPI_P2 ||
  528. sspi->type == SIRF_USP_SPI_A7)
  529. writel(0, sspi->base + sspi->regs->tx_rx_en);
  530. dmaengine_terminate_all(sspi->tx_chan);
  531. }
  532. dma_unmap_single(&spi->dev, sspi->src_start, t->len, DMA_TO_DEVICE);
  533. dma_unmap_single(&spi->dev, sspi->dst_start, t->len, DMA_FROM_DEVICE);
  534. /* TX, RX FIFO stop */
  535. writel(0, sspi->base + sspi->regs->rxfifo_op);
  536. writel(0, sspi->base + sspi->regs->txfifo_op);
  537. if (sspi->left_tx_word >= sspi->dat_max_frm_len)
  538. writel(0, sspi->base + sspi->regs->tx_rx_en);
  539. if (sspi->type == SIRF_USP_SPI_P2 ||
  540. sspi->type == SIRF_USP_SPI_A7)
  541. writel(0, sspi->base + sspi->regs->tx_rx_en);
  542. }
  543. static void spi_sirfsoc_pio_transfer(struct spi_device *spi,
  544. struct spi_transfer *t)
  545. {
  546. struct sirfsoc_spi *sspi;
  547. int timeout = t->len * 10;
  548. unsigned int data_units;
  549. sspi = spi_master_get_devdata(spi->master);
  550. do {
  551. writel(SIRFSOC_SPI_FIFO_RESET,
  552. sspi->base + sspi->regs->rxfifo_op);
  553. writel(SIRFSOC_SPI_FIFO_RESET,
  554. sspi->base + sspi->regs->txfifo_op);
  555. switch (sspi->type) {
  556. case SIRF_USP_SPI_P2:
  557. writel(0x0, sspi->base + sspi->regs->rxfifo_op);
  558. writel(0x0, sspi->base + sspi->regs->txfifo_op);
  559. writel(0, sspi->base + sspi->regs->int_en);
  560. writel(readl(sspi->base + sspi->regs->int_st),
  561. sspi->base + sspi->regs->int_st);
  562. writel(min((sspi->left_tx_word * sspi->word_width),
  563. sspi->fifo_size),
  564. sspi->base + sspi->regs->tx_dma_io_len);
  565. writel(min((sspi->left_rx_word * sspi->word_width),
  566. sspi->fifo_size),
  567. sspi->base + sspi->regs->rx_dma_io_len);
  568. break;
  569. case SIRF_USP_SPI_A7:
  570. writel(0x0, sspi->base + sspi->regs->rxfifo_op);
  571. writel(0x0, sspi->base + sspi->regs->txfifo_op);
  572. writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr);
  573. writel(readl(sspi->base + sspi->regs->int_st),
  574. sspi->base + sspi->regs->int_st);
  575. writel(min((sspi->left_tx_word * sspi->word_width),
  576. sspi->fifo_size),
  577. sspi->base + sspi->regs->tx_dma_io_len);
  578. writel(min((sspi->left_rx_word * sspi->word_width),
  579. sspi->fifo_size),
  580. sspi->base + sspi->regs->rx_dma_io_len);
  581. break;
  582. case SIRF_REAL_SPI:
  583. writel(SIRFSOC_SPI_FIFO_START,
  584. sspi->base + sspi->regs->rxfifo_op);
  585. writel(SIRFSOC_SPI_FIFO_START,
  586. sspi->base + sspi->regs->txfifo_op);
  587. writel(0, sspi->base + sspi->regs->int_en);
  588. writel(readl(sspi->base + sspi->regs->int_st),
  589. sspi->base + sspi->regs->int_st);
  590. writel(readl(sspi->base + sspi->regs->spi_ctrl) |
  591. SIRFSOC_SPI_MUL_DAT_MODE |
  592. SIRFSOC_SPI_ENA_AUTO_CLR,
  593. sspi->base + sspi->regs->spi_ctrl);
  594. data_units = sspi->fifo_size / sspi->word_width;
  595. writel(min(sspi->left_tx_word, data_units) - 1,
  596. sspi->base + sspi->regs->tx_dma_io_len);
  597. writel(min(sspi->left_rx_word, data_units) - 1,
  598. sspi->base + sspi->regs->rx_dma_io_len);
  599. break;
  600. }
  601. while (!((readl(sspi->base + sspi->regs->txfifo_st)
  602. & SIRFSOC_SPI_FIFO_FULL_MASK(sspi))) &&
  603. sspi->left_tx_word)
  604. sspi->tx_word(sspi);
  605. writel(SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN |
  606. SIRFSOC_SPI_TX_UFLOW_INT_EN |
  607. SIRFSOC_SPI_RX_OFLOW_INT_EN |
  608. SIRFSOC_SPI_RX_IO_DMA_INT_EN,
  609. sspi->base + sspi->regs->int_en);
  610. writel(SIRFSOC_SPI_RX_EN | SIRFSOC_SPI_TX_EN,
  611. sspi->base + sspi->regs->tx_rx_en);
  612. if (sspi->type == SIRF_USP_SPI_P2 ||
  613. sspi->type == SIRF_USP_SPI_A7) {
  614. writel(SIRFSOC_SPI_FIFO_START,
  615. sspi->base + sspi->regs->rxfifo_op);
  616. writel(SIRFSOC_SPI_FIFO_START,
  617. sspi->base + sspi->regs->txfifo_op);
  618. }
  619. if (!wait_for_completion_timeout(&sspi->tx_done, timeout) ||
  620. !wait_for_completion_timeout(&sspi->rx_done, timeout)) {
  621. dev_err(&spi->dev, "transfer timeout\n");
  622. if (sspi->type == SIRF_USP_SPI_P2 ||
  623. sspi->type == SIRF_USP_SPI_A7)
  624. writel(0, sspi->base + sspi->regs->tx_rx_en);
  625. break;
  626. }
  627. while (!((readl(sspi->base + sspi->regs->rxfifo_st)
  628. & SIRFSOC_SPI_FIFO_EMPTY_MASK(sspi))) &&
  629. sspi->left_rx_word)
  630. sspi->rx_word(sspi);
  631. if (sspi->type == SIRF_USP_SPI_P2 ||
  632. sspi->type == SIRF_USP_SPI_A7)
  633. writel(0, sspi->base + sspi->regs->tx_rx_en);
  634. writel(0, sspi->base + sspi->regs->rxfifo_op);
  635. writel(0, sspi->base + sspi->regs->txfifo_op);
  636. } while (sspi->left_tx_word != 0 || sspi->left_rx_word != 0);
  637. }
  638. static int spi_sirfsoc_transfer(struct spi_device *spi, struct spi_transfer *t)
  639. {
  640. struct sirfsoc_spi *sspi;
  641. sspi = spi_master_get_devdata(spi->master);
  642. sspi->tx = t->tx_buf;
  643. sspi->rx = t->rx_buf;
  644. sspi->left_tx_word = sspi->left_rx_word = t->len / sspi->word_width;
  645. reinit_completion(&sspi->rx_done);
  646. reinit_completion(&sspi->tx_done);
  647. /*
  648. * in the transfer, if transfer data using command register with rx_buf
  649. * null, just fill command data into command register and wait for its
  650. * completion.
  651. */
  652. if (sspi->type == SIRF_REAL_SPI && sspi->tx_by_cmd)
  653. spi_sirfsoc_cmd_transfer(spi, t);
  654. else if (IS_DMA_VALID(t))
  655. spi_sirfsoc_dma_transfer(spi, t);
  656. else
  657. spi_sirfsoc_pio_transfer(spi, t);
  658. return t->len - sspi->left_rx_word * sspi->word_width;
  659. }
  660. static void spi_sirfsoc_chipselect(struct spi_device *spi, int value)
  661. {
  662. struct sirfsoc_spi *sspi = spi_master_get_devdata(spi->master);
  663. if (sspi->hw_cs) {
  664. u32 regval;
  665. switch (sspi->type) {
  666. case SIRF_REAL_SPI:
  667. regval = readl(sspi->base + sspi->regs->spi_ctrl);
  668. switch (value) {
  669. case BITBANG_CS_ACTIVE:
  670. if (spi->mode & SPI_CS_HIGH)
  671. regval |= SIRFSOC_SPI_CS_IO_OUT;
  672. else
  673. regval &= ~SIRFSOC_SPI_CS_IO_OUT;
  674. break;
  675. case BITBANG_CS_INACTIVE:
  676. if (spi->mode & SPI_CS_HIGH)
  677. regval &= ~SIRFSOC_SPI_CS_IO_OUT;
  678. else
  679. regval |= SIRFSOC_SPI_CS_IO_OUT;
  680. break;
  681. }
  682. writel(regval, sspi->base + sspi->regs->spi_ctrl);
  683. break;
  684. case SIRF_USP_SPI_P2:
  685. case SIRF_USP_SPI_A7:
  686. regval = readl(sspi->base +
  687. sspi->regs->usp_pin_io_data);
  688. switch (value) {
  689. case BITBANG_CS_ACTIVE:
  690. if (spi->mode & SPI_CS_HIGH)
  691. regval |= SIRFSOC_USP_CS_HIGH_VALUE;
  692. else
  693. regval &= ~(SIRFSOC_USP_CS_HIGH_VALUE);
  694. break;
  695. case BITBANG_CS_INACTIVE:
  696. if (spi->mode & SPI_CS_HIGH)
  697. regval &= ~(SIRFSOC_USP_CS_HIGH_VALUE);
  698. else
  699. regval |= SIRFSOC_USP_CS_HIGH_VALUE;
  700. break;
  701. }
  702. writel(regval,
  703. sspi->base + sspi->regs->usp_pin_io_data);
  704. break;
  705. }
  706. } else {
  707. switch (value) {
  708. case BITBANG_CS_ACTIVE:
  709. gpio_direction_output(spi->cs_gpio,
  710. spi->mode & SPI_CS_HIGH ? 1 : 0);
  711. break;
  712. case BITBANG_CS_INACTIVE:
  713. gpio_direction_output(spi->cs_gpio,
  714. spi->mode & SPI_CS_HIGH ? 0 : 1);
  715. break;
  716. }
  717. }
  718. }
  719. static int spi_sirfsoc_config_mode(struct spi_device *spi)
  720. {
  721. struct sirfsoc_spi *sspi;
  722. u32 regval, usp_mode1;
  723. sspi = spi_master_get_devdata(spi->master);
  724. regval = readl(sspi->base + sspi->regs->spi_ctrl);
  725. usp_mode1 = readl(sspi->base + sspi->regs->usp_mode1);
  726. if (!(spi->mode & SPI_CS_HIGH)) {
  727. regval |= SIRFSOC_SPI_CS_IDLE_STAT;
  728. usp_mode1 &= ~SIRFSOC_USP_CS_HIGH_VALID;
  729. } else {
  730. regval &= ~SIRFSOC_SPI_CS_IDLE_STAT;
  731. usp_mode1 |= SIRFSOC_USP_CS_HIGH_VALID;
  732. }
  733. if (!(spi->mode & SPI_LSB_FIRST)) {
  734. regval |= SIRFSOC_SPI_TRAN_MSB;
  735. usp_mode1 &= ~SIRFSOC_USP_LSB;
  736. } else {
  737. regval &= ~SIRFSOC_SPI_TRAN_MSB;
  738. usp_mode1 |= SIRFSOC_USP_LSB;
  739. }
  740. if (spi->mode & SPI_CPOL) {
  741. regval |= SIRFSOC_SPI_CLK_IDLE_STAT;
  742. usp_mode1 |= SIRFSOC_USP_SCLK_IDLE_STAT;
  743. } else {
  744. regval &= ~SIRFSOC_SPI_CLK_IDLE_STAT;
  745. usp_mode1 &= ~SIRFSOC_USP_SCLK_IDLE_STAT;
  746. }
  747. /*
  748. * Data should be driven at least 1/2 cycle before the fetch edge
  749. * to make sure that data gets stable at the fetch edge.
  750. */
  751. if (((spi->mode & SPI_CPOL) && (spi->mode & SPI_CPHA)) ||
  752. (!(spi->mode & SPI_CPOL) && !(spi->mode & SPI_CPHA))) {
  753. regval &= ~SIRFSOC_SPI_DRV_POS_EDGE;
  754. usp_mode1 |= (SIRFSOC_USP_TXD_FALLING_EDGE |
  755. SIRFSOC_USP_RXD_FALLING_EDGE);
  756. } else {
  757. regval |= SIRFSOC_SPI_DRV_POS_EDGE;
  758. usp_mode1 &= ~(SIRFSOC_USP_RXD_FALLING_EDGE |
  759. SIRFSOC_USP_TXD_FALLING_EDGE);
  760. }
  761. writel((SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(sspi, sspi->fifo_size - 2) <<
  762. SIRFSOC_SPI_FIFO_SC_OFFSET) |
  763. (SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(sspi, sspi->fifo_size / 2) <<
  764. SIRFSOC_SPI_FIFO_LC_OFFSET) |
  765. (SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(sspi, 2) <<
  766. SIRFSOC_SPI_FIFO_HC_OFFSET),
  767. sspi->base + sspi->regs->txfifo_level_chk);
  768. writel((SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(sspi, 2) <<
  769. SIRFSOC_SPI_FIFO_SC_OFFSET) |
  770. (SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(sspi, sspi->fifo_size / 2) <<
  771. SIRFSOC_SPI_FIFO_LC_OFFSET) |
  772. (SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(sspi, sspi->fifo_size - 2) <<
  773. SIRFSOC_SPI_FIFO_HC_OFFSET),
  774. sspi->base + sspi->regs->rxfifo_level_chk);
  775. /*
  776. * it should never set to hardware cs mode because in hardware cs mode,
  777. * cs signal can't controlled by driver.
  778. */
  779. switch (sspi->type) {
  780. case SIRF_REAL_SPI:
  781. regval |= SIRFSOC_SPI_CS_IO_MODE;
  782. writel(regval, sspi->base + sspi->regs->spi_ctrl);
  783. break;
  784. case SIRF_USP_SPI_P2:
  785. case SIRF_USP_SPI_A7:
  786. usp_mode1 |= SIRFSOC_USP_SYNC_MODE;
  787. usp_mode1 |= SIRFSOC_USP_TFS_IO_MODE;
  788. usp_mode1 &= ~SIRFSOC_USP_TFS_IO_INPUT;
  789. writel(usp_mode1, sspi->base + sspi->regs->usp_mode1);
  790. break;
  791. }
  792. return 0;
  793. }
  794. static int
  795. spi_sirfsoc_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
  796. {
  797. struct sirfsoc_spi *sspi;
  798. u8 bits_per_word = 0;
  799. int hz = 0;
  800. u32 regval, txfifo_ctrl, rxfifo_ctrl, tx_frm_ctl, rx_frm_ctl, usp_mode2;
  801. sspi = spi_master_get_devdata(spi->master);
  802. bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
  803. hz = t && t->speed_hz ? t->speed_hz : spi->max_speed_hz;
  804. usp_mode2 = regval = (sspi->ctrl_freq / (2 * hz)) - 1;
  805. if (regval > 0xFFFF || regval < 0) {
  806. dev_err(&spi->dev, "Speed %d not supported\n", hz);
  807. return -EINVAL;
  808. }
  809. switch (bits_per_word) {
  810. case 8:
  811. regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_8;
  812. sspi->rx_word = spi_sirfsoc_rx_word_u8;
  813. sspi->tx_word = spi_sirfsoc_tx_word_u8;
  814. break;
  815. case 12:
  816. case 16:
  817. regval |= (bits_per_word == 12) ?
  818. SIRFSOC_SPI_TRAN_DAT_FORMAT_12 :
  819. SIRFSOC_SPI_TRAN_DAT_FORMAT_16;
  820. sspi->rx_word = spi_sirfsoc_rx_word_u16;
  821. sspi->tx_word = spi_sirfsoc_tx_word_u16;
  822. break;
  823. case 32:
  824. regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_32;
  825. sspi->rx_word = spi_sirfsoc_rx_word_u32;
  826. sspi->tx_word = spi_sirfsoc_tx_word_u32;
  827. break;
  828. default:
  829. dev_err(&spi->dev, "bpw %d not supported\n", bits_per_word);
  830. return -EINVAL;
  831. }
  832. sspi->word_width = DIV_ROUND_UP(bits_per_word, 8);
  833. txfifo_ctrl = (((sspi->fifo_size / 2) &
  834. SIRFSOC_SPI_FIFO_THD_MASK(sspi))
  835. << SIRFSOC_SPI_FIFO_THD_OFFSET) |
  836. (sspi->word_width >> 1);
  837. rxfifo_ctrl = (((sspi->fifo_size / 2) &
  838. SIRFSOC_SPI_FIFO_THD_MASK(sspi))
  839. << SIRFSOC_SPI_FIFO_THD_OFFSET) |
  840. (sspi->word_width >> 1);
  841. writel(txfifo_ctrl, sspi->base + sspi->regs->txfifo_ctrl);
  842. writel(rxfifo_ctrl, sspi->base + sspi->regs->rxfifo_ctrl);
  843. if (sspi->type == SIRF_USP_SPI_P2 ||
  844. sspi->type == SIRF_USP_SPI_A7) {
  845. tx_frm_ctl = 0;
  846. tx_frm_ctl |= ((bits_per_word - 1) & SIRFSOC_USP_TX_DATA_MASK)
  847. << SIRFSOC_USP_TX_DATA_OFFSET;
  848. tx_frm_ctl |= ((bits_per_word + 1 + SIRFSOC_USP_TXD_DELAY_LEN
  849. - 1) & SIRFSOC_USP_TX_SYNC_MASK) <<
  850. SIRFSOC_USP_TX_SYNC_OFFSET;
  851. tx_frm_ctl |= ((bits_per_word + 1 + SIRFSOC_USP_TXD_DELAY_LEN
  852. + 2 - 1) & SIRFSOC_USP_TX_FRAME_MASK) <<
  853. SIRFSOC_USP_TX_FRAME_OFFSET;
  854. tx_frm_ctl |= ((bits_per_word - 1) &
  855. SIRFSOC_USP_TX_SHIFTER_MASK) <<
  856. SIRFSOC_USP_TX_SHIFTER_OFFSET;
  857. rx_frm_ctl = 0;
  858. rx_frm_ctl |= ((bits_per_word - 1) & SIRFSOC_USP_RX_DATA_MASK)
  859. << SIRFSOC_USP_RX_DATA_OFFSET;
  860. rx_frm_ctl |= ((bits_per_word + 1 + SIRFSOC_USP_RXD_DELAY_LEN
  861. + 2 - 1) & SIRFSOC_USP_RX_FRAME_MASK) <<
  862. SIRFSOC_USP_RX_FRAME_OFFSET;
  863. rx_frm_ctl |= ((bits_per_word - 1)
  864. & SIRFSOC_USP_RX_SHIFTER_MASK) <<
  865. SIRFSOC_USP_RX_SHIFTER_OFFSET;
  866. writel(tx_frm_ctl | (((usp_mode2 >> 10) &
  867. SIRFSOC_USP_CLK_10_11_MASK) <<
  868. SIRFSOC_USP_CLK_10_11_OFFSET),
  869. sspi->base + sspi->regs->usp_tx_frame_ctrl);
  870. writel(rx_frm_ctl | (((usp_mode2 >> 12) &
  871. SIRFSOC_USP_CLK_12_15_MASK) <<
  872. SIRFSOC_USP_CLK_12_15_OFFSET),
  873. sspi->base + sspi->regs->usp_rx_frame_ctrl);
  874. writel(readl(sspi->base + sspi->regs->usp_mode2) |
  875. ((usp_mode2 & SIRFSOC_USP_CLK_DIVISOR_MASK) <<
  876. SIRFSOC_USP_CLK_DIVISOR_OFFSET) |
  877. (SIRFSOC_USP_RXD_DELAY_LEN <<
  878. SIRFSOC_USP_RXD_DELAY_OFFSET) |
  879. (SIRFSOC_USP_TXD_DELAY_LEN <<
  880. SIRFSOC_USP_TXD_DELAY_OFFSET),
  881. sspi->base + sspi->regs->usp_mode2);
  882. }
  883. if (sspi->type == SIRF_REAL_SPI)
  884. writel(regval, sspi->base + sspi->regs->spi_ctrl);
  885. spi_sirfsoc_config_mode(spi);
  886. if (sspi->type == SIRF_REAL_SPI) {
  887. if (t && t->tx_buf && !t->rx_buf &&
  888. (t->len <= SIRFSOC_MAX_CMD_BYTES)) {
  889. sspi->tx_by_cmd = true;
  890. writel(readl(sspi->base + sspi->regs->spi_ctrl) |
  891. (SIRFSOC_SPI_CMD_BYTE_NUM((t->len - 1)) |
  892. SIRFSOC_SPI_CMD_MODE),
  893. sspi->base + sspi->regs->spi_ctrl);
  894. } else {
  895. sspi->tx_by_cmd = false;
  896. writel(readl(sspi->base + sspi->regs->spi_ctrl) &
  897. ~SIRFSOC_SPI_CMD_MODE,
  898. sspi->base + sspi->regs->spi_ctrl);
  899. }
  900. }
  901. if (IS_DMA_VALID(t)) {
  902. /* Enable DMA mode for RX, TX */
  903. writel(0, sspi->base + sspi->regs->tx_dma_io_ctrl);
  904. writel(SIRFSOC_SPI_RX_DMA_FLUSH,
  905. sspi->base + sspi->regs->rx_dma_io_ctrl);
  906. } else {
  907. /* Enable IO mode for RX, TX */
  908. writel(SIRFSOC_SPI_IO_MODE_SEL,
  909. sspi->base + sspi->regs->tx_dma_io_ctrl);
  910. writel(SIRFSOC_SPI_IO_MODE_SEL,
  911. sspi->base + sspi->regs->rx_dma_io_ctrl);
  912. }
  913. return 0;
  914. }
  915. static int spi_sirfsoc_setup(struct spi_device *spi)
  916. {
  917. struct sirfsoc_spi *sspi;
  918. int ret = 0;
  919. sspi = spi_master_get_devdata(spi->master);
  920. if (spi->cs_gpio == -ENOENT)
  921. sspi->hw_cs = true;
  922. else {
  923. sspi->hw_cs = false;
  924. if (!spi_get_ctldata(spi)) {
  925. void *cs = kmalloc(sizeof(int), GFP_KERNEL);
  926. if (!cs) {
  927. ret = -ENOMEM;
  928. goto exit;
  929. }
  930. ret = gpio_is_valid(spi->cs_gpio);
  931. if (!ret) {
  932. dev_err(&spi->dev, "no valid gpio\n");
  933. ret = -ENOENT;
  934. goto exit;
  935. }
  936. ret = gpio_request(spi->cs_gpio, DRIVER_NAME);
  937. if (ret) {
  938. dev_err(&spi->dev, "failed to request gpio\n");
  939. goto exit;
  940. }
  941. spi_set_ctldata(spi, cs);
  942. }
  943. }
  944. spi_sirfsoc_config_mode(spi);
  945. spi_sirfsoc_chipselect(spi, BITBANG_CS_INACTIVE);
  946. exit:
  947. return ret;
  948. }
  949. static void spi_sirfsoc_cleanup(struct spi_device *spi)
  950. {
  951. if (spi_get_ctldata(spi)) {
  952. gpio_free(spi->cs_gpio);
  953. kfree(spi_get_ctldata(spi));
  954. }
  955. }
  956. static const struct sirf_spi_comp_data sirf_real_spi = {
  957. .regs = &real_spi_register,
  958. .type = SIRF_REAL_SPI,
  959. .dat_max_frm_len = 64 * 1024,
  960. .fifo_size = 256,
  961. };
  962. static const struct sirf_spi_comp_data sirf_usp_spi_p2 = {
  963. .regs = &usp_spi_register,
  964. .type = SIRF_USP_SPI_P2,
  965. .dat_max_frm_len = 1024 * 1024,
  966. .fifo_size = 128,
  967. .hwinit = sirfsoc_usp_hwinit,
  968. };
  969. static const struct sirf_spi_comp_data sirf_usp_spi_a7 = {
  970. .regs = &usp_spi_register,
  971. .type = SIRF_USP_SPI_A7,
  972. .dat_max_frm_len = 1024 * 1024,
  973. .fifo_size = 512,
  974. .hwinit = sirfsoc_usp_hwinit,
  975. };
  976. static const struct of_device_id spi_sirfsoc_of_match[] = {
  977. { .compatible = "sirf,prima2-spi", .data = &sirf_real_spi},
  978. { .compatible = "sirf,prima2-usp-spi", .data = &sirf_usp_spi_p2},
  979. { .compatible = "sirf,atlas7-usp-spi", .data = &sirf_usp_spi_a7},
  980. {}
  981. };
  982. MODULE_DEVICE_TABLE(of, spi_sirfsoc_of_match);
  983. static int spi_sirfsoc_probe(struct platform_device *pdev)
  984. {
  985. struct sirfsoc_spi *sspi;
  986. struct spi_master *master;
  987. const struct sirf_spi_comp_data *spi_comp_data;
  988. int irq;
  989. int ret;
  990. const struct of_device_id *match;
  991. ret = device_reset(&pdev->dev);
  992. if (ret) {
  993. dev_err(&pdev->dev, "SPI reset failed!\n");
  994. return ret;
  995. }
  996. master = spi_alloc_master(&pdev->dev, sizeof(*sspi));
  997. if (!master) {
  998. dev_err(&pdev->dev, "Unable to allocate SPI master\n");
  999. return -ENOMEM;
  1000. }
  1001. match = of_match_node(spi_sirfsoc_of_match, pdev->dev.of_node);
  1002. platform_set_drvdata(pdev, master);
  1003. sspi = spi_master_get_devdata(master);
  1004. sspi->fifo_full_offset = ilog2(sspi->fifo_size);
  1005. spi_comp_data = match->data;
  1006. sspi->regs = spi_comp_data->regs;
  1007. sspi->type = spi_comp_data->type;
  1008. sspi->fifo_level_chk_mask = (sspi->fifo_size / 4) - 1;
  1009. sspi->dat_max_frm_len = spi_comp_data->dat_max_frm_len;
  1010. sspi->fifo_size = spi_comp_data->fifo_size;
  1011. sspi->base = devm_platform_ioremap_resource(pdev, 0);
  1012. if (IS_ERR(sspi->base)) {
  1013. ret = PTR_ERR(sspi->base);
  1014. goto free_master;
  1015. }
  1016. irq = platform_get_irq(pdev, 0);
  1017. if (irq < 0) {
  1018. ret = -ENXIO;
  1019. goto free_master;
  1020. }
  1021. ret = devm_request_irq(&pdev->dev, irq, spi_sirfsoc_irq, 0,
  1022. DRIVER_NAME, sspi);
  1023. if (ret)
  1024. goto free_master;
  1025. sspi->bitbang.master = master;
  1026. sspi->bitbang.chipselect = spi_sirfsoc_chipselect;
  1027. sspi->bitbang.setup_transfer = spi_sirfsoc_setup_transfer;
  1028. sspi->bitbang.txrx_bufs = spi_sirfsoc_transfer;
  1029. sspi->bitbang.master->setup = spi_sirfsoc_setup;
  1030. sspi->bitbang.master->cleanup = spi_sirfsoc_cleanup;
  1031. master->bus_num = pdev->id;
  1032. master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH;
  1033. master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(12) |
  1034. SPI_BPW_MASK(16) | SPI_BPW_MASK(32);
  1035. master->max_speed_hz = SIRFSOC_SPI_DEFAULT_FRQ;
  1036. master->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX;
  1037. sspi->bitbang.master->dev.of_node = pdev->dev.of_node;
  1038. /* request DMA channels */
  1039. sspi->rx_chan = dma_request_chan(&pdev->dev, "rx");
  1040. if (IS_ERR(sspi->rx_chan)) {
  1041. dev_err(&pdev->dev, "can not allocate rx dma channel\n");
  1042. ret = PTR_ERR(sspi->rx_chan);
  1043. goto free_master;
  1044. }
  1045. sspi->tx_chan = dma_request_chan(&pdev->dev, "tx");
  1046. if (IS_ERR(sspi->tx_chan)) {
  1047. dev_err(&pdev->dev, "can not allocate tx dma channel\n");
  1048. ret = PTR_ERR(sspi->tx_chan);
  1049. goto free_rx_dma;
  1050. }
  1051. sspi->clk = clk_get(&pdev->dev, NULL);
  1052. if (IS_ERR(sspi->clk)) {
  1053. ret = PTR_ERR(sspi->clk);
  1054. goto free_tx_dma;
  1055. }
  1056. clk_prepare_enable(sspi->clk);
  1057. if (spi_comp_data->hwinit)
  1058. spi_comp_data->hwinit(sspi);
  1059. sspi->ctrl_freq = clk_get_rate(sspi->clk);
  1060. init_completion(&sspi->rx_done);
  1061. init_completion(&sspi->tx_done);
  1062. ret = spi_bitbang_start(&sspi->bitbang);
  1063. if (ret)
  1064. goto free_clk;
  1065. dev_info(&pdev->dev, "registered, bus number = %d\n", master->bus_num);
  1066. return 0;
  1067. free_clk:
  1068. clk_disable_unprepare(sspi->clk);
  1069. clk_put(sspi->clk);
  1070. free_tx_dma:
  1071. dma_release_channel(sspi->tx_chan);
  1072. free_rx_dma:
  1073. dma_release_channel(sspi->rx_chan);
  1074. free_master:
  1075. spi_master_put(master);
  1076. return ret;
  1077. }
  1078. static int spi_sirfsoc_remove(struct platform_device *pdev)
  1079. {
  1080. struct spi_master *master;
  1081. struct sirfsoc_spi *sspi;
  1082. master = platform_get_drvdata(pdev);
  1083. sspi = spi_master_get_devdata(master);
  1084. spi_bitbang_stop(&sspi->bitbang);
  1085. clk_disable_unprepare(sspi->clk);
  1086. clk_put(sspi->clk);
  1087. dma_release_channel(sspi->rx_chan);
  1088. dma_release_channel(sspi->tx_chan);
  1089. spi_master_put(master);
  1090. return 0;
  1091. }
  1092. #ifdef CONFIG_PM_SLEEP
  1093. static int spi_sirfsoc_suspend(struct device *dev)
  1094. {
  1095. struct spi_master *master = dev_get_drvdata(dev);
  1096. struct sirfsoc_spi *sspi = spi_master_get_devdata(master);
  1097. int ret;
  1098. ret = spi_master_suspend(master);
  1099. if (ret)
  1100. return ret;
  1101. clk_disable(sspi->clk);
  1102. return 0;
  1103. }
  1104. static int spi_sirfsoc_resume(struct device *dev)
  1105. {
  1106. struct spi_master *master = dev_get_drvdata(dev);
  1107. struct sirfsoc_spi *sspi = spi_master_get_devdata(master);
  1108. clk_enable(sspi->clk);
  1109. writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->txfifo_op);
  1110. writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->rxfifo_op);
  1111. writel(SIRFSOC_SPI_FIFO_START, sspi->base + sspi->regs->txfifo_op);
  1112. writel(SIRFSOC_SPI_FIFO_START, sspi->base + sspi->regs->rxfifo_op);
  1113. return 0;
  1114. }
  1115. #endif
  1116. static SIMPLE_DEV_PM_OPS(spi_sirfsoc_pm_ops, spi_sirfsoc_suspend,
  1117. spi_sirfsoc_resume);
  1118. static struct platform_driver spi_sirfsoc_driver = {
  1119. .driver = {
  1120. .name = DRIVER_NAME,
  1121. .pm = &spi_sirfsoc_pm_ops,
  1122. .of_match_table = spi_sirfsoc_of_match,
  1123. },
  1124. .probe = spi_sirfsoc_probe,
  1125. .remove = spi_sirfsoc_remove,
  1126. };
  1127. module_platform_driver(spi_sirfsoc_driver);
  1128. MODULE_DESCRIPTION("SiRF SoC SPI master driver");
  1129. MODULE_AUTHOR("Zhiwu Song <Zhiwu.Song@csr.com>");
  1130. MODULE_AUTHOR("Barry Song <Baohua.Song@csr.com>");
  1131. MODULE_AUTHOR("Qipan Li <Qipan.Li@csr.com>");
  1132. MODULE_LICENSE("GPL v2");