spi-sh-hspi.c 6.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * SuperH HSPI bus driver
  4. *
  5. * Copyright (C) 2011 Kuninori Morimoto
  6. *
  7. * Based on spi-sh.c:
  8. * Based on pxa2xx_spi.c:
  9. * Copyright (C) 2011 Renesas Solutions Corp.
  10. * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
  11. */
  12. #include <linux/clk.h>
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/timer.h>
  16. #include <linux/delay.h>
  17. #include <linux/list.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/pm_runtime.h>
  21. #include <linux/io.h>
  22. #include <linux/spi/spi.h>
  23. #include <linux/spi/sh_hspi.h>
  24. #define SPCR 0x00
  25. #define SPSR 0x04
  26. #define SPSCR 0x08
  27. #define SPTBR 0x0C
  28. #define SPRBR 0x10
  29. #define SPCR2 0x14
  30. /* SPSR */
  31. #define RXFL (1 << 2)
  32. struct hspi_priv {
  33. void __iomem *addr;
  34. struct spi_controller *ctlr;
  35. struct device *dev;
  36. struct clk *clk;
  37. };
  38. /*
  39. * basic function
  40. */
  41. static void hspi_write(struct hspi_priv *hspi, int reg, u32 val)
  42. {
  43. iowrite32(val, hspi->addr + reg);
  44. }
  45. static u32 hspi_read(struct hspi_priv *hspi, int reg)
  46. {
  47. return ioread32(hspi->addr + reg);
  48. }
  49. static void hspi_bit_set(struct hspi_priv *hspi, int reg, u32 mask, u32 set)
  50. {
  51. u32 val = hspi_read(hspi, reg);
  52. val &= ~mask;
  53. val |= set & mask;
  54. hspi_write(hspi, reg, val);
  55. }
  56. /*
  57. * transfer function
  58. */
  59. static int hspi_status_check_timeout(struct hspi_priv *hspi, u32 mask, u32 val)
  60. {
  61. int t = 256;
  62. while (t--) {
  63. if ((mask & hspi_read(hspi, SPSR)) == val)
  64. return 0;
  65. udelay(10);
  66. }
  67. dev_err(hspi->dev, "timeout\n");
  68. return -ETIMEDOUT;
  69. }
  70. /*
  71. * spi master function
  72. */
  73. #define hspi_hw_cs_enable(hspi) hspi_hw_cs_ctrl(hspi, 0)
  74. #define hspi_hw_cs_disable(hspi) hspi_hw_cs_ctrl(hspi, 1)
  75. static void hspi_hw_cs_ctrl(struct hspi_priv *hspi, int hi)
  76. {
  77. hspi_bit_set(hspi, SPSCR, (1 << 6), (hi) << 6);
  78. }
  79. static void hspi_hw_setup(struct hspi_priv *hspi,
  80. struct spi_message *msg,
  81. struct spi_transfer *t)
  82. {
  83. struct spi_device *spi = msg->spi;
  84. struct device *dev = hspi->dev;
  85. u32 spcr, idiv_clk;
  86. u32 rate, best_rate, min, tmp;
  87. /*
  88. * find best IDIV/CLKCx settings
  89. */
  90. min = ~0;
  91. best_rate = 0;
  92. spcr = 0;
  93. for (idiv_clk = 0x00; idiv_clk <= 0x3F; idiv_clk++) {
  94. rate = clk_get_rate(hspi->clk);
  95. /* IDIV calculation */
  96. if (idiv_clk & (1 << 5))
  97. rate /= 128;
  98. else
  99. rate /= 16;
  100. /* CLKCx calculation */
  101. rate /= (((idiv_clk & 0x1F) + 1) * 2);
  102. /* save best settings */
  103. tmp = abs(t->speed_hz - rate);
  104. if (tmp < min) {
  105. min = tmp;
  106. spcr = idiv_clk;
  107. best_rate = rate;
  108. }
  109. }
  110. if (spi->mode & SPI_CPHA)
  111. spcr |= 1 << 7;
  112. if (spi->mode & SPI_CPOL)
  113. spcr |= 1 << 6;
  114. dev_dbg(dev, "speed %d/%d\n", t->speed_hz, best_rate);
  115. hspi_write(hspi, SPCR, spcr);
  116. hspi_write(hspi, SPSR, 0x0);
  117. hspi_write(hspi, SPSCR, 0x21); /* master mode / CS control */
  118. }
  119. static int hspi_transfer_one_message(struct spi_controller *ctlr,
  120. struct spi_message *msg)
  121. {
  122. struct hspi_priv *hspi = spi_controller_get_devdata(ctlr);
  123. struct spi_transfer *t;
  124. u32 tx;
  125. u32 rx;
  126. int ret, i;
  127. unsigned int cs_change;
  128. const int nsecs = 50;
  129. dev_dbg(hspi->dev, "%s\n", __func__);
  130. cs_change = 1;
  131. ret = 0;
  132. list_for_each_entry(t, &msg->transfers, transfer_list) {
  133. if (cs_change) {
  134. hspi_hw_setup(hspi, msg, t);
  135. hspi_hw_cs_enable(hspi);
  136. ndelay(nsecs);
  137. }
  138. cs_change = t->cs_change;
  139. for (i = 0; i < t->len; i++) {
  140. /* wait remains */
  141. ret = hspi_status_check_timeout(hspi, 0x1, 0);
  142. if (ret < 0)
  143. break;
  144. tx = 0;
  145. if (t->tx_buf)
  146. tx = (u32)((u8 *)t->tx_buf)[i];
  147. hspi_write(hspi, SPTBR, tx);
  148. /* wait receive */
  149. ret = hspi_status_check_timeout(hspi, 0x4, 0x4);
  150. if (ret < 0)
  151. break;
  152. rx = hspi_read(hspi, SPRBR);
  153. if (t->rx_buf)
  154. ((u8 *)t->rx_buf)[i] = (u8)rx;
  155. }
  156. msg->actual_length += t->len;
  157. spi_transfer_delay_exec(t);
  158. if (cs_change) {
  159. ndelay(nsecs);
  160. hspi_hw_cs_disable(hspi);
  161. ndelay(nsecs);
  162. }
  163. }
  164. msg->status = ret;
  165. if (!cs_change) {
  166. ndelay(nsecs);
  167. hspi_hw_cs_disable(hspi);
  168. }
  169. spi_finalize_current_message(ctlr);
  170. return ret;
  171. }
  172. static int hspi_probe(struct platform_device *pdev)
  173. {
  174. struct resource *res;
  175. struct spi_controller *ctlr;
  176. struct hspi_priv *hspi;
  177. struct clk *clk;
  178. int ret;
  179. /* get base addr */
  180. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  181. if (!res) {
  182. dev_err(&pdev->dev, "invalid resource\n");
  183. return -EINVAL;
  184. }
  185. ctlr = spi_alloc_master(&pdev->dev, sizeof(*hspi));
  186. if (!ctlr)
  187. return -ENOMEM;
  188. clk = clk_get(&pdev->dev, NULL);
  189. if (IS_ERR(clk)) {
  190. dev_err(&pdev->dev, "couldn't get clock\n");
  191. ret = -EINVAL;
  192. goto error0;
  193. }
  194. hspi = spi_controller_get_devdata(ctlr);
  195. platform_set_drvdata(pdev, hspi);
  196. /* init hspi */
  197. hspi->ctlr = ctlr;
  198. hspi->dev = &pdev->dev;
  199. hspi->clk = clk;
  200. hspi->addr = devm_ioremap(hspi->dev,
  201. res->start, resource_size(res));
  202. if (!hspi->addr) {
  203. ret = -ENOMEM;
  204. goto error1;
  205. }
  206. pm_runtime_enable(&pdev->dev);
  207. ctlr->bus_num = pdev->id;
  208. ctlr->mode_bits = SPI_CPOL | SPI_CPHA;
  209. ctlr->dev.of_node = pdev->dev.of_node;
  210. ctlr->auto_runtime_pm = true;
  211. ctlr->transfer_one_message = hspi_transfer_one_message;
  212. ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
  213. ret = devm_spi_register_controller(&pdev->dev, ctlr);
  214. if (ret < 0) {
  215. dev_err(&pdev->dev, "devm_spi_register_controller error.\n");
  216. goto error2;
  217. }
  218. return 0;
  219. error2:
  220. pm_runtime_disable(&pdev->dev);
  221. error1:
  222. clk_put(clk);
  223. error0:
  224. spi_controller_put(ctlr);
  225. return ret;
  226. }
  227. static int hspi_remove(struct platform_device *pdev)
  228. {
  229. struct hspi_priv *hspi = platform_get_drvdata(pdev);
  230. pm_runtime_disable(&pdev->dev);
  231. clk_put(hspi->clk);
  232. return 0;
  233. }
  234. static const struct of_device_id hspi_of_match[] = {
  235. { .compatible = "renesas,hspi", },
  236. { /* sentinel */ }
  237. };
  238. MODULE_DEVICE_TABLE(of, hspi_of_match);
  239. static struct platform_driver hspi_driver = {
  240. .probe = hspi_probe,
  241. .remove = hspi_remove,
  242. .driver = {
  243. .name = "sh-hspi",
  244. .of_match_table = hspi_of_match,
  245. },
  246. };
  247. module_platform_driver(hspi_driver);
  248. MODULE_DESCRIPTION("SuperH HSPI bus driver");
  249. MODULE_LICENSE("GPL v2");
  250. MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");
  251. MODULE_ALIAS("platform:sh-hspi");