spi-s3c24xx.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2006 Ben Dooks
  4. * Copyright 2006-2009 Simtec Electronics
  5. * Ben Dooks <ben@simtec.co.uk>
  6. */
  7. #include <linux/spinlock.h>
  8. #include <linux/interrupt.h>
  9. #include <linux/delay.h>
  10. #include <linux/errno.h>
  11. #include <linux/err.h>
  12. #include <linux/clk.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/gpio.h>
  15. #include <linux/io.h>
  16. #include <linux/slab.h>
  17. #include <linux/spi/spi.h>
  18. #include <linux/spi/spi_bitbang.h>
  19. #include <linux/spi/s3c24xx.h>
  20. #include <linux/spi/s3c24xx-fiq.h>
  21. #include <linux/module.h>
  22. #include <asm/fiq.h>
  23. #include "spi-s3c24xx-regs.h"
  24. /**
  25. * struct s3c24xx_spi_devstate - per device data
  26. * @hz: Last frequency calculated for @sppre field.
  27. * @mode: Last mode setting for the @spcon field.
  28. * @spcon: Value to write to the SPCON register.
  29. * @sppre: Value to write to the SPPRE register.
  30. */
  31. struct s3c24xx_spi_devstate {
  32. unsigned int hz;
  33. unsigned int mode;
  34. u8 spcon;
  35. u8 sppre;
  36. };
  37. enum spi_fiq_mode {
  38. FIQ_MODE_NONE = 0,
  39. FIQ_MODE_TX = 1,
  40. FIQ_MODE_RX = 2,
  41. FIQ_MODE_TXRX = 3,
  42. };
  43. struct s3c24xx_spi {
  44. /* bitbang has to be first */
  45. struct spi_bitbang bitbang;
  46. struct completion done;
  47. void __iomem *regs;
  48. int irq;
  49. int len;
  50. int count;
  51. struct fiq_handler fiq_handler;
  52. enum spi_fiq_mode fiq_mode;
  53. unsigned char fiq_inuse;
  54. unsigned char fiq_claimed;
  55. void (*set_cs)(struct s3c2410_spi_info *spi,
  56. int cs, int pol);
  57. /* data buffers */
  58. const unsigned char *tx;
  59. unsigned char *rx;
  60. struct clk *clk;
  61. struct spi_master *master;
  62. struct spi_device *curdev;
  63. struct device *dev;
  64. struct s3c2410_spi_info *pdata;
  65. };
  66. #define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT)
  67. #define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP)
  68. static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev)
  69. {
  70. return spi_master_get_devdata(sdev->master);
  71. }
  72. static void s3c24xx_spi_gpiocs(struct s3c2410_spi_info *spi, int cs, int pol)
  73. {
  74. gpio_set_value(spi->pin_cs, pol);
  75. }
  76. static void s3c24xx_spi_chipsel(struct spi_device *spi, int value)
  77. {
  78. struct s3c24xx_spi_devstate *cs = spi->controller_state;
  79. struct s3c24xx_spi *hw = to_hw(spi);
  80. unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
  81. /* change the chipselect state and the state of the spi engine clock */
  82. switch (value) {
  83. case BITBANG_CS_INACTIVE:
  84. hw->set_cs(hw->pdata, spi->chip_select, cspol^1);
  85. writeb(cs->spcon, hw->regs + S3C2410_SPCON);
  86. break;
  87. case BITBANG_CS_ACTIVE:
  88. writeb(cs->spcon | S3C2410_SPCON_ENSCK,
  89. hw->regs + S3C2410_SPCON);
  90. hw->set_cs(hw->pdata, spi->chip_select, cspol);
  91. break;
  92. }
  93. }
  94. static int s3c24xx_spi_update_state(struct spi_device *spi,
  95. struct spi_transfer *t)
  96. {
  97. struct s3c24xx_spi *hw = to_hw(spi);
  98. struct s3c24xx_spi_devstate *cs = spi->controller_state;
  99. unsigned int hz;
  100. unsigned int div;
  101. unsigned long clk;
  102. hz = t ? t->speed_hz : spi->max_speed_hz;
  103. if (!hz)
  104. hz = spi->max_speed_hz;
  105. if (spi->mode != cs->mode) {
  106. u8 spcon = SPCON_DEFAULT | S3C2410_SPCON_ENSCK;
  107. if (spi->mode & SPI_CPHA)
  108. spcon |= S3C2410_SPCON_CPHA_FMTB;
  109. if (spi->mode & SPI_CPOL)
  110. spcon |= S3C2410_SPCON_CPOL_HIGH;
  111. cs->mode = spi->mode;
  112. cs->spcon = spcon;
  113. }
  114. if (cs->hz != hz) {
  115. clk = clk_get_rate(hw->clk);
  116. div = DIV_ROUND_UP(clk, hz * 2) - 1;
  117. if (div > 255)
  118. div = 255;
  119. dev_dbg(&spi->dev, "pre-scaler=%d (wanted %d, got %ld)\n",
  120. div, hz, clk / (2 * (div + 1)));
  121. cs->hz = hz;
  122. cs->sppre = div;
  123. }
  124. return 0;
  125. }
  126. static int s3c24xx_spi_setupxfer(struct spi_device *spi,
  127. struct spi_transfer *t)
  128. {
  129. struct s3c24xx_spi_devstate *cs = spi->controller_state;
  130. struct s3c24xx_spi *hw = to_hw(spi);
  131. int ret;
  132. ret = s3c24xx_spi_update_state(spi, t);
  133. if (!ret)
  134. writeb(cs->sppre, hw->regs + S3C2410_SPPRE);
  135. return ret;
  136. }
  137. static int s3c24xx_spi_setup(struct spi_device *spi)
  138. {
  139. struct s3c24xx_spi_devstate *cs = spi->controller_state;
  140. struct s3c24xx_spi *hw = to_hw(spi);
  141. int ret;
  142. /* allocate settings on the first call */
  143. if (!cs) {
  144. cs = devm_kzalloc(&spi->dev,
  145. sizeof(struct s3c24xx_spi_devstate),
  146. GFP_KERNEL);
  147. if (!cs)
  148. return -ENOMEM;
  149. cs->spcon = SPCON_DEFAULT;
  150. cs->hz = -1;
  151. spi->controller_state = cs;
  152. }
  153. /* initialise the state from the device */
  154. ret = s3c24xx_spi_update_state(spi, NULL);
  155. if (ret)
  156. return ret;
  157. mutex_lock(&hw->bitbang.lock);
  158. if (!hw->bitbang.busy) {
  159. hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
  160. /* need to ndelay for 0.5 clocktick ? */
  161. }
  162. mutex_unlock(&hw->bitbang.lock);
  163. return 0;
  164. }
  165. static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count)
  166. {
  167. return hw->tx ? hw->tx[count] : 0;
  168. }
  169. #ifdef CONFIG_SPI_S3C24XX_FIQ
  170. /* Support for FIQ based pseudo-DMA to improve the transfer speed.
  171. *
  172. * This code uses the assembly helper in spi_s3c24xx_spi.S which is
  173. * used by the FIQ core to move data between main memory and the peripheral
  174. * block. Since this is code running on the processor, there is no problem
  175. * with cache coherency of the buffers, so we can use any buffer we like.
  176. */
  177. /**
  178. * struct spi_fiq_code - FIQ code and header
  179. * @length: The length of the code fragment, excluding this header.
  180. * @ack_offset: The offset from @data to the word to place the IRQ ACK bit at.
  181. * @data: The code itself to install as a FIQ handler.
  182. */
  183. struct spi_fiq_code {
  184. u32 length;
  185. u32 ack_offset;
  186. u8 data[];
  187. };
  188. /**
  189. * s3c24xx_spi_tryfiq - attempt to claim and setup FIQ for transfer
  190. * @hw: The hardware state.
  191. *
  192. * Claim the FIQ handler (only one can be active at any one time) and
  193. * then setup the correct transfer code for this transfer.
  194. *
  195. * This call updates all the necessary state information if successful,
  196. * so the caller does not need to do anything more than start the transfer
  197. * as normal, since the IRQ will have been re-routed to the FIQ handler.
  198. */
  199. static void s3c24xx_spi_tryfiq(struct s3c24xx_spi *hw)
  200. {
  201. struct pt_regs regs;
  202. enum spi_fiq_mode mode;
  203. struct spi_fiq_code *code;
  204. u32 *ack_ptr = NULL;
  205. int ret;
  206. if (!hw->fiq_claimed) {
  207. /* try and claim fiq if we haven't got it, and if not
  208. * then return and simply use another transfer method */
  209. ret = claim_fiq(&hw->fiq_handler);
  210. if (ret)
  211. return;
  212. }
  213. if (hw->tx && !hw->rx)
  214. mode = FIQ_MODE_TX;
  215. else if (hw->rx && !hw->tx)
  216. mode = FIQ_MODE_RX;
  217. else
  218. mode = FIQ_MODE_TXRX;
  219. regs.uregs[fiq_rspi] = (long)hw->regs;
  220. regs.uregs[fiq_rrx] = (long)hw->rx;
  221. regs.uregs[fiq_rtx] = (long)hw->tx + 1;
  222. regs.uregs[fiq_rcount] = hw->len - 1;
  223. set_fiq_regs(&regs);
  224. if (hw->fiq_mode != mode) {
  225. hw->fiq_mode = mode;
  226. switch (mode) {
  227. case FIQ_MODE_TX:
  228. code = &s3c24xx_spi_fiq_tx;
  229. break;
  230. case FIQ_MODE_RX:
  231. code = &s3c24xx_spi_fiq_rx;
  232. break;
  233. case FIQ_MODE_TXRX:
  234. code = &s3c24xx_spi_fiq_txrx;
  235. break;
  236. default:
  237. code = NULL;
  238. }
  239. BUG_ON(!code);
  240. ack_ptr = (u32 *)&code->data[code->ack_offset];
  241. set_fiq_handler(&code->data, code->length);
  242. }
  243. s3c24xx_set_fiq(hw->irq, ack_ptr, true);
  244. hw->fiq_mode = mode;
  245. hw->fiq_inuse = 1;
  246. }
  247. /**
  248. * s3c24xx_spi_fiqop - FIQ core code callback
  249. * @pw: Data registered with the handler
  250. * @release: Whether this is a release or a return.
  251. *
  252. * Called by the FIQ code when another module wants to use the FIQ, so
  253. * return whether we are currently using this or not and then update our
  254. * internal state.
  255. */
  256. static int s3c24xx_spi_fiqop(void *pw, int release)
  257. {
  258. struct s3c24xx_spi *hw = pw;
  259. int ret = 0;
  260. if (release) {
  261. if (hw->fiq_inuse)
  262. ret = -EBUSY;
  263. /* note, we do not need to unroute the FIQ, as the FIQ
  264. * vector code de-routes it to signal the end of transfer */
  265. hw->fiq_mode = FIQ_MODE_NONE;
  266. hw->fiq_claimed = 0;
  267. } else {
  268. hw->fiq_claimed = 1;
  269. }
  270. return ret;
  271. }
  272. /**
  273. * s3c24xx_spi_initfiq - setup the information for the FIQ core
  274. * @hw: The hardware state.
  275. *
  276. * Setup the fiq_handler block to pass to the FIQ core.
  277. */
  278. static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *hw)
  279. {
  280. hw->fiq_handler.dev_id = hw;
  281. hw->fiq_handler.name = dev_name(hw->dev);
  282. hw->fiq_handler.fiq_op = s3c24xx_spi_fiqop;
  283. }
  284. /**
  285. * s3c24xx_spi_usefiq - return if we should be using FIQ.
  286. * @hw: The hardware state.
  287. *
  288. * Return true if the platform data specifies whether this channel is
  289. * allowed to use the FIQ.
  290. */
  291. static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *hw)
  292. {
  293. return hw->pdata->use_fiq;
  294. }
  295. /**
  296. * s3c24xx_spi_usingfiq - return if channel is using FIQ
  297. * @spi: The hardware state.
  298. *
  299. * Return whether the channel is currently using the FIQ (separate from
  300. * whether the FIQ is claimed).
  301. */
  302. static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *spi)
  303. {
  304. return spi->fiq_inuse;
  305. }
  306. #else
  307. static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *s) { }
  308. static inline void s3c24xx_spi_tryfiq(struct s3c24xx_spi *s) { }
  309. static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *s) { return false; }
  310. static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *s) { return false; }
  311. #endif /* CONFIG_SPI_S3C24XX_FIQ */
  312. static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
  313. {
  314. struct s3c24xx_spi *hw = to_hw(spi);
  315. hw->tx = t->tx_buf;
  316. hw->rx = t->rx_buf;
  317. hw->len = t->len;
  318. hw->count = 0;
  319. init_completion(&hw->done);
  320. hw->fiq_inuse = 0;
  321. if (s3c24xx_spi_usefiq(hw) && t->len >= 3)
  322. s3c24xx_spi_tryfiq(hw);
  323. /* send the first byte */
  324. writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT);
  325. wait_for_completion(&hw->done);
  326. return hw->count;
  327. }
  328. static irqreturn_t s3c24xx_spi_irq(int irq, void *dev)
  329. {
  330. struct s3c24xx_spi *hw = dev;
  331. unsigned int spsta = readb(hw->regs + S3C2410_SPSTA);
  332. unsigned int count = hw->count;
  333. if (spsta & S3C2410_SPSTA_DCOL) {
  334. dev_dbg(hw->dev, "data-collision\n");
  335. complete(&hw->done);
  336. goto irq_done;
  337. }
  338. if (!(spsta & S3C2410_SPSTA_READY)) {
  339. dev_dbg(hw->dev, "spi not ready for tx?\n");
  340. complete(&hw->done);
  341. goto irq_done;
  342. }
  343. if (!s3c24xx_spi_usingfiq(hw)) {
  344. hw->count++;
  345. if (hw->rx)
  346. hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT);
  347. count++;
  348. if (count < hw->len)
  349. writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT);
  350. else
  351. complete(&hw->done);
  352. } else {
  353. hw->count = hw->len;
  354. hw->fiq_inuse = 0;
  355. if (hw->rx)
  356. hw->rx[hw->len-1] = readb(hw->regs + S3C2410_SPRDAT);
  357. complete(&hw->done);
  358. }
  359. irq_done:
  360. return IRQ_HANDLED;
  361. }
  362. static void s3c24xx_spi_initialsetup(struct s3c24xx_spi *hw)
  363. {
  364. /* for the moment, permanently enable the clock */
  365. clk_enable(hw->clk);
  366. /* program defaults into the registers */
  367. writeb(0xff, hw->regs + S3C2410_SPPRE);
  368. writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN);
  369. writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON);
  370. if (hw->pdata) {
  371. if (hw->set_cs == s3c24xx_spi_gpiocs)
  372. gpio_direction_output(hw->pdata->pin_cs, 1);
  373. if (hw->pdata->gpio_setup)
  374. hw->pdata->gpio_setup(hw->pdata, 1);
  375. }
  376. }
  377. static int s3c24xx_spi_probe(struct platform_device *pdev)
  378. {
  379. struct s3c2410_spi_info *pdata;
  380. struct s3c24xx_spi *hw;
  381. struct spi_master *master;
  382. int err = 0;
  383. master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi));
  384. if (master == NULL) {
  385. dev_err(&pdev->dev, "No memory for spi_master\n");
  386. return -ENOMEM;
  387. }
  388. hw = spi_master_get_devdata(master);
  389. hw->master = master;
  390. hw->pdata = pdata = dev_get_platdata(&pdev->dev);
  391. hw->dev = &pdev->dev;
  392. if (pdata == NULL) {
  393. dev_err(&pdev->dev, "No platform data supplied\n");
  394. err = -ENOENT;
  395. goto err_no_pdata;
  396. }
  397. platform_set_drvdata(pdev, hw);
  398. init_completion(&hw->done);
  399. /* initialise fiq handler */
  400. s3c24xx_spi_initfiq(hw);
  401. /* setup the master state. */
  402. /* the spi->mode bits understood by this driver: */
  403. master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
  404. master->num_chipselect = hw->pdata->num_cs;
  405. master->bus_num = pdata->bus_num;
  406. master->bits_per_word_mask = SPI_BPW_MASK(8);
  407. /* setup the state for the bitbang driver */
  408. hw->bitbang.master = hw->master;
  409. hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer;
  410. hw->bitbang.chipselect = s3c24xx_spi_chipsel;
  411. hw->bitbang.txrx_bufs = s3c24xx_spi_txrx;
  412. hw->master->setup = s3c24xx_spi_setup;
  413. dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
  414. /* find and map our resources */
  415. hw->regs = devm_platform_ioremap_resource(pdev, 0);
  416. if (IS_ERR(hw->regs)) {
  417. err = PTR_ERR(hw->regs);
  418. goto err_no_pdata;
  419. }
  420. hw->irq = platform_get_irq(pdev, 0);
  421. if (hw->irq < 0) {
  422. err = -ENOENT;
  423. goto err_no_pdata;
  424. }
  425. err = devm_request_irq(&pdev->dev, hw->irq, s3c24xx_spi_irq, 0,
  426. pdev->name, hw);
  427. if (err) {
  428. dev_err(&pdev->dev, "Cannot claim IRQ\n");
  429. goto err_no_pdata;
  430. }
  431. hw->clk = devm_clk_get(&pdev->dev, "spi");
  432. if (IS_ERR(hw->clk)) {
  433. dev_err(&pdev->dev, "No clock for device\n");
  434. err = PTR_ERR(hw->clk);
  435. goto err_no_pdata;
  436. }
  437. /* setup any gpio we can */
  438. if (!pdata->set_cs) {
  439. if (pdata->pin_cs < 0) {
  440. dev_err(&pdev->dev, "No chipselect pin\n");
  441. err = -EINVAL;
  442. goto err_register;
  443. }
  444. err = devm_gpio_request(&pdev->dev, pdata->pin_cs,
  445. dev_name(&pdev->dev));
  446. if (err) {
  447. dev_err(&pdev->dev, "Failed to get gpio for cs\n");
  448. goto err_register;
  449. }
  450. hw->set_cs = s3c24xx_spi_gpiocs;
  451. gpio_direction_output(pdata->pin_cs, 1);
  452. } else
  453. hw->set_cs = pdata->set_cs;
  454. s3c24xx_spi_initialsetup(hw);
  455. /* register our spi controller */
  456. err = spi_bitbang_start(&hw->bitbang);
  457. if (err) {
  458. dev_err(&pdev->dev, "Failed to register SPI master\n");
  459. goto err_register;
  460. }
  461. return 0;
  462. err_register:
  463. clk_disable(hw->clk);
  464. err_no_pdata:
  465. spi_master_put(hw->master);
  466. return err;
  467. }
  468. static int s3c24xx_spi_remove(struct platform_device *dev)
  469. {
  470. struct s3c24xx_spi *hw = platform_get_drvdata(dev);
  471. spi_bitbang_stop(&hw->bitbang);
  472. clk_disable(hw->clk);
  473. spi_master_put(hw->master);
  474. return 0;
  475. }
  476. #ifdef CONFIG_PM
  477. static int s3c24xx_spi_suspend(struct device *dev)
  478. {
  479. struct s3c24xx_spi *hw = dev_get_drvdata(dev);
  480. int ret;
  481. ret = spi_master_suspend(hw->master);
  482. if (ret)
  483. return ret;
  484. if (hw->pdata && hw->pdata->gpio_setup)
  485. hw->pdata->gpio_setup(hw->pdata, 0);
  486. clk_disable(hw->clk);
  487. return 0;
  488. }
  489. static int s3c24xx_spi_resume(struct device *dev)
  490. {
  491. struct s3c24xx_spi *hw = dev_get_drvdata(dev);
  492. s3c24xx_spi_initialsetup(hw);
  493. return spi_master_resume(hw->master);
  494. }
  495. static const struct dev_pm_ops s3c24xx_spi_pmops = {
  496. .suspend = s3c24xx_spi_suspend,
  497. .resume = s3c24xx_spi_resume,
  498. };
  499. #define S3C24XX_SPI_PMOPS &s3c24xx_spi_pmops
  500. #else
  501. #define S3C24XX_SPI_PMOPS NULL
  502. #endif /* CONFIG_PM */
  503. MODULE_ALIAS("platform:s3c2410-spi");
  504. static struct platform_driver s3c24xx_spi_driver = {
  505. .probe = s3c24xx_spi_probe,
  506. .remove = s3c24xx_spi_remove,
  507. .driver = {
  508. .name = "s3c2410-spi",
  509. .pm = S3C24XX_SPI_PMOPS,
  510. },
  511. };
  512. module_platform_driver(s3c24xx_spi_driver);
  513. MODULE_DESCRIPTION("S3C24XX SPI Driver");
  514. MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
  515. MODULE_LICENSE("GPL");