spi-s3c24xx-regs.h 1.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (c) 2004 Fetron GmbH
  4. *
  5. * S3C2410 SPI register definition
  6. */
  7. #ifndef __SPI_S3C2410_H
  8. #define __SPI_S3C2410_H
  9. #define S3C2410_SPCON (0x00)
  10. #define S3C2410_SPCON_SMOD_DMA (2 << 5) /* DMA mode */
  11. #define S3C2410_SPCON_SMOD_INT (1 << 5) /* interrupt mode */
  12. #define S3C2410_SPCON_SMOD_POLL (0 << 5) /* polling mode */
  13. #define S3C2410_SPCON_ENSCK (1 << 4) /* Enable SCK */
  14. #define S3C2410_SPCON_MSTR (1 << 3) /* Master:1, Slave:0 select */
  15. #define S3C2410_SPCON_CPOL_HIGH (1 << 2) /* Clock polarity select */
  16. #define S3C2410_SPCON_CPOL_LOW (0 << 2) /* Clock polarity select */
  17. #define S3C2410_SPCON_CPHA_FMTB (1 << 1) /* Clock Phase Select */
  18. #define S3C2410_SPCON_CPHA_FMTA (0 << 1) /* Clock Phase Select */
  19. #define S3C2410_SPSTA (0x04)
  20. #define S3C2410_SPSTA_DCOL (1 << 2) /* Data Collision Error */
  21. #define S3C2410_SPSTA_MULD (1 << 1) /* Multi Master Error */
  22. #define S3C2410_SPSTA_READY (1 << 0) /* Data Tx/Rx ready */
  23. #define S3C2412_SPSTA_READY_ORG (1 << 3)
  24. #define S3C2410_SPPIN (0x08)
  25. #define S3C2410_SPPIN_ENMUL (1 << 2) /* Multi Master Error detect */
  26. #define S3C2410_SPPIN_RESERVED (1 << 1)
  27. #define S3C2410_SPPIN_KEEP (1 << 0) /* Master Out keep */
  28. #define S3C2410_SPPRE (0x0C)
  29. #define S3C2410_SPTDAT (0x10)
  30. #define S3C2410_SPRDAT (0x14)
  31. #endif /* __SPI_S3C2410_H */