spi-rb4xx.c 5.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * SPI controller driver for the Mikrotik RB4xx boards
  4. *
  5. * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
  6. * Copyright (C) 2015 Bert Vermeulen <bert@biot.com>
  7. *
  8. * This file was based on the patches for Linux 2.6.27.39 published by
  9. * MikroTik for their RouterBoard 4xx series devices.
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/module.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/clk.h>
  15. #include <linux/spi/spi.h>
  16. #include <linux/of.h>
  17. #include <asm/mach-ath79/ar71xx_regs.h>
  18. struct rb4xx_spi {
  19. void __iomem *base;
  20. struct clk *clk;
  21. };
  22. static inline u32 rb4xx_read(struct rb4xx_spi *rbspi, u32 reg)
  23. {
  24. return __raw_readl(rbspi->base + reg);
  25. }
  26. static inline void rb4xx_write(struct rb4xx_spi *rbspi, u32 reg, u32 value)
  27. {
  28. __raw_writel(value, rbspi->base + reg);
  29. }
  30. static inline void do_spi_clk(struct rb4xx_spi *rbspi, u32 spi_ioc, int value)
  31. {
  32. u32 regval;
  33. regval = spi_ioc;
  34. if (value & BIT(0))
  35. regval |= AR71XX_SPI_IOC_DO;
  36. rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval);
  37. rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval | AR71XX_SPI_IOC_CLK);
  38. }
  39. static void do_spi_byte(struct rb4xx_spi *rbspi, u32 spi_ioc, u8 byte)
  40. {
  41. int i;
  42. for (i = 7; i >= 0; i--)
  43. do_spi_clk(rbspi, spi_ioc, byte >> i);
  44. }
  45. /* The CS2 pin is used to clock in a second bit per clock cycle. */
  46. static inline void do_spi_clk_two(struct rb4xx_spi *rbspi, u32 spi_ioc,
  47. u8 value)
  48. {
  49. u32 regval;
  50. regval = spi_ioc;
  51. if (value & BIT(1))
  52. regval |= AR71XX_SPI_IOC_DO;
  53. if (value & BIT(0))
  54. regval |= AR71XX_SPI_IOC_CS2;
  55. rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval);
  56. rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval | AR71XX_SPI_IOC_CLK);
  57. }
  58. /* Two bits at a time, msb first */
  59. static void do_spi_byte_two(struct rb4xx_spi *rbspi, u32 spi_ioc, u8 byte)
  60. {
  61. do_spi_clk_two(rbspi, spi_ioc, byte >> 6);
  62. do_spi_clk_two(rbspi, spi_ioc, byte >> 4);
  63. do_spi_clk_two(rbspi, spi_ioc, byte >> 2);
  64. do_spi_clk_two(rbspi, spi_ioc, byte >> 0);
  65. }
  66. static void rb4xx_set_cs(struct spi_device *spi, bool enable)
  67. {
  68. struct rb4xx_spi *rbspi = spi_master_get_devdata(spi->master);
  69. /*
  70. * Setting CS is done along with bitbanging the actual values,
  71. * since it's all on the same hardware register. However the
  72. * CPLD needs CS deselected after every command.
  73. */
  74. if (enable)
  75. rb4xx_write(rbspi, AR71XX_SPI_REG_IOC,
  76. AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1);
  77. }
  78. static int rb4xx_transfer_one(struct spi_master *master,
  79. struct spi_device *spi, struct spi_transfer *t)
  80. {
  81. struct rb4xx_spi *rbspi = spi_master_get_devdata(master);
  82. int i;
  83. u32 spi_ioc;
  84. u8 *rx_buf;
  85. const u8 *tx_buf;
  86. /*
  87. * Prime the SPI register with the SPI device selected. The m25p80 boot
  88. * flash and CPLD share the CS0 pin. This works because the CPLD's
  89. * command set was designed to almost not clash with that of the
  90. * boot flash.
  91. */
  92. if (spi->chip_select == 2)
  93. /* MMC */
  94. spi_ioc = AR71XX_SPI_IOC_CS0;
  95. else
  96. /* Boot flash and CPLD */
  97. spi_ioc = AR71XX_SPI_IOC_CS1;
  98. tx_buf = t->tx_buf;
  99. rx_buf = t->rx_buf;
  100. for (i = 0; i < t->len; ++i) {
  101. if (t->tx_nbits == SPI_NBITS_DUAL)
  102. /* CPLD can use two-wire transfers */
  103. do_spi_byte_two(rbspi, spi_ioc, tx_buf[i]);
  104. else
  105. do_spi_byte(rbspi, spi_ioc, tx_buf[i]);
  106. if (!rx_buf)
  107. continue;
  108. rx_buf[i] = rb4xx_read(rbspi, AR71XX_SPI_REG_RDS);
  109. }
  110. spi_finalize_current_transfer(master);
  111. return 0;
  112. }
  113. static int rb4xx_spi_probe(struct platform_device *pdev)
  114. {
  115. struct spi_master *master;
  116. struct clk *ahb_clk;
  117. struct rb4xx_spi *rbspi;
  118. int err;
  119. void __iomem *spi_base;
  120. spi_base = devm_platform_ioremap_resource(pdev, 0);
  121. if (IS_ERR(spi_base))
  122. return PTR_ERR(spi_base);
  123. master = devm_spi_alloc_master(&pdev->dev, sizeof(*rbspi));
  124. if (!master)
  125. return -ENOMEM;
  126. ahb_clk = devm_clk_get(&pdev->dev, "ahb");
  127. if (IS_ERR(ahb_clk))
  128. return PTR_ERR(ahb_clk);
  129. master->dev.of_node = pdev->dev.of_node;
  130. master->bus_num = 0;
  131. master->num_chipselect = 3;
  132. master->mode_bits = SPI_TX_DUAL;
  133. master->bits_per_word_mask = SPI_BPW_MASK(8);
  134. master->flags = SPI_MASTER_MUST_TX;
  135. master->transfer_one = rb4xx_transfer_one;
  136. master->set_cs = rb4xx_set_cs;
  137. rbspi = spi_master_get_devdata(master);
  138. rbspi->base = spi_base;
  139. rbspi->clk = ahb_clk;
  140. platform_set_drvdata(pdev, rbspi);
  141. err = devm_spi_register_master(&pdev->dev, master);
  142. if (err) {
  143. dev_err(&pdev->dev, "failed to register SPI master\n");
  144. return err;
  145. }
  146. err = clk_prepare_enable(ahb_clk);
  147. if (err)
  148. return err;
  149. /* Enable SPI */
  150. rb4xx_write(rbspi, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
  151. return 0;
  152. }
  153. static int rb4xx_spi_remove(struct platform_device *pdev)
  154. {
  155. struct rb4xx_spi *rbspi = platform_get_drvdata(pdev);
  156. clk_disable_unprepare(rbspi->clk);
  157. return 0;
  158. }
  159. static const struct of_device_id rb4xx_spi_dt_match[] = {
  160. { .compatible = "mikrotik,rb4xx-spi" },
  161. { },
  162. };
  163. MODULE_DEVICE_TABLE(of, rb4xx_spi_dt_match);
  164. static struct platform_driver rb4xx_spi_drv = {
  165. .probe = rb4xx_spi_probe,
  166. .remove = rb4xx_spi_remove,
  167. .driver = {
  168. .name = "rb4xx-spi",
  169. .of_match_table = of_match_ptr(rb4xx_spi_dt_match),
  170. },
  171. };
  172. module_platform_driver(rb4xx_spi_drv);
  173. MODULE_DESCRIPTION("Mikrotik RB4xx SPI controller driver");
  174. MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
  175. MODULE_AUTHOR("Bert Vermeulen <bert@biot.com>");
  176. MODULE_LICENSE("GPL v2");