spi-ppc4xx.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * SPI_PPC4XX SPI controller driver.
  4. *
  5. * Copyright (C) 2007 Gary Jennejohn <garyj@denx.de>
  6. * Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
  7. * Copyright 2009 Harris Corporation, Steven A. Falco <sfalco@harris.com>
  8. *
  9. * Based in part on drivers/spi/spi_s3c24xx.c
  10. *
  11. * Copyright (c) 2006 Ben Dooks
  12. * Copyright (c) 2006 Simtec Electronics
  13. * Ben Dooks <ben@simtec.co.uk>
  14. */
  15. /*
  16. * The PPC4xx SPI controller has no FIFO so each sent/received byte will
  17. * generate an interrupt to the CPU. This can cause high CPU utilization.
  18. * This driver allows platforms to reduce the interrupt load on the CPU
  19. * during SPI transfers by setting max_speed_hz via the device tree.
  20. */
  21. #include <linux/module.h>
  22. #include <linux/sched.h>
  23. #include <linux/slab.h>
  24. #include <linux/errno.h>
  25. #include <linux/wait.h>
  26. #include <linux/of_address.h>
  27. #include <linux/of_irq.h>
  28. #include <linux/of_platform.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/delay.h>
  31. #include <linux/spi/spi.h>
  32. #include <linux/spi/spi_bitbang.h>
  33. #include <asm/io.h>
  34. #include <asm/dcr.h>
  35. #include <asm/dcr-regs.h>
  36. /* bits in mode register - bit 0 is MSb */
  37. /*
  38. * SPI_PPC4XX_MODE_SCP = 0 means "data latched on trailing edge of clock"
  39. * SPI_PPC4XX_MODE_SCP = 1 means "data latched on leading edge of clock"
  40. * Note: This is the inverse of CPHA.
  41. */
  42. #define SPI_PPC4XX_MODE_SCP (0x80 >> 3)
  43. /* SPI_PPC4XX_MODE_SPE = 1 means "port enabled" */
  44. #define SPI_PPC4XX_MODE_SPE (0x80 >> 4)
  45. /*
  46. * SPI_PPC4XX_MODE_RD = 0 means "MSB first" - this is the normal mode
  47. * SPI_PPC4XX_MODE_RD = 1 means "LSB first" - this is bit-reversed mode
  48. * Note: This is identical to SPI_LSB_FIRST.
  49. */
  50. #define SPI_PPC4XX_MODE_RD (0x80 >> 5)
  51. /*
  52. * SPI_PPC4XX_MODE_CI = 0 means "clock idles low"
  53. * SPI_PPC4XX_MODE_CI = 1 means "clock idles high"
  54. * Note: This is identical to CPOL.
  55. */
  56. #define SPI_PPC4XX_MODE_CI (0x80 >> 6)
  57. /*
  58. * SPI_PPC4XX_MODE_IL = 0 means "loopback disable"
  59. * SPI_PPC4XX_MODE_IL = 1 means "loopback enable"
  60. */
  61. #define SPI_PPC4XX_MODE_IL (0x80 >> 7)
  62. /* bits in control register */
  63. /* starts a transfer when set */
  64. #define SPI_PPC4XX_CR_STR (0x80 >> 7)
  65. /* bits in status register */
  66. /* port is busy with a transfer */
  67. #define SPI_PPC4XX_SR_BSY (0x80 >> 6)
  68. /* RxD ready */
  69. #define SPI_PPC4XX_SR_RBR (0x80 >> 7)
  70. /* clock settings (SCP and CI) for various SPI modes */
  71. #define SPI_CLK_MODE0 (SPI_PPC4XX_MODE_SCP | 0)
  72. #define SPI_CLK_MODE1 (0 | 0)
  73. #define SPI_CLK_MODE2 (SPI_PPC4XX_MODE_SCP | SPI_PPC4XX_MODE_CI)
  74. #define SPI_CLK_MODE3 (0 | SPI_PPC4XX_MODE_CI)
  75. #define DRIVER_NAME "spi_ppc4xx_of"
  76. struct spi_ppc4xx_regs {
  77. u8 mode;
  78. u8 rxd;
  79. u8 txd;
  80. u8 cr;
  81. u8 sr;
  82. u8 dummy;
  83. /*
  84. * Clock divisor modulus register
  85. * This uses the following formula:
  86. * SCPClkOut = OPBCLK/(4(CDM + 1))
  87. * or
  88. * CDM = (OPBCLK/4*SCPClkOut) - 1
  89. * bit 0 is the MSb!
  90. */
  91. u8 cdm;
  92. };
  93. /* SPI Controller driver's private data. */
  94. struct ppc4xx_spi {
  95. /* bitbang has to be first */
  96. struct spi_bitbang bitbang;
  97. struct completion done;
  98. u64 mapbase;
  99. u64 mapsize;
  100. int irqnum;
  101. /* need this to set the SPI clock */
  102. unsigned int opb_freq;
  103. /* for transfers */
  104. int len;
  105. int count;
  106. /* data buffers */
  107. const unsigned char *tx;
  108. unsigned char *rx;
  109. struct spi_ppc4xx_regs __iomem *regs; /* pointer to the registers */
  110. struct spi_master *master;
  111. struct device *dev;
  112. };
  113. /* need this so we can set the clock in the chipselect routine */
  114. struct spi_ppc4xx_cs {
  115. u8 mode;
  116. };
  117. static int spi_ppc4xx_txrx(struct spi_device *spi, struct spi_transfer *t)
  118. {
  119. struct ppc4xx_spi *hw;
  120. u8 data;
  121. dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
  122. t->tx_buf, t->rx_buf, t->len);
  123. hw = spi_master_get_devdata(spi->master);
  124. hw->tx = t->tx_buf;
  125. hw->rx = t->rx_buf;
  126. hw->len = t->len;
  127. hw->count = 0;
  128. /* send the first byte */
  129. data = hw->tx ? hw->tx[0] : 0;
  130. out_8(&hw->regs->txd, data);
  131. out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR);
  132. wait_for_completion(&hw->done);
  133. return hw->count;
  134. }
  135. static int spi_ppc4xx_setupxfer(struct spi_device *spi, struct spi_transfer *t)
  136. {
  137. struct ppc4xx_spi *hw = spi_master_get_devdata(spi->master);
  138. struct spi_ppc4xx_cs *cs = spi->controller_state;
  139. int scr;
  140. u8 cdm = 0;
  141. u32 speed;
  142. u8 bits_per_word;
  143. /* Start with the generic configuration for this device. */
  144. bits_per_word = spi->bits_per_word;
  145. speed = spi->max_speed_hz;
  146. /*
  147. * Modify the configuration if the transfer overrides it. Do not allow
  148. * the transfer to overwrite the generic configuration with zeros.
  149. */
  150. if (t) {
  151. if (t->bits_per_word)
  152. bits_per_word = t->bits_per_word;
  153. if (t->speed_hz)
  154. speed = min(t->speed_hz, spi->max_speed_hz);
  155. }
  156. if (!speed || (speed > spi->max_speed_hz)) {
  157. dev_err(&spi->dev, "invalid speed_hz (%d)\n", speed);
  158. return -EINVAL;
  159. }
  160. /* Write new configuration */
  161. out_8(&hw->regs->mode, cs->mode);
  162. /* Set the clock */
  163. /* opb_freq was already divided by 4 */
  164. scr = (hw->opb_freq / speed) - 1;
  165. if (scr > 0)
  166. cdm = min(scr, 0xff);
  167. dev_dbg(&spi->dev, "setting pre-scaler to %d (hz %d)\n", cdm, speed);
  168. if (in_8(&hw->regs->cdm) != cdm)
  169. out_8(&hw->regs->cdm, cdm);
  170. mutex_lock(&hw->bitbang.lock);
  171. if (!hw->bitbang.busy) {
  172. hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
  173. /* Need to ndelay here? */
  174. }
  175. mutex_unlock(&hw->bitbang.lock);
  176. return 0;
  177. }
  178. static int spi_ppc4xx_setup(struct spi_device *spi)
  179. {
  180. struct spi_ppc4xx_cs *cs = spi->controller_state;
  181. if (!spi->max_speed_hz) {
  182. dev_err(&spi->dev, "invalid max_speed_hz (must be non-zero)\n");
  183. return -EINVAL;
  184. }
  185. if (cs == NULL) {
  186. cs = kzalloc(sizeof *cs, GFP_KERNEL);
  187. if (!cs)
  188. return -ENOMEM;
  189. spi->controller_state = cs;
  190. }
  191. /*
  192. * We set all bits of the SPI0_MODE register, so,
  193. * no need to read-modify-write
  194. */
  195. cs->mode = SPI_PPC4XX_MODE_SPE;
  196. switch (spi->mode & (SPI_CPHA | SPI_CPOL)) {
  197. case SPI_MODE_0:
  198. cs->mode |= SPI_CLK_MODE0;
  199. break;
  200. case SPI_MODE_1:
  201. cs->mode |= SPI_CLK_MODE1;
  202. break;
  203. case SPI_MODE_2:
  204. cs->mode |= SPI_CLK_MODE2;
  205. break;
  206. case SPI_MODE_3:
  207. cs->mode |= SPI_CLK_MODE3;
  208. break;
  209. }
  210. if (spi->mode & SPI_LSB_FIRST)
  211. cs->mode |= SPI_PPC4XX_MODE_RD;
  212. return 0;
  213. }
  214. static irqreturn_t spi_ppc4xx_int(int irq, void *dev_id)
  215. {
  216. struct ppc4xx_spi *hw;
  217. u8 status;
  218. u8 data;
  219. unsigned int count;
  220. hw = (struct ppc4xx_spi *)dev_id;
  221. status = in_8(&hw->regs->sr);
  222. if (!status)
  223. return IRQ_NONE;
  224. /*
  225. * BSY de-asserts one cycle after the transfer is complete. The
  226. * interrupt is asserted after the transfer is complete. The exact
  227. * relationship is not documented, hence this code.
  228. */
  229. if (unlikely(status & SPI_PPC4XX_SR_BSY)) {
  230. u8 lstatus;
  231. int cnt = 0;
  232. dev_dbg(hw->dev, "got interrupt but spi still busy?\n");
  233. do {
  234. ndelay(10);
  235. lstatus = in_8(&hw->regs->sr);
  236. } while (++cnt < 100 && lstatus & SPI_PPC4XX_SR_BSY);
  237. if (cnt >= 100) {
  238. dev_err(hw->dev, "busywait: too many loops!\n");
  239. complete(&hw->done);
  240. return IRQ_HANDLED;
  241. } else {
  242. /* status is always 1 (RBR) here */
  243. status = in_8(&hw->regs->sr);
  244. dev_dbg(hw->dev, "loops %d status %x\n", cnt, status);
  245. }
  246. }
  247. count = hw->count;
  248. hw->count++;
  249. /* RBR triggered this interrupt. Therefore, data must be ready. */
  250. data = in_8(&hw->regs->rxd);
  251. if (hw->rx)
  252. hw->rx[count] = data;
  253. count++;
  254. if (count < hw->len) {
  255. data = hw->tx ? hw->tx[count] : 0;
  256. out_8(&hw->regs->txd, data);
  257. out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR);
  258. } else {
  259. complete(&hw->done);
  260. }
  261. return IRQ_HANDLED;
  262. }
  263. static void spi_ppc4xx_cleanup(struct spi_device *spi)
  264. {
  265. kfree(spi->controller_state);
  266. }
  267. static void spi_ppc4xx_enable(struct ppc4xx_spi *hw)
  268. {
  269. /*
  270. * On all 4xx PPC's the SPI bus is shared/multiplexed with
  271. * the 2nd I2C bus. We need to enable the the SPI bus before
  272. * using it.
  273. */
  274. /* need to clear bit 14 to enable SPC */
  275. dcri_clrset(SDR0, SDR0_PFC1, 0x80000000 >> 14, 0);
  276. }
  277. /*
  278. * platform_device layer stuff...
  279. */
  280. static int spi_ppc4xx_of_probe(struct platform_device *op)
  281. {
  282. struct ppc4xx_spi *hw;
  283. struct spi_master *master;
  284. struct spi_bitbang *bbp;
  285. struct resource resource;
  286. struct device_node *np = op->dev.of_node;
  287. struct device *dev = &op->dev;
  288. struct device_node *opbnp;
  289. int ret;
  290. const unsigned int *clk;
  291. master = spi_alloc_master(dev, sizeof *hw);
  292. if (master == NULL)
  293. return -ENOMEM;
  294. master->dev.of_node = np;
  295. platform_set_drvdata(op, master);
  296. hw = spi_master_get_devdata(master);
  297. hw->master = master;
  298. hw->dev = dev;
  299. init_completion(&hw->done);
  300. /* Setup the state for the bitbang driver */
  301. bbp = &hw->bitbang;
  302. bbp->master = hw->master;
  303. bbp->setup_transfer = spi_ppc4xx_setupxfer;
  304. bbp->txrx_bufs = spi_ppc4xx_txrx;
  305. bbp->use_dma = 0;
  306. bbp->master->setup = spi_ppc4xx_setup;
  307. bbp->master->cleanup = spi_ppc4xx_cleanup;
  308. bbp->master->bits_per_word_mask = SPI_BPW_MASK(8);
  309. bbp->master->use_gpio_descriptors = true;
  310. /*
  311. * The SPI core will count the number of GPIO descriptors to figure
  312. * out the number of chip selects available on the platform.
  313. */
  314. bbp->master->num_chipselect = 0;
  315. /* the spi->mode bits understood by this driver: */
  316. bbp->master->mode_bits =
  317. SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST;
  318. /* Get the clock for the OPB */
  319. opbnp = of_find_compatible_node(NULL, NULL, "ibm,opb");
  320. if (opbnp == NULL) {
  321. dev_err(dev, "OPB: cannot find node\n");
  322. ret = -ENODEV;
  323. goto free_master;
  324. }
  325. /* Get the clock (Hz) for the OPB */
  326. clk = of_get_property(opbnp, "clock-frequency", NULL);
  327. if (clk == NULL) {
  328. dev_err(dev, "OPB: no clock-frequency property set\n");
  329. of_node_put(opbnp);
  330. ret = -ENODEV;
  331. goto free_master;
  332. }
  333. hw->opb_freq = *clk;
  334. hw->opb_freq >>= 2;
  335. of_node_put(opbnp);
  336. ret = of_address_to_resource(np, 0, &resource);
  337. if (ret) {
  338. dev_err(dev, "error while parsing device node resource\n");
  339. goto free_master;
  340. }
  341. hw->mapbase = resource.start;
  342. hw->mapsize = resource_size(&resource);
  343. /* Sanity check */
  344. if (hw->mapsize < sizeof(struct spi_ppc4xx_regs)) {
  345. dev_err(dev, "too small to map registers\n");
  346. ret = -EINVAL;
  347. goto free_master;
  348. }
  349. /* Request IRQ */
  350. hw->irqnum = irq_of_parse_and_map(np, 0);
  351. ret = request_irq(hw->irqnum, spi_ppc4xx_int,
  352. 0, "spi_ppc4xx_of", (void *)hw);
  353. if (ret) {
  354. dev_err(dev, "unable to allocate interrupt\n");
  355. goto free_master;
  356. }
  357. if (!request_mem_region(hw->mapbase, hw->mapsize, DRIVER_NAME)) {
  358. dev_err(dev, "resource unavailable\n");
  359. ret = -EBUSY;
  360. goto request_mem_error;
  361. }
  362. hw->regs = ioremap(hw->mapbase, sizeof(struct spi_ppc4xx_regs));
  363. if (!hw->regs) {
  364. dev_err(dev, "unable to memory map registers\n");
  365. ret = -ENXIO;
  366. goto map_io_error;
  367. }
  368. spi_ppc4xx_enable(hw);
  369. /* Finally register our spi controller */
  370. dev->dma_mask = 0;
  371. ret = spi_bitbang_start(bbp);
  372. if (ret) {
  373. dev_err(dev, "failed to register SPI master\n");
  374. goto unmap_regs;
  375. }
  376. dev_info(dev, "driver initialized\n");
  377. return 0;
  378. unmap_regs:
  379. iounmap(hw->regs);
  380. map_io_error:
  381. release_mem_region(hw->mapbase, hw->mapsize);
  382. request_mem_error:
  383. free_irq(hw->irqnum, hw);
  384. free_master:
  385. spi_master_put(master);
  386. dev_err(dev, "initialization failed\n");
  387. return ret;
  388. }
  389. static int spi_ppc4xx_of_remove(struct platform_device *op)
  390. {
  391. struct spi_master *master = platform_get_drvdata(op);
  392. struct ppc4xx_spi *hw = spi_master_get_devdata(master);
  393. spi_bitbang_stop(&hw->bitbang);
  394. release_mem_region(hw->mapbase, hw->mapsize);
  395. free_irq(hw->irqnum, hw);
  396. iounmap(hw->regs);
  397. spi_master_put(master);
  398. return 0;
  399. }
  400. static const struct of_device_id spi_ppc4xx_of_match[] = {
  401. { .compatible = "ibm,ppc4xx-spi", },
  402. {},
  403. };
  404. MODULE_DEVICE_TABLE(of, spi_ppc4xx_of_match);
  405. static struct platform_driver spi_ppc4xx_of_driver = {
  406. .probe = spi_ppc4xx_of_probe,
  407. .remove = spi_ppc4xx_of_remove,
  408. .driver = {
  409. .name = DRIVER_NAME,
  410. .of_match_table = spi_ppc4xx_of_match,
  411. },
  412. };
  413. module_platform_driver(spi_ppc4xx_of_driver);
  414. MODULE_AUTHOR("Gary Jennejohn & Stefan Roese");
  415. MODULE_DESCRIPTION("Simple PPC4xx SPI Driver");
  416. MODULE_LICENSE("GPL");