spi-mt65xx.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015 MediaTek Inc.
  4. * Author: Leilk Liu <leilk.liu@mediatek.com>
  5. */
  6. #include <linux/clk.h>
  7. #include <linux/device.h>
  8. #include <linux/err.h>
  9. #include <linux/interrupt.h>
  10. #include <linux/io.h>
  11. #include <linux/ioport.h>
  12. #include <linux/module.h>
  13. #include <linux/of.h>
  14. #include <linux/of_gpio.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/platform_data/spi-mt65xx.h>
  17. #include <linux/pm_runtime.h>
  18. #include <linux/spi/spi.h>
  19. #include <linux/dma-mapping.h>
  20. #define SPI_CFG0_REG 0x0000
  21. #define SPI_CFG1_REG 0x0004
  22. #define SPI_TX_SRC_REG 0x0008
  23. #define SPI_RX_DST_REG 0x000c
  24. #define SPI_TX_DATA_REG 0x0010
  25. #define SPI_RX_DATA_REG 0x0014
  26. #define SPI_CMD_REG 0x0018
  27. #define SPI_STATUS0_REG 0x001c
  28. #define SPI_PAD_SEL_REG 0x0024
  29. #define SPI_CFG2_REG 0x0028
  30. #define SPI_TX_SRC_REG_64 0x002c
  31. #define SPI_RX_DST_REG_64 0x0030
  32. #define SPI_CFG0_SCK_HIGH_OFFSET 0
  33. #define SPI_CFG0_SCK_LOW_OFFSET 8
  34. #define SPI_CFG0_CS_HOLD_OFFSET 16
  35. #define SPI_CFG0_CS_SETUP_OFFSET 24
  36. #define SPI_ADJUST_CFG0_CS_HOLD_OFFSET 0
  37. #define SPI_ADJUST_CFG0_CS_SETUP_OFFSET 16
  38. #define SPI_CFG1_CS_IDLE_OFFSET 0
  39. #define SPI_CFG1_PACKET_LOOP_OFFSET 8
  40. #define SPI_CFG1_PACKET_LENGTH_OFFSET 16
  41. #define SPI_CFG1_GET_TICK_DLY_OFFSET 30
  42. #define SPI_CFG1_CS_IDLE_MASK 0xff
  43. #define SPI_CFG1_PACKET_LOOP_MASK 0xff00
  44. #define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000
  45. #define SPI_CFG2_SCK_HIGH_OFFSET 0
  46. #define SPI_CFG2_SCK_LOW_OFFSET 16
  47. #define SPI_CMD_ACT BIT(0)
  48. #define SPI_CMD_RESUME BIT(1)
  49. #define SPI_CMD_RST BIT(2)
  50. #define SPI_CMD_PAUSE_EN BIT(4)
  51. #define SPI_CMD_DEASSERT BIT(5)
  52. #define SPI_CMD_SAMPLE_SEL BIT(6)
  53. #define SPI_CMD_CS_POL BIT(7)
  54. #define SPI_CMD_CPHA BIT(8)
  55. #define SPI_CMD_CPOL BIT(9)
  56. #define SPI_CMD_RX_DMA BIT(10)
  57. #define SPI_CMD_TX_DMA BIT(11)
  58. #define SPI_CMD_TXMSBF BIT(12)
  59. #define SPI_CMD_RXMSBF BIT(13)
  60. #define SPI_CMD_RX_ENDIAN BIT(14)
  61. #define SPI_CMD_TX_ENDIAN BIT(15)
  62. #define SPI_CMD_FINISH_IE BIT(16)
  63. #define SPI_CMD_PAUSE_IE BIT(17)
  64. #define MT8173_SPI_MAX_PAD_SEL 3
  65. #define MTK_SPI_PAUSE_INT_STATUS 0x2
  66. #define MTK_SPI_IDLE 0
  67. #define MTK_SPI_PAUSED 1
  68. #define MTK_SPI_MAX_FIFO_SIZE 32U
  69. #define MTK_SPI_PACKET_SIZE 1024
  70. #define MTK_SPI_32BITS_MASK (0xffffffff)
  71. #define DMA_ADDR_EXT_BITS (36)
  72. #define DMA_ADDR_DEF_BITS (32)
  73. struct mtk_spi_compatible {
  74. bool need_pad_sel;
  75. /* Must explicitly send dummy Tx bytes to do Rx only transfer */
  76. bool must_tx;
  77. /* some IC design adjust cfg register to enhance time accuracy */
  78. bool enhance_timing;
  79. /* some IC support DMA addr extension */
  80. bool dma_ext;
  81. };
  82. struct mtk_spi {
  83. void __iomem *base;
  84. u32 state;
  85. int pad_num;
  86. u32 *pad_sel;
  87. struct clk *parent_clk, *sel_clk, *spi_clk;
  88. struct spi_transfer *cur_transfer;
  89. u32 xfer_len;
  90. u32 num_xfered;
  91. struct scatterlist *tx_sgl, *rx_sgl;
  92. u32 tx_sgl_len, rx_sgl_len;
  93. const struct mtk_spi_compatible *dev_comp;
  94. };
  95. static const struct mtk_spi_compatible mtk_common_compat;
  96. static const struct mtk_spi_compatible mt2712_compat = {
  97. .must_tx = true,
  98. };
  99. static const struct mtk_spi_compatible mt6765_compat = {
  100. .need_pad_sel = true,
  101. .must_tx = true,
  102. .enhance_timing = true,
  103. .dma_ext = true,
  104. };
  105. static const struct mtk_spi_compatible mt7622_compat = {
  106. .must_tx = true,
  107. .enhance_timing = true,
  108. };
  109. static const struct mtk_spi_compatible mt8173_compat = {
  110. .need_pad_sel = true,
  111. .must_tx = true,
  112. };
  113. static const struct mtk_spi_compatible mt8183_compat = {
  114. .need_pad_sel = true,
  115. .must_tx = true,
  116. .enhance_timing = true,
  117. };
  118. /*
  119. * A piece of default chip info unless the platform
  120. * supplies it.
  121. */
  122. static const struct mtk_chip_config mtk_default_chip_info = {
  123. .sample_sel = 0,
  124. };
  125. static const struct of_device_id mtk_spi_of_match[] = {
  126. { .compatible = "mediatek,mt2701-spi",
  127. .data = (void *)&mtk_common_compat,
  128. },
  129. { .compatible = "mediatek,mt2712-spi",
  130. .data = (void *)&mt2712_compat,
  131. },
  132. { .compatible = "mediatek,mt6589-spi",
  133. .data = (void *)&mtk_common_compat,
  134. },
  135. { .compatible = "mediatek,mt6765-spi",
  136. .data = (void *)&mt6765_compat,
  137. },
  138. { .compatible = "mediatek,mt7622-spi",
  139. .data = (void *)&mt7622_compat,
  140. },
  141. { .compatible = "mediatek,mt7629-spi",
  142. .data = (void *)&mt7622_compat,
  143. },
  144. { .compatible = "mediatek,mt8135-spi",
  145. .data = (void *)&mtk_common_compat,
  146. },
  147. { .compatible = "mediatek,mt8173-spi",
  148. .data = (void *)&mt8173_compat,
  149. },
  150. { .compatible = "mediatek,mt8183-spi",
  151. .data = (void *)&mt8183_compat,
  152. },
  153. { .compatible = "mediatek,mt8192-spi",
  154. .data = (void *)&mt6765_compat,
  155. },
  156. {}
  157. };
  158. MODULE_DEVICE_TABLE(of, mtk_spi_of_match);
  159. static void mtk_spi_reset(struct mtk_spi *mdata)
  160. {
  161. u32 reg_val;
  162. /* set the software reset bit in SPI_CMD_REG. */
  163. reg_val = readl(mdata->base + SPI_CMD_REG);
  164. reg_val |= SPI_CMD_RST;
  165. writel(reg_val, mdata->base + SPI_CMD_REG);
  166. reg_val = readl(mdata->base + SPI_CMD_REG);
  167. reg_val &= ~SPI_CMD_RST;
  168. writel(reg_val, mdata->base + SPI_CMD_REG);
  169. }
  170. static int mtk_spi_prepare_message(struct spi_master *master,
  171. struct spi_message *msg)
  172. {
  173. u16 cpha, cpol;
  174. u32 reg_val;
  175. struct spi_device *spi = msg->spi;
  176. struct mtk_chip_config *chip_config = spi->controller_data;
  177. struct mtk_spi *mdata = spi_master_get_devdata(master);
  178. cpha = spi->mode & SPI_CPHA ? 1 : 0;
  179. cpol = spi->mode & SPI_CPOL ? 1 : 0;
  180. reg_val = readl(mdata->base + SPI_CMD_REG);
  181. if (cpha)
  182. reg_val |= SPI_CMD_CPHA;
  183. else
  184. reg_val &= ~SPI_CMD_CPHA;
  185. if (cpol)
  186. reg_val |= SPI_CMD_CPOL;
  187. else
  188. reg_val &= ~SPI_CMD_CPOL;
  189. /* set the mlsbx and mlsbtx */
  190. if (spi->mode & SPI_LSB_FIRST) {
  191. reg_val &= ~SPI_CMD_TXMSBF;
  192. reg_val &= ~SPI_CMD_RXMSBF;
  193. } else {
  194. reg_val |= SPI_CMD_TXMSBF;
  195. reg_val |= SPI_CMD_RXMSBF;
  196. }
  197. /* set the tx/rx endian */
  198. #ifdef __LITTLE_ENDIAN
  199. reg_val &= ~SPI_CMD_TX_ENDIAN;
  200. reg_val &= ~SPI_CMD_RX_ENDIAN;
  201. #else
  202. reg_val |= SPI_CMD_TX_ENDIAN;
  203. reg_val |= SPI_CMD_RX_ENDIAN;
  204. #endif
  205. if (mdata->dev_comp->enhance_timing) {
  206. /* set CS polarity */
  207. if (spi->mode & SPI_CS_HIGH)
  208. reg_val |= SPI_CMD_CS_POL;
  209. else
  210. reg_val &= ~SPI_CMD_CS_POL;
  211. if (chip_config->sample_sel)
  212. reg_val |= SPI_CMD_SAMPLE_SEL;
  213. else
  214. reg_val &= ~SPI_CMD_SAMPLE_SEL;
  215. }
  216. /* set finish and pause interrupt always enable */
  217. reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE;
  218. /* disable dma mode */
  219. reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA);
  220. /* disable deassert mode */
  221. reg_val &= ~SPI_CMD_DEASSERT;
  222. writel(reg_val, mdata->base + SPI_CMD_REG);
  223. /* pad select */
  224. if (mdata->dev_comp->need_pad_sel)
  225. writel(mdata->pad_sel[spi->chip_select],
  226. mdata->base + SPI_PAD_SEL_REG);
  227. return 0;
  228. }
  229. static void mtk_spi_set_cs(struct spi_device *spi, bool enable)
  230. {
  231. u32 reg_val;
  232. struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
  233. if (spi->mode & SPI_CS_HIGH)
  234. enable = !enable;
  235. reg_val = readl(mdata->base + SPI_CMD_REG);
  236. if (!enable) {
  237. reg_val |= SPI_CMD_PAUSE_EN;
  238. writel(reg_val, mdata->base + SPI_CMD_REG);
  239. } else {
  240. reg_val &= ~SPI_CMD_PAUSE_EN;
  241. writel(reg_val, mdata->base + SPI_CMD_REG);
  242. mdata->state = MTK_SPI_IDLE;
  243. mtk_spi_reset(mdata);
  244. }
  245. }
  246. static void mtk_spi_prepare_transfer(struct spi_master *master,
  247. struct spi_transfer *xfer)
  248. {
  249. u32 spi_clk_hz, div, sck_time, cs_time, reg_val;
  250. struct mtk_spi *mdata = spi_master_get_devdata(master);
  251. spi_clk_hz = clk_get_rate(mdata->spi_clk);
  252. if (xfer->speed_hz < spi_clk_hz / 2)
  253. div = DIV_ROUND_UP(spi_clk_hz, xfer->speed_hz);
  254. else
  255. div = 1;
  256. sck_time = (div + 1) / 2;
  257. cs_time = sck_time * 2;
  258. if (mdata->dev_comp->enhance_timing) {
  259. reg_val = (((sck_time - 1) & 0xffff)
  260. << SPI_CFG2_SCK_HIGH_OFFSET);
  261. reg_val |= (((sck_time - 1) & 0xffff)
  262. << SPI_CFG2_SCK_LOW_OFFSET);
  263. writel(reg_val, mdata->base + SPI_CFG2_REG);
  264. reg_val = (((cs_time - 1) & 0xffff)
  265. << SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
  266. reg_val |= (((cs_time - 1) & 0xffff)
  267. << SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
  268. writel(reg_val, mdata->base + SPI_CFG0_REG);
  269. } else {
  270. reg_val = (((sck_time - 1) & 0xff)
  271. << SPI_CFG0_SCK_HIGH_OFFSET);
  272. reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);
  273. reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
  274. reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET);
  275. writel(reg_val, mdata->base + SPI_CFG0_REG);
  276. }
  277. reg_val = readl(mdata->base + SPI_CFG1_REG);
  278. reg_val &= ~SPI_CFG1_CS_IDLE_MASK;
  279. reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET);
  280. writel(reg_val, mdata->base + SPI_CFG1_REG);
  281. }
  282. static void mtk_spi_setup_packet(struct spi_master *master)
  283. {
  284. u32 packet_size, packet_loop, reg_val;
  285. struct mtk_spi *mdata = spi_master_get_devdata(master);
  286. packet_size = min_t(u32, mdata->xfer_len, MTK_SPI_PACKET_SIZE);
  287. packet_loop = mdata->xfer_len / packet_size;
  288. reg_val = readl(mdata->base + SPI_CFG1_REG);
  289. reg_val &= ~(SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK);
  290. reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET;
  291. reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET;
  292. writel(reg_val, mdata->base + SPI_CFG1_REG);
  293. }
  294. static void mtk_spi_enable_transfer(struct spi_master *master)
  295. {
  296. u32 cmd;
  297. struct mtk_spi *mdata = spi_master_get_devdata(master);
  298. cmd = readl(mdata->base + SPI_CMD_REG);
  299. if (mdata->state == MTK_SPI_IDLE)
  300. cmd |= SPI_CMD_ACT;
  301. else
  302. cmd |= SPI_CMD_RESUME;
  303. writel(cmd, mdata->base + SPI_CMD_REG);
  304. }
  305. static int mtk_spi_get_mult_delta(u32 xfer_len)
  306. {
  307. u32 mult_delta;
  308. if (xfer_len > MTK_SPI_PACKET_SIZE)
  309. mult_delta = xfer_len % MTK_SPI_PACKET_SIZE;
  310. else
  311. mult_delta = 0;
  312. return mult_delta;
  313. }
  314. static void mtk_spi_update_mdata_len(struct spi_master *master)
  315. {
  316. int mult_delta;
  317. struct mtk_spi *mdata = spi_master_get_devdata(master);
  318. if (mdata->tx_sgl_len && mdata->rx_sgl_len) {
  319. if (mdata->tx_sgl_len > mdata->rx_sgl_len) {
  320. mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
  321. mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
  322. mdata->rx_sgl_len = mult_delta;
  323. mdata->tx_sgl_len -= mdata->xfer_len;
  324. } else {
  325. mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
  326. mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
  327. mdata->tx_sgl_len = mult_delta;
  328. mdata->rx_sgl_len -= mdata->xfer_len;
  329. }
  330. } else if (mdata->tx_sgl_len) {
  331. mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
  332. mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
  333. mdata->tx_sgl_len = mult_delta;
  334. } else if (mdata->rx_sgl_len) {
  335. mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
  336. mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
  337. mdata->rx_sgl_len = mult_delta;
  338. }
  339. }
  340. static void mtk_spi_setup_dma_addr(struct spi_master *master,
  341. struct spi_transfer *xfer)
  342. {
  343. struct mtk_spi *mdata = spi_master_get_devdata(master);
  344. if (mdata->tx_sgl) {
  345. writel((u32)(xfer->tx_dma & MTK_SPI_32BITS_MASK),
  346. mdata->base + SPI_TX_SRC_REG);
  347. #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
  348. if (mdata->dev_comp->dma_ext)
  349. writel((u32)(xfer->tx_dma >> 32),
  350. mdata->base + SPI_TX_SRC_REG_64);
  351. #endif
  352. }
  353. if (mdata->rx_sgl) {
  354. writel((u32)(xfer->rx_dma & MTK_SPI_32BITS_MASK),
  355. mdata->base + SPI_RX_DST_REG);
  356. #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
  357. if (mdata->dev_comp->dma_ext)
  358. writel((u32)(xfer->rx_dma >> 32),
  359. mdata->base + SPI_RX_DST_REG_64);
  360. #endif
  361. }
  362. }
  363. static int mtk_spi_fifo_transfer(struct spi_master *master,
  364. struct spi_device *spi,
  365. struct spi_transfer *xfer)
  366. {
  367. int cnt, remainder;
  368. u32 reg_val;
  369. struct mtk_spi *mdata = spi_master_get_devdata(master);
  370. mdata->cur_transfer = xfer;
  371. mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, xfer->len);
  372. mdata->num_xfered = 0;
  373. mtk_spi_prepare_transfer(master, xfer);
  374. mtk_spi_setup_packet(master);
  375. if (xfer->tx_buf) {
  376. cnt = xfer->len / 4;
  377. iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt);
  378. remainder = xfer->len % 4;
  379. if (remainder > 0) {
  380. reg_val = 0;
  381. memcpy(&reg_val, xfer->tx_buf + (cnt * 4), remainder);
  382. writel(reg_val, mdata->base + SPI_TX_DATA_REG);
  383. }
  384. }
  385. mtk_spi_enable_transfer(master);
  386. return 1;
  387. }
  388. static int mtk_spi_dma_transfer(struct spi_master *master,
  389. struct spi_device *spi,
  390. struct spi_transfer *xfer)
  391. {
  392. int cmd;
  393. struct mtk_spi *mdata = spi_master_get_devdata(master);
  394. mdata->tx_sgl = NULL;
  395. mdata->rx_sgl = NULL;
  396. mdata->tx_sgl_len = 0;
  397. mdata->rx_sgl_len = 0;
  398. mdata->cur_transfer = xfer;
  399. mdata->num_xfered = 0;
  400. mtk_spi_prepare_transfer(master, xfer);
  401. cmd = readl(mdata->base + SPI_CMD_REG);
  402. if (xfer->tx_buf)
  403. cmd |= SPI_CMD_TX_DMA;
  404. if (xfer->rx_buf)
  405. cmd |= SPI_CMD_RX_DMA;
  406. writel(cmd, mdata->base + SPI_CMD_REG);
  407. if (xfer->tx_buf)
  408. mdata->tx_sgl = xfer->tx_sg.sgl;
  409. if (xfer->rx_buf)
  410. mdata->rx_sgl = xfer->rx_sg.sgl;
  411. if (mdata->tx_sgl) {
  412. xfer->tx_dma = sg_dma_address(mdata->tx_sgl);
  413. mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
  414. }
  415. if (mdata->rx_sgl) {
  416. xfer->rx_dma = sg_dma_address(mdata->rx_sgl);
  417. mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
  418. }
  419. mtk_spi_update_mdata_len(master);
  420. mtk_spi_setup_packet(master);
  421. mtk_spi_setup_dma_addr(master, xfer);
  422. mtk_spi_enable_transfer(master);
  423. return 1;
  424. }
  425. static int mtk_spi_transfer_one(struct spi_master *master,
  426. struct spi_device *spi,
  427. struct spi_transfer *xfer)
  428. {
  429. if (master->can_dma(master, spi, xfer))
  430. return mtk_spi_dma_transfer(master, spi, xfer);
  431. else
  432. return mtk_spi_fifo_transfer(master, spi, xfer);
  433. }
  434. static bool mtk_spi_can_dma(struct spi_master *master,
  435. struct spi_device *spi,
  436. struct spi_transfer *xfer)
  437. {
  438. /* Buffers for DMA transactions must be 4-byte aligned */
  439. return (xfer->len > MTK_SPI_MAX_FIFO_SIZE &&
  440. (unsigned long)xfer->tx_buf % 4 == 0 &&
  441. (unsigned long)xfer->rx_buf % 4 == 0);
  442. }
  443. static int mtk_spi_setup(struct spi_device *spi)
  444. {
  445. struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
  446. if (!spi->controller_data)
  447. spi->controller_data = (void *)&mtk_default_chip_info;
  448. if (mdata->dev_comp->need_pad_sel && gpio_is_valid(spi->cs_gpio))
  449. gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
  450. return 0;
  451. }
  452. static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id)
  453. {
  454. u32 cmd, reg_val, cnt, remainder, len;
  455. struct spi_master *master = dev_id;
  456. struct mtk_spi *mdata = spi_master_get_devdata(master);
  457. struct spi_transfer *trans = mdata->cur_transfer;
  458. reg_val = readl(mdata->base + SPI_STATUS0_REG);
  459. if (reg_val & MTK_SPI_PAUSE_INT_STATUS)
  460. mdata->state = MTK_SPI_PAUSED;
  461. else
  462. mdata->state = MTK_SPI_IDLE;
  463. if (!master->can_dma(master, NULL, trans)) {
  464. if (trans->rx_buf) {
  465. cnt = mdata->xfer_len / 4;
  466. ioread32_rep(mdata->base + SPI_RX_DATA_REG,
  467. trans->rx_buf + mdata->num_xfered, cnt);
  468. remainder = mdata->xfer_len % 4;
  469. if (remainder > 0) {
  470. reg_val = readl(mdata->base + SPI_RX_DATA_REG);
  471. memcpy(trans->rx_buf +
  472. mdata->num_xfered +
  473. (cnt * 4),
  474. &reg_val,
  475. remainder);
  476. }
  477. }
  478. mdata->num_xfered += mdata->xfer_len;
  479. if (mdata->num_xfered == trans->len) {
  480. spi_finalize_current_transfer(master);
  481. return IRQ_HANDLED;
  482. }
  483. len = trans->len - mdata->num_xfered;
  484. mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, len);
  485. mtk_spi_setup_packet(master);
  486. cnt = mdata->xfer_len / 4;
  487. iowrite32_rep(mdata->base + SPI_TX_DATA_REG,
  488. trans->tx_buf + mdata->num_xfered, cnt);
  489. remainder = mdata->xfer_len % 4;
  490. if (remainder > 0) {
  491. reg_val = 0;
  492. memcpy(&reg_val,
  493. trans->tx_buf + (cnt * 4) + mdata->num_xfered,
  494. remainder);
  495. writel(reg_val, mdata->base + SPI_TX_DATA_REG);
  496. }
  497. mtk_spi_enable_transfer(master);
  498. return IRQ_HANDLED;
  499. }
  500. if (mdata->tx_sgl)
  501. trans->tx_dma += mdata->xfer_len;
  502. if (mdata->rx_sgl)
  503. trans->rx_dma += mdata->xfer_len;
  504. if (mdata->tx_sgl && (mdata->tx_sgl_len == 0)) {
  505. mdata->tx_sgl = sg_next(mdata->tx_sgl);
  506. if (mdata->tx_sgl) {
  507. trans->tx_dma = sg_dma_address(mdata->tx_sgl);
  508. mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
  509. }
  510. }
  511. if (mdata->rx_sgl && (mdata->rx_sgl_len == 0)) {
  512. mdata->rx_sgl = sg_next(mdata->rx_sgl);
  513. if (mdata->rx_sgl) {
  514. trans->rx_dma = sg_dma_address(mdata->rx_sgl);
  515. mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
  516. }
  517. }
  518. if (!mdata->tx_sgl && !mdata->rx_sgl) {
  519. /* spi disable dma */
  520. cmd = readl(mdata->base + SPI_CMD_REG);
  521. cmd &= ~SPI_CMD_TX_DMA;
  522. cmd &= ~SPI_CMD_RX_DMA;
  523. writel(cmd, mdata->base + SPI_CMD_REG);
  524. spi_finalize_current_transfer(master);
  525. return IRQ_HANDLED;
  526. }
  527. mtk_spi_update_mdata_len(master);
  528. mtk_spi_setup_packet(master);
  529. mtk_spi_setup_dma_addr(master, trans);
  530. mtk_spi_enable_transfer(master);
  531. return IRQ_HANDLED;
  532. }
  533. static int mtk_spi_probe(struct platform_device *pdev)
  534. {
  535. struct spi_master *master;
  536. struct mtk_spi *mdata;
  537. const struct of_device_id *of_id;
  538. int i, irq, ret, addr_bits;
  539. master = spi_alloc_master(&pdev->dev, sizeof(*mdata));
  540. if (!master) {
  541. dev_err(&pdev->dev, "failed to alloc spi master\n");
  542. return -ENOMEM;
  543. }
  544. master->auto_runtime_pm = true;
  545. master->dev.of_node = pdev->dev.of_node;
  546. master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
  547. master->set_cs = mtk_spi_set_cs;
  548. master->prepare_message = mtk_spi_prepare_message;
  549. master->transfer_one = mtk_spi_transfer_one;
  550. master->can_dma = mtk_spi_can_dma;
  551. master->setup = mtk_spi_setup;
  552. of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node);
  553. if (!of_id) {
  554. dev_err(&pdev->dev, "failed to probe of_node\n");
  555. ret = -EINVAL;
  556. goto err_put_master;
  557. }
  558. mdata = spi_master_get_devdata(master);
  559. mdata->dev_comp = of_id->data;
  560. if (mdata->dev_comp->enhance_timing)
  561. master->mode_bits |= SPI_CS_HIGH;
  562. if (mdata->dev_comp->must_tx)
  563. master->flags = SPI_MASTER_MUST_TX;
  564. if (mdata->dev_comp->need_pad_sel) {
  565. mdata->pad_num = of_property_count_u32_elems(
  566. pdev->dev.of_node,
  567. "mediatek,pad-select");
  568. if (mdata->pad_num < 0) {
  569. dev_err(&pdev->dev,
  570. "No 'mediatek,pad-select' property\n");
  571. ret = -EINVAL;
  572. goto err_put_master;
  573. }
  574. mdata->pad_sel = devm_kmalloc_array(&pdev->dev, mdata->pad_num,
  575. sizeof(u32), GFP_KERNEL);
  576. if (!mdata->pad_sel) {
  577. ret = -ENOMEM;
  578. goto err_put_master;
  579. }
  580. for (i = 0; i < mdata->pad_num; i++) {
  581. of_property_read_u32_index(pdev->dev.of_node,
  582. "mediatek,pad-select",
  583. i, &mdata->pad_sel[i]);
  584. if (mdata->pad_sel[i] > MT8173_SPI_MAX_PAD_SEL) {
  585. dev_err(&pdev->dev, "wrong pad-sel[%d]: %u\n",
  586. i, mdata->pad_sel[i]);
  587. ret = -EINVAL;
  588. goto err_put_master;
  589. }
  590. }
  591. }
  592. platform_set_drvdata(pdev, master);
  593. mdata->base = devm_platform_ioremap_resource(pdev, 0);
  594. if (IS_ERR(mdata->base)) {
  595. ret = PTR_ERR(mdata->base);
  596. goto err_put_master;
  597. }
  598. irq = platform_get_irq(pdev, 0);
  599. if (irq < 0) {
  600. ret = irq;
  601. goto err_put_master;
  602. }
  603. if (!pdev->dev.dma_mask)
  604. pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
  605. ret = devm_request_irq(&pdev->dev, irq, mtk_spi_interrupt,
  606. IRQF_TRIGGER_NONE, dev_name(&pdev->dev), master);
  607. if (ret) {
  608. dev_err(&pdev->dev, "failed to register irq (%d)\n", ret);
  609. goto err_put_master;
  610. }
  611. mdata->parent_clk = devm_clk_get(&pdev->dev, "parent-clk");
  612. if (IS_ERR(mdata->parent_clk)) {
  613. ret = PTR_ERR(mdata->parent_clk);
  614. dev_err(&pdev->dev, "failed to get parent-clk: %d\n", ret);
  615. goto err_put_master;
  616. }
  617. mdata->sel_clk = devm_clk_get(&pdev->dev, "sel-clk");
  618. if (IS_ERR(mdata->sel_clk)) {
  619. ret = PTR_ERR(mdata->sel_clk);
  620. dev_err(&pdev->dev, "failed to get sel-clk: %d\n", ret);
  621. goto err_put_master;
  622. }
  623. mdata->spi_clk = devm_clk_get(&pdev->dev, "spi-clk");
  624. if (IS_ERR(mdata->spi_clk)) {
  625. ret = PTR_ERR(mdata->spi_clk);
  626. dev_err(&pdev->dev, "failed to get spi-clk: %d\n", ret);
  627. goto err_put_master;
  628. }
  629. ret = clk_prepare_enable(mdata->spi_clk);
  630. if (ret < 0) {
  631. dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret);
  632. goto err_put_master;
  633. }
  634. ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk);
  635. if (ret < 0) {
  636. dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret);
  637. clk_disable_unprepare(mdata->spi_clk);
  638. goto err_put_master;
  639. }
  640. clk_disable_unprepare(mdata->spi_clk);
  641. pm_runtime_enable(&pdev->dev);
  642. ret = devm_spi_register_master(&pdev->dev, master);
  643. if (ret) {
  644. dev_err(&pdev->dev, "failed to register master (%d)\n", ret);
  645. goto err_disable_runtime_pm;
  646. }
  647. if (mdata->dev_comp->need_pad_sel) {
  648. if (mdata->pad_num != master->num_chipselect) {
  649. dev_err(&pdev->dev,
  650. "pad_num does not match num_chipselect(%d != %d)\n",
  651. mdata->pad_num, master->num_chipselect);
  652. ret = -EINVAL;
  653. goto err_disable_runtime_pm;
  654. }
  655. if (!master->cs_gpios && master->num_chipselect > 1) {
  656. dev_err(&pdev->dev,
  657. "cs_gpios not specified and num_chipselect > 1\n");
  658. ret = -EINVAL;
  659. goto err_disable_runtime_pm;
  660. }
  661. if (master->cs_gpios) {
  662. for (i = 0; i < master->num_chipselect; i++) {
  663. ret = devm_gpio_request(&pdev->dev,
  664. master->cs_gpios[i],
  665. dev_name(&pdev->dev));
  666. if (ret) {
  667. dev_err(&pdev->dev,
  668. "can't get CS GPIO %i\n", i);
  669. goto err_disable_runtime_pm;
  670. }
  671. }
  672. }
  673. }
  674. if (mdata->dev_comp->dma_ext)
  675. addr_bits = DMA_ADDR_EXT_BITS;
  676. else
  677. addr_bits = DMA_ADDR_DEF_BITS;
  678. ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(addr_bits));
  679. if (ret)
  680. dev_notice(&pdev->dev, "SPI dma_set_mask(%d) failed, ret:%d\n",
  681. addr_bits, ret);
  682. return 0;
  683. err_disable_runtime_pm:
  684. pm_runtime_disable(&pdev->dev);
  685. err_put_master:
  686. spi_master_put(master);
  687. return ret;
  688. }
  689. static int mtk_spi_remove(struct platform_device *pdev)
  690. {
  691. struct spi_master *master = platform_get_drvdata(pdev);
  692. struct mtk_spi *mdata = spi_master_get_devdata(master);
  693. pm_runtime_disable(&pdev->dev);
  694. mtk_spi_reset(mdata);
  695. return 0;
  696. }
  697. #ifdef CONFIG_PM_SLEEP
  698. static int mtk_spi_suspend(struct device *dev)
  699. {
  700. int ret;
  701. struct spi_master *master = dev_get_drvdata(dev);
  702. struct mtk_spi *mdata = spi_master_get_devdata(master);
  703. ret = spi_master_suspend(master);
  704. if (ret)
  705. return ret;
  706. if (!pm_runtime_suspended(dev))
  707. clk_disable_unprepare(mdata->spi_clk);
  708. return ret;
  709. }
  710. static int mtk_spi_resume(struct device *dev)
  711. {
  712. int ret;
  713. struct spi_master *master = dev_get_drvdata(dev);
  714. struct mtk_spi *mdata = spi_master_get_devdata(master);
  715. if (!pm_runtime_suspended(dev)) {
  716. ret = clk_prepare_enable(mdata->spi_clk);
  717. if (ret < 0) {
  718. dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
  719. return ret;
  720. }
  721. }
  722. ret = spi_master_resume(master);
  723. if (ret < 0)
  724. clk_disable_unprepare(mdata->spi_clk);
  725. return ret;
  726. }
  727. #endif /* CONFIG_PM_SLEEP */
  728. #ifdef CONFIG_PM
  729. static int mtk_spi_runtime_suspend(struct device *dev)
  730. {
  731. struct spi_master *master = dev_get_drvdata(dev);
  732. struct mtk_spi *mdata = spi_master_get_devdata(master);
  733. clk_disable_unprepare(mdata->spi_clk);
  734. return 0;
  735. }
  736. static int mtk_spi_runtime_resume(struct device *dev)
  737. {
  738. struct spi_master *master = dev_get_drvdata(dev);
  739. struct mtk_spi *mdata = spi_master_get_devdata(master);
  740. int ret;
  741. ret = clk_prepare_enable(mdata->spi_clk);
  742. if (ret < 0) {
  743. dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
  744. return ret;
  745. }
  746. return 0;
  747. }
  748. #endif /* CONFIG_PM */
  749. static const struct dev_pm_ops mtk_spi_pm = {
  750. SET_SYSTEM_SLEEP_PM_OPS(mtk_spi_suspend, mtk_spi_resume)
  751. SET_RUNTIME_PM_OPS(mtk_spi_runtime_suspend,
  752. mtk_spi_runtime_resume, NULL)
  753. };
  754. static struct platform_driver mtk_spi_driver = {
  755. .driver = {
  756. .name = "mtk-spi",
  757. .pm = &mtk_spi_pm,
  758. .of_match_table = mtk_spi_of_match,
  759. },
  760. .probe = mtk_spi_probe,
  761. .remove = mtk_spi_remove,
  762. };
  763. module_platform_driver(mtk_spi_driver);
  764. MODULE_DESCRIPTION("MTK SPI Controller driver");
  765. MODULE_AUTHOR("Leilk Liu <leilk.liu@mediatek.com>");
  766. MODULE_LICENSE("GPL v2");
  767. MODULE_ALIAS("platform:mtk-spi");