spi-mpc52xx.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * MPC52xx SPI bus driver.
  4. *
  5. * Copyright (C) 2008 Secret Lab Technologies Ltd.
  6. *
  7. * This is the driver for the MPC5200's dedicated SPI controller.
  8. *
  9. * Note: this driver does not support the MPC5200 PSC in SPI mode. For
  10. * that driver see drivers/spi/mpc52xx_psc_spi.c
  11. */
  12. #include <linux/module.h>
  13. #include <linux/errno.h>
  14. #include <linux/of_platform.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/delay.h>
  17. #include <linux/spi/spi.h>
  18. #include <linux/io.h>
  19. #include <linux/of_gpio.h>
  20. #include <linux/slab.h>
  21. #include <asm/time.h>
  22. #include <asm/mpc52xx.h>
  23. MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>");
  24. MODULE_DESCRIPTION("MPC52xx SPI (non-PSC) Driver");
  25. MODULE_LICENSE("GPL");
  26. /* Register offsets */
  27. #define SPI_CTRL1 0x00
  28. #define SPI_CTRL1_SPIE (1 << 7)
  29. #define SPI_CTRL1_SPE (1 << 6)
  30. #define SPI_CTRL1_MSTR (1 << 4)
  31. #define SPI_CTRL1_CPOL (1 << 3)
  32. #define SPI_CTRL1_CPHA (1 << 2)
  33. #define SPI_CTRL1_SSOE (1 << 1)
  34. #define SPI_CTRL1_LSBFE (1 << 0)
  35. #define SPI_CTRL2 0x01
  36. #define SPI_BRR 0x04
  37. #define SPI_STATUS 0x05
  38. #define SPI_STATUS_SPIF (1 << 7)
  39. #define SPI_STATUS_WCOL (1 << 6)
  40. #define SPI_STATUS_MODF (1 << 4)
  41. #define SPI_DATA 0x09
  42. #define SPI_PORTDATA 0x0d
  43. #define SPI_DATADIR 0x10
  44. /* FSM state return values */
  45. #define FSM_STOP 0 /* Nothing more for the state machine to */
  46. /* do. If something interesting happens */
  47. /* then an IRQ will be received */
  48. #define FSM_POLL 1 /* need to poll for completion, an IRQ is */
  49. /* not expected */
  50. #define FSM_CONTINUE 2 /* Keep iterating the state machine */
  51. /* Driver internal data */
  52. struct mpc52xx_spi {
  53. struct spi_master *master;
  54. void __iomem *regs;
  55. int irq0; /* MODF irq */
  56. int irq1; /* SPIF irq */
  57. unsigned int ipb_freq;
  58. /* Statistics; not used now, but will be reintroduced for debugfs */
  59. int msg_count;
  60. int wcol_count;
  61. int wcol_ticks;
  62. u32 wcol_tx_timestamp;
  63. int modf_count;
  64. int byte_count;
  65. struct list_head queue; /* queue of pending messages */
  66. spinlock_t lock;
  67. struct work_struct work;
  68. /* Details of current transfer (length, and buffer pointers) */
  69. struct spi_message *message; /* current message */
  70. struct spi_transfer *transfer; /* current transfer */
  71. int (*state)(int irq, struct mpc52xx_spi *ms, u8 status, u8 data);
  72. int len;
  73. int timestamp;
  74. u8 *rx_buf;
  75. const u8 *tx_buf;
  76. int cs_change;
  77. int gpio_cs_count;
  78. unsigned int *gpio_cs;
  79. };
  80. /*
  81. * CS control function
  82. */
  83. static void mpc52xx_spi_chipsel(struct mpc52xx_spi *ms, int value)
  84. {
  85. int cs;
  86. if (ms->gpio_cs_count > 0) {
  87. cs = ms->message->spi->chip_select;
  88. gpio_set_value(ms->gpio_cs[cs], value ? 0 : 1);
  89. } else
  90. out_8(ms->regs + SPI_PORTDATA, value ? 0 : 0x08);
  91. }
  92. /*
  93. * Start a new transfer. This is called both by the idle state
  94. * for the first transfer in a message, and by the wait state when the
  95. * previous transfer in a message is complete.
  96. */
  97. static void mpc52xx_spi_start_transfer(struct mpc52xx_spi *ms)
  98. {
  99. ms->rx_buf = ms->transfer->rx_buf;
  100. ms->tx_buf = ms->transfer->tx_buf;
  101. ms->len = ms->transfer->len;
  102. /* Activate the chip select */
  103. if (ms->cs_change)
  104. mpc52xx_spi_chipsel(ms, 1);
  105. ms->cs_change = ms->transfer->cs_change;
  106. /* Write out the first byte */
  107. ms->wcol_tx_timestamp = get_tbl();
  108. if (ms->tx_buf)
  109. out_8(ms->regs + SPI_DATA, *ms->tx_buf++);
  110. else
  111. out_8(ms->regs + SPI_DATA, 0);
  112. }
  113. /* Forward declaration of state handlers */
  114. static int mpc52xx_spi_fsmstate_transfer(int irq, struct mpc52xx_spi *ms,
  115. u8 status, u8 data);
  116. static int mpc52xx_spi_fsmstate_wait(int irq, struct mpc52xx_spi *ms,
  117. u8 status, u8 data);
  118. /*
  119. * IDLE state
  120. *
  121. * No transfers are in progress; if another transfer is pending then retrieve
  122. * it and kick it off. Otherwise, stop processing the state machine
  123. */
  124. static int
  125. mpc52xx_spi_fsmstate_idle(int irq, struct mpc52xx_spi *ms, u8 status, u8 data)
  126. {
  127. struct spi_device *spi;
  128. int spr, sppr;
  129. u8 ctrl1;
  130. if (status && (irq != NO_IRQ))
  131. dev_err(&ms->master->dev, "spurious irq, status=0x%.2x\n",
  132. status);
  133. /* Check if there is another transfer waiting. */
  134. if (list_empty(&ms->queue))
  135. return FSM_STOP;
  136. /* get the head of the queue */
  137. ms->message = list_first_entry(&ms->queue, struct spi_message, queue);
  138. list_del_init(&ms->message->queue);
  139. /* Setup the controller parameters */
  140. ctrl1 = SPI_CTRL1_SPIE | SPI_CTRL1_SPE | SPI_CTRL1_MSTR;
  141. spi = ms->message->spi;
  142. if (spi->mode & SPI_CPHA)
  143. ctrl1 |= SPI_CTRL1_CPHA;
  144. if (spi->mode & SPI_CPOL)
  145. ctrl1 |= SPI_CTRL1_CPOL;
  146. if (spi->mode & SPI_LSB_FIRST)
  147. ctrl1 |= SPI_CTRL1_LSBFE;
  148. out_8(ms->regs + SPI_CTRL1, ctrl1);
  149. /* Setup the controller speed */
  150. /* minimum divider is '2'. Also, add '1' to force rounding the
  151. * divider up. */
  152. sppr = ((ms->ipb_freq / ms->message->spi->max_speed_hz) + 1) >> 1;
  153. spr = 0;
  154. if (sppr < 1)
  155. sppr = 1;
  156. while (((sppr - 1) & ~0x7) != 0) {
  157. sppr = (sppr + 1) >> 1; /* add '1' to force rounding up */
  158. spr++;
  159. }
  160. sppr--; /* sppr quantity in register is offset by 1 */
  161. if (spr > 7) {
  162. /* Don't overrun limits of SPI baudrate register */
  163. spr = 7;
  164. sppr = 7;
  165. }
  166. out_8(ms->regs + SPI_BRR, sppr << 4 | spr); /* Set speed */
  167. ms->cs_change = 1;
  168. ms->transfer = container_of(ms->message->transfers.next,
  169. struct spi_transfer, transfer_list);
  170. mpc52xx_spi_start_transfer(ms);
  171. ms->state = mpc52xx_spi_fsmstate_transfer;
  172. return FSM_CONTINUE;
  173. }
  174. /*
  175. * TRANSFER state
  176. *
  177. * In the middle of a transfer. If the SPI core has completed processing
  178. * a byte, then read out the received data and write out the next byte
  179. * (unless this transfer is finished; in which case go on to the wait
  180. * state)
  181. */
  182. static int mpc52xx_spi_fsmstate_transfer(int irq, struct mpc52xx_spi *ms,
  183. u8 status, u8 data)
  184. {
  185. if (!status)
  186. return ms->irq0 ? FSM_STOP : FSM_POLL;
  187. if (status & SPI_STATUS_WCOL) {
  188. /* The SPI controller is stoopid. At slower speeds, it may
  189. * raise the SPIF flag before the state machine is actually
  190. * finished, which causes a collision (internal to the state
  191. * machine only). The manual recommends inserting a delay
  192. * between receiving the interrupt and sending the next byte,
  193. * but it can also be worked around simply by retrying the
  194. * transfer which is what we do here. */
  195. ms->wcol_count++;
  196. ms->wcol_ticks += get_tbl() - ms->wcol_tx_timestamp;
  197. ms->wcol_tx_timestamp = get_tbl();
  198. data = 0;
  199. if (ms->tx_buf)
  200. data = *(ms->tx_buf - 1);
  201. out_8(ms->regs + SPI_DATA, data); /* try again */
  202. return FSM_CONTINUE;
  203. } else if (status & SPI_STATUS_MODF) {
  204. ms->modf_count++;
  205. dev_err(&ms->master->dev, "mode fault\n");
  206. mpc52xx_spi_chipsel(ms, 0);
  207. ms->message->status = -EIO;
  208. if (ms->message->complete)
  209. ms->message->complete(ms->message->context);
  210. ms->state = mpc52xx_spi_fsmstate_idle;
  211. return FSM_CONTINUE;
  212. }
  213. /* Read data out of the spi device */
  214. ms->byte_count++;
  215. if (ms->rx_buf)
  216. *ms->rx_buf++ = data;
  217. /* Is the transfer complete? */
  218. ms->len--;
  219. if (ms->len == 0) {
  220. ms->timestamp = get_tbl();
  221. ms->timestamp += ms->transfer->delay_usecs * tb_ticks_per_usec;
  222. ms->state = mpc52xx_spi_fsmstate_wait;
  223. return FSM_CONTINUE;
  224. }
  225. /* Write out the next byte */
  226. ms->wcol_tx_timestamp = get_tbl();
  227. if (ms->tx_buf)
  228. out_8(ms->regs + SPI_DATA, *ms->tx_buf++);
  229. else
  230. out_8(ms->regs + SPI_DATA, 0);
  231. return FSM_CONTINUE;
  232. }
  233. /*
  234. * WAIT state
  235. *
  236. * A transfer has completed; need to wait for the delay period to complete
  237. * before starting the next transfer
  238. */
  239. static int
  240. mpc52xx_spi_fsmstate_wait(int irq, struct mpc52xx_spi *ms, u8 status, u8 data)
  241. {
  242. if (status && irq)
  243. dev_err(&ms->master->dev, "spurious irq, status=0x%.2x\n",
  244. status);
  245. if (((int)get_tbl()) - ms->timestamp < 0)
  246. return FSM_POLL;
  247. ms->message->actual_length += ms->transfer->len;
  248. /* Check if there is another transfer in this message. If there
  249. * aren't then deactivate CS, notify sender, and drop back to idle
  250. * to start the next message. */
  251. if (ms->transfer->transfer_list.next == &ms->message->transfers) {
  252. ms->msg_count++;
  253. mpc52xx_spi_chipsel(ms, 0);
  254. ms->message->status = 0;
  255. if (ms->message->complete)
  256. ms->message->complete(ms->message->context);
  257. ms->state = mpc52xx_spi_fsmstate_idle;
  258. return FSM_CONTINUE;
  259. }
  260. /* There is another transfer; kick it off */
  261. if (ms->cs_change)
  262. mpc52xx_spi_chipsel(ms, 0);
  263. ms->transfer = container_of(ms->transfer->transfer_list.next,
  264. struct spi_transfer, transfer_list);
  265. mpc52xx_spi_start_transfer(ms);
  266. ms->state = mpc52xx_spi_fsmstate_transfer;
  267. return FSM_CONTINUE;
  268. }
  269. /**
  270. * mpc52xx_spi_fsm_process - Finite State Machine iteration function
  271. * @irq: irq number that triggered the FSM or 0 for polling
  272. * @ms: pointer to mpc52xx_spi driver data
  273. */
  274. static void mpc52xx_spi_fsm_process(int irq, struct mpc52xx_spi *ms)
  275. {
  276. int rc = FSM_CONTINUE;
  277. u8 status, data;
  278. while (rc == FSM_CONTINUE) {
  279. /* Interrupt cleared by read of STATUS followed by
  280. * read of DATA registers */
  281. status = in_8(ms->regs + SPI_STATUS);
  282. data = in_8(ms->regs + SPI_DATA);
  283. rc = ms->state(irq, ms, status, data);
  284. }
  285. if (rc == FSM_POLL)
  286. schedule_work(&ms->work);
  287. }
  288. /**
  289. * mpc52xx_spi_irq - IRQ handler
  290. */
  291. static irqreturn_t mpc52xx_spi_irq(int irq, void *_ms)
  292. {
  293. struct mpc52xx_spi *ms = _ms;
  294. spin_lock(&ms->lock);
  295. mpc52xx_spi_fsm_process(irq, ms);
  296. spin_unlock(&ms->lock);
  297. return IRQ_HANDLED;
  298. }
  299. /**
  300. * mpc52xx_spi_wq - Workqueue function for polling the state machine
  301. */
  302. static void mpc52xx_spi_wq(struct work_struct *work)
  303. {
  304. struct mpc52xx_spi *ms = container_of(work, struct mpc52xx_spi, work);
  305. unsigned long flags;
  306. spin_lock_irqsave(&ms->lock, flags);
  307. mpc52xx_spi_fsm_process(0, ms);
  308. spin_unlock_irqrestore(&ms->lock, flags);
  309. }
  310. /*
  311. * spi_master ops
  312. */
  313. static int mpc52xx_spi_transfer(struct spi_device *spi, struct spi_message *m)
  314. {
  315. struct mpc52xx_spi *ms = spi_master_get_devdata(spi->master);
  316. unsigned long flags;
  317. m->actual_length = 0;
  318. m->status = -EINPROGRESS;
  319. spin_lock_irqsave(&ms->lock, flags);
  320. list_add_tail(&m->queue, &ms->queue);
  321. spin_unlock_irqrestore(&ms->lock, flags);
  322. schedule_work(&ms->work);
  323. return 0;
  324. }
  325. /*
  326. * OF Platform Bus Binding
  327. */
  328. static int mpc52xx_spi_probe(struct platform_device *op)
  329. {
  330. struct spi_master *master;
  331. struct mpc52xx_spi *ms;
  332. void __iomem *regs;
  333. u8 ctrl1;
  334. int rc, i = 0;
  335. int gpio_cs;
  336. /* MMIO registers */
  337. dev_dbg(&op->dev, "probing mpc5200 SPI device\n");
  338. regs = of_iomap(op->dev.of_node, 0);
  339. if (!regs)
  340. return -ENODEV;
  341. /* initialize the device */
  342. ctrl1 = SPI_CTRL1_SPIE | SPI_CTRL1_SPE | SPI_CTRL1_MSTR;
  343. out_8(regs + SPI_CTRL1, ctrl1);
  344. out_8(regs + SPI_CTRL2, 0x0);
  345. out_8(regs + SPI_DATADIR, 0xe); /* Set output pins */
  346. out_8(regs + SPI_PORTDATA, 0x8); /* Deassert /SS signal */
  347. /* Clear the status register and re-read it to check for a MODF
  348. * failure. This driver cannot currently handle multiple masters
  349. * on the SPI bus. This fault will also occur if the SPI signals
  350. * are not connected to any pins (port_config setting) */
  351. in_8(regs + SPI_STATUS);
  352. out_8(regs + SPI_CTRL1, ctrl1);
  353. in_8(regs + SPI_DATA);
  354. if (in_8(regs + SPI_STATUS) & SPI_STATUS_MODF) {
  355. dev_err(&op->dev, "mode fault; is port_config correct?\n");
  356. rc = -EIO;
  357. goto err_init;
  358. }
  359. dev_dbg(&op->dev, "allocating spi_master struct\n");
  360. master = spi_alloc_master(&op->dev, sizeof *ms);
  361. if (!master) {
  362. rc = -ENOMEM;
  363. goto err_alloc;
  364. }
  365. master->transfer = mpc52xx_spi_transfer;
  366. master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
  367. master->bits_per_word_mask = SPI_BPW_MASK(8);
  368. master->dev.of_node = op->dev.of_node;
  369. platform_set_drvdata(op, master);
  370. ms = spi_master_get_devdata(master);
  371. ms->master = master;
  372. ms->regs = regs;
  373. ms->irq0 = irq_of_parse_and_map(op->dev.of_node, 0);
  374. ms->irq1 = irq_of_parse_and_map(op->dev.of_node, 1);
  375. ms->state = mpc52xx_spi_fsmstate_idle;
  376. ms->ipb_freq = mpc5xxx_get_bus_frequency(op->dev.of_node);
  377. ms->gpio_cs_count = of_gpio_count(op->dev.of_node);
  378. if (ms->gpio_cs_count > 0) {
  379. master->num_chipselect = ms->gpio_cs_count;
  380. ms->gpio_cs = kmalloc_array(ms->gpio_cs_count,
  381. sizeof(*ms->gpio_cs),
  382. GFP_KERNEL);
  383. if (!ms->gpio_cs) {
  384. rc = -ENOMEM;
  385. goto err_alloc_gpio;
  386. }
  387. for (i = 0; i < ms->gpio_cs_count; i++) {
  388. gpio_cs = of_get_gpio(op->dev.of_node, i);
  389. if (!gpio_is_valid(gpio_cs)) {
  390. dev_err(&op->dev,
  391. "could not parse the gpio field in oftree\n");
  392. rc = -ENODEV;
  393. goto err_gpio;
  394. }
  395. rc = gpio_request(gpio_cs, dev_name(&op->dev));
  396. if (rc) {
  397. dev_err(&op->dev,
  398. "can't request spi cs gpio #%d on gpio line %d\n",
  399. i, gpio_cs);
  400. goto err_gpio;
  401. }
  402. gpio_direction_output(gpio_cs, 1);
  403. ms->gpio_cs[i] = gpio_cs;
  404. }
  405. }
  406. spin_lock_init(&ms->lock);
  407. INIT_LIST_HEAD(&ms->queue);
  408. INIT_WORK(&ms->work, mpc52xx_spi_wq);
  409. /* Decide if interrupts can be used */
  410. if (ms->irq0 && ms->irq1) {
  411. rc = request_irq(ms->irq0, mpc52xx_spi_irq, 0,
  412. "mpc5200-spi-modf", ms);
  413. rc |= request_irq(ms->irq1, mpc52xx_spi_irq, 0,
  414. "mpc5200-spi-spif", ms);
  415. if (rc) {
  416. free_irq(ms->irq0, ms);
  417. free_irq(ms->irq1, ms);
  418. ms->irq0 = ms->irq1 = 0;
  419. }
  420. } else {
  421. /* operate in polled mode */
  422. ms->irq0 = ms->irq1 = 0;
  423. }
  424. if (!ms->irq0)
  425. dev_info(&op->dev, "using polled mode\n");
  426. dev_dbg(&op->dev, "registering spi_master struct\n");
  427. rc = spi_register_master(master);
  428. if (rc)
  429. goto err_register;
  430. dev_info(&ms->master->dev, "registered MPC5200 SPI bus\n");
  431. return rc;
  432. err_register:
  433. dev_err(&ms->master->dev, "initialization failed\n");
  434. err_gpio:
  435. while (i-- > 0)
  436. gpio_free(ms->gpio_cs[i]);
  437. kfree(ms->gpio_cs);
  438. err_alloc_gpio:
  439. spi_master_put(master);
  440. err_alloc:
  441. err_init:
  442. iounmap(regs);
  443. return rc;
  444. }
  445. static int mpc52xx_spi_remove(struct platform_device *op)
  446. {
  447. struct spi_master *master = spi_master_get(platform_get_drvdata(op));
  448. struct mpc52xx_spi *ms = spi_master_get_devdata(master);
  449. int i;
  450. free_irq(ms->irq0, ms);
  451. free_irq(ms->irq1, ms);
  452. for (i = 0; i < ms->gpio_cs_count; i++)
  453. gpio_free(ms->gpio_cs[i]);
  454. kfree(ms->gpio_cs);
  455. spi_unregister_master(master);
  456. iounmap(ms->regs);
  457. spi_master_put(master);
  458. return 0;
  459. }
  460. static const struct of_device_id mpc52xx_spi_match[] = {
  461. { .compatible = "fsl,mpc5200-spi", },
  462. {}
  463. };
  464. MODULE_DEVICE_TABLE(of, mpc52xx_spi_match);
  465. static struct platform_driver mpc52xx_spi_of_driver = {
  466. .driver = {
  467. .name = "mpc52xx-spi",
  468. .of_match_table = mpc52xx_spi_match,
  469. },
  470. .probe = mpc52xx_spi_probe,
  471. .remove = mpc52xx_spi_remove,
  472. };
  473. module_platform_driver(mpc52xx_spi_of_driver);