spi-img-spfi.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * IMG SPFI controller driver
  4. *
  5. * Copyright (C) 2007,2008,2013 Imagination Technologies Ltd.
  6. * Copyright (C) 2014 Google, Inc.
  7. */
  8. #include <linux/clk.h>
  9. #include <linux/delay.h>
  10. #include <linux/dmaengine.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/io.h>
  13. #include <linux/irq.h>
  14. #include <linux/module.h>
  15. #include <linux/of.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/pm_runtime.h>
  18. #include <linux/scatterlist.h>
  19. #include <linux/slab.h>
  20. #include <linux/spi/spi.h>
  21. #include <linux/spinlock.h>
  22. #define SPFI_DEVICE_PARAMETER(x) (0x00 + 0x4 * (x))
  23. #define SPFI_DEVICE_PARAMETER_BITCLK_SHIFT 24
  24. #define SPFI_DEVICE_PARAMETER_BITCLK_MASK 0xff
  25. #define SPFI_DEVICE_PARAMETER_CSSETUP_SHIFT 16
  26. #define SPFI_DEVICE_PARAMETER_CSSETUP_MASK 0xff
  27. #define SPFI_DEVICE_PARAMETER_CSHOLD_SHIFT 8
  28. #define SPFI_DEVICE_PARAMETER_CSHOLD_MASK 0xff
  29. #define SPFI_DEVICE_PARAMETER_CSDELAY_SHIFT 0
  30. #define SPFI_DEVICE_PARAMETER_CSDELAY_MASK 0xff
  31. #define SPFI_CONTROL 0x14
  32. #define SPFI_CONTROL_CONTINUE BIT(12)
  33. #define SPFI_CONTROL_SOFT_RESET BIT(11)
  34. #define SPFI_CONTROL_SEND_DMA BIT(10)
  35. #define SPFI_CONTROL_GET_DMA BIT(9)
  36. #define SPFI_CONTROL_SE BIT(8)
  37. #define SPFI_CONTROL_TMODE_SHIFT 5
  38. #define SPFI_CONTROL_TMODE_MASK 0x7
  39. #define SPFI_CONTROL_TMODE_SINGLE 0
  40. #define SPFI_CONTROL_TMODE_DUAL 1
  41. #define SPFI_CONTROL_TMODE_QUAD 2
  42. #define SPFI_CONTROL_SPFI_EN BIT(0)
  43. #define SPFI_TRANSACTION 0x18
  44. #define SPFI_TRANSACTION_TSIZE_SHIFT 16
  45. #define SPFI_TRANSACTION_TSIZE_MASK 0xffff
  46. #define SPFI_PORT_STATE 0x1c
  47. #define SPFI_PORT_STATE_DEV_SEL_SHIFT 20
  48. #define SPFI_PORT_STATE_DEV_SEL_MASK 0x7
  49. #define SPFI_PORT_STATE_CK_POL(x) BIT(19 - (x))
  50. #define SPFI_PORT_STATE_CK_PHASE(x) BIT(14 - (x))
  51. #define SPFI_TX_32BIT_VALID_DATA 0x20
  52. #define SPFI_TX_8BIT_VALID_DATA 0x24
  53. #define SPFI_RX_32BIT_VALID_DATA 0x28
  54. #define SPFI_RX_8BIT_VALID_DATA 0x2c
  55. #define SPFI_INTERRUPT_STATUS 0x30
  56. #define SPFI_INTERRUPT_ENABLE 0x34
  57. #define SPFI_INTERRUPT_CLEAR 0x38
  58. #define SPFI_INTERRUPT_IACCESS BIT(12)
  59. #define SPFI_INTERRUPT_GDEX8BIT BIT(11)
  60. #define SPFI_INTERRUPT_ALLDONETRIG BIT(9)
  61. #define SPFI_INTERRUPT_GDFUL BIT(8)
  62. #define SPFI_INTERRUPT_GDHF BIT(7)
  63. #define SPFI_INTERRUPT_GDEX32BIT BIT(6)
  64. #define SPFI_INTERRUPT_GDTRIG BIT(5)
  65. #define SPFI_INTERRUPT_SDFUL BIT(3)
  66. #define SPFI_INTERRUPT_SDHF BIT(2)
  67. #define SPFI_INTERRUPT_SDE BIT(1)
  68. #define SPFI_INTERRUPT_SDTRIG BIT(0)
  69. /*
  70. * There are four parallel FIFOs of 16 bytes each. The word buffer
  71. * (*_32BIT_VALID_DATA) accesses all four FIFOs at once, resulting in an
  72. * effective FIFO size of 64 bytes. The byte buffer (*_8BIT_VALID_DATA)
  73. * accesses only a single FIFO, resulting in an effective FIFO size of
  74. * 16 bytes.
  75. */
  76. #define SPFI_32BIT_FIFO_SIZE 64
  77. #define SPFI_8BIT_FIFO_SIZE 16
  78. struct img_spfi {
  79. struct device *dev;
  80. struct spi_master *master;
  81. spinlock_t lock;
  82. void __iomem *regs;
  83. phys_addr_t phys;
  84. int irq;
  85. struct clk *spfi_clk;
  86. struct clk *sys_clk;
  87. struct dma_chan *rx_ch;
  88. struct dma_chan *tx_ch;
  89. bool tx_dma_busy;
  90. bool rx_dma_busy;
  91. };
  92. static inline u32 spfi_readl(struct img_spfi *spfi, u32 reg)
  93. {
  94. return readl(spfi->regs + reg);
  95. }
  96. static inline void spfi_writel(struct img_spfi *spfi, u32 val, u32 reg)
  97. {
  98. writel(val, spfi->regs + reg);
  99. }
  100. static inline void spfi_start(struct img_spfi *spfi)
  101. {
  102. u32 val;
  103. val = spfi_readl(spfi, SPFI_CONTROL);
  104. val |= SPFI_CONTROL_SPFI_EN;
  105. spfi_writel(spfi, val, SPFI_CONTROL);
  106. }
  107. static inline void spfi_reset(struct img_spfi *spfi)
  108. {
  109. spfi_writel(spfi, SPFI_CONTROL_SOFT_RESET, SPFI_CONTROL);
  110. spfi_writel(spfi, 0, SPFI_CONTROL);
  111. }
  112. static int spfi_wait_all_done(struct img_spfi *spfi)
  113. {
  114. unsigned long timeout = jiffies + msecs_to_jiffies(50);
  115. while (time_before(jiffies, timeout)) {
  116. u32 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
  117. if (status & SPFI_INTERRUPT_ALLDONETRIG) {
  118. spfi_writel(spfi, SPFI_INTERRUPT_ALLDONETRIG,
  119. SPFI_INTERRUPT_CLEAR);
  120. return 0;
  121. }
  122. cpu_relax();
  123. }
  124. dev_err(spfi->dev, "Timed out waiting for transaction to complete\n");
  125. spfi_reset(spfi);
  126. return -ETIMEDOUT;
  127. }
  128. static unsigned int spfi_pio_write32(struct img_spfi *spfi, const u32 *buf,
  129. unsigned int max)
  130. {
  131. unsigned int count = 0;
  132. u32 status;
  133. while (count < max / 4) {
  134. spfi_writel(spfi, SPFI_INTERRUPT_SDFUL, SPFI_INTERRUPT_CLEAR);
  135. status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
  136. if (status & SPFI_INTERRUPT_SDFUL)
  137. break;
  138. spfi_writel(spfi, buf[count], SPFI_TX_32BIT_VALID_DATA);
  139. count++;
  140. }
  141. return count * 4;
  142. }
  143. static unsigned int spfi_pio_write8(struct img_spfi *spfi, const u8 *buf,
  144. unsigned int max)
  145. {
  146. unsigned int count = 0;
  147. u32 status;
  148. while (count < max) {
  149. spfi_writel(spfi, SPFI_INTERRUPT_SDFUL, SPFI_INTERRUPT_CLEAR);
  150. status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
  151. if (status & SPFI_INTERRUPT_SDFUL)
  152. break;
  153. spfi_writel(spfi, buf[count], SPFI_TX_8BIT_VALID_DATA);
  154. count++;
  155. }
  156. return count;
  157. }
  158. static unsigned int spfi_pio_read32(struct img_spfi *spfi, u32 *buf,
  159. unsigned int max)
  160. {
  161. unsigned int count = 0;
  162. u32 status;
  163. while (count < max / 4) {
  164. spfi_writel(spfi, SPFI_INTERRUPT_GDEX32BIT,
  165. SPFI_INTERRUPT_CLEAR);
  166. status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
  167. if (!(status & SPFI_INTERRUPT_GDEX32BIT))
  168. break;
  169. buf[count] = spfi_readl(spfi, SPFI_RX_32BIT_VALID_DATA);
  170. count++;
  171. }
  172. return count * 4;
  173. }
  174. static unsigned int spfi_pio_read8(struct img_spfi *spfi, u8 *buf,
  175. unsigned int max)
  176. {
  177. unsigned int count = 0;
  178. u32 status;
  179. while (count < max) {
  180. spfi_writel(spfi, SPFI_INTERRUPT_GDEX8BIT,
  181. SPFI_INTERRUPT_CLEAR);
  182. status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
  183. if (!(status & SPFI_INTERRUPT_GDEX8BIT))
  184. break;
  185. buf[count] = spfi_readl(spfi, SPFI_RX_8BIT_VALID_DATA);
  186. count++;
  187. }
  188. return count;
  189. }
  190. static int img_spfi_start_pio(struct spi_master *master,
  191. struct spi_device *spi,
  192. struct spi_transfer *xfer)
  193. {
  194. struct img_spfi *spfi = spi_master_get_devdata(spi->master);
  195. unsigned int tx_bytes = 0, rx_bytes = 0;
  196. const void *tx_buf = xfer->tx_buf;
  197. void *rx_buf = xfer->rx_buf;
  198. unsigned long timeout;
  199. int ret;
  200. if (tx_buf)
  201. tx_bytes = xfer->len;
  202. if (rx_buf)
  203. rx_bytes = xfer->len;
  204. spfi_start(spfi);
  205. timeout = jiffies +
  206. msecs_to_jiffies(xfer->len * 8 * 1000 / xfer->speed_hz + 100);
  207. while ((tx_bytes > 0 || rx_bytes > 0) &&
  208. time_before(jiffies, timeout)) {
  209. unsigned int tx_count, rx_count;
  210. if (tx_bytes >= 4)
  211. tx_count = spfi_pio_write32(spfi, tx_buf, tx_bytes);
  212. else
  213. tx_count = spfi_pio_write8(spfi, tx_buf, tx_bytes);
  214. if (rx_bytes >= 4)
  215. rx_count = spfi_pio_read32(spfi, rx_buf, rx_bytes);
  216. else
  217. rx_count = spfi_pio_read8(spfi, rx_buf, rx_bytes);
  218. tx_buf += tx_count;
  219. rx_buf += rx_count;
  220. tx_bytes -= tx_count;
  221. rx_bytes -= rx_count;
  222. cpu_relax();
  223. }
  224. if (rx_bytes > 0 || tx_bytes > 0) {
  225. dev_err(spfi->dev, "PIO transfer timed out\n");
  226. return -ETIMEDOUT;
  227. }
  228. ret = spfi_wait_all_done(spfi);
  229. if (ret < 0)
  230. return ret;
  231. return 0;
  232. }
  233. static void img_spfi_dma_rx_cb(void *data)
  234. {
  235. struct img_spfi *spfi = data;
  236. unsigned long flags;
  237. spfi_wait_all_done(spfi);
  238. spin_lock_irqsave(&spfi->lock, flags);
  239. spfi->rx_dma_busy = false;
  240. if (!spfi->tx_dma_busy)
  241. spi_finalize_current_transfer(spfi->master);
  242. spin_unlock_irqrestore(&spfi->lock, flags);
  243. }
  244. static void img_spfi_dma_tx_cb(void *data)
  245. {
  246. struct img_spfi *spfi = data;
  247. unsigned long flags;
  248. spfi_wait_all_done(spfi);
  249. spin_lock_irqsave(&spfi->lock, flags);
  250. spfi->tx_dma_busy = false;
  251. if (!spfi->rx_dma_busy)
  252. spi_finalize_current_transfer(spfi->master);
  253. spin_unlock_irqrestore(&spfi->lock, flags);
  254. }
  255. static int img_spfi_start_dma(struct spi_master *master,
  256. struct spi_device *spi,
  257. struct spi_transfer *xfer)
  258. {
  259. struct img_spfi *spfi = spi_master_get_devdata(spi->master);
  260. struct dma_async_tx_descriptor *rxdesc = NULL, *txdesc = NULL;
  261. struct dma_slave_config rxconf, txconf;
  262. spfi->rx_dma_busy = false;
  263. spfi->tx_dma_busy = false;
  264. if (xfer->rx_buf) {
  265. rxconf.direction = DMA_DEV_TO_MEM;
  266. if (xfer->len % 4 == 0) {
  267. rxconf.src_addr = spfi->phys + SPFI_RX_32BIT_VALID_DATA;
  268. rxconf.src_addr_width = 4;
  269. rxconf.src_maxburst = 4;
  270. } else {
  271. rxconf.src_addr = spfi->phys + SPFI_RX_8BIT_VALID_DATA;
  272. rxconf.src_addr_width = 1;
  273. rxconf.src_maxburst = 4;
  274. }
  275. dmaengine_slave_config(spfi->rx_ch, &rxconf);
  276. rxdesc = dmaengine_prep_slave_sg(spfi->rx_ch, xfer->rx_sg.sgl,
  277. xfer->rx_sg.nents,
  278. DMA_DEV_TO_MEM,
  279. DMA_PREP_INTERRUPT);
  280. if (!rxdesc)
  281. goto stop_dma;
  282. rxdesc->callback = img_spfi_dma_rx_cb;
  283. rxdesc->callback_param = spfi;
  284. }
  285. if (xfer->tx_buf) {
  286. txconf.direction = DMA_MEM_TO_DEV;
  287. if (xfer->len % 4 == 0) {
  288. txconf.dst_addr = spfi->phys + SPFI_TX_32BIT_VALID_DATA;
  289. txconf.dst_addr_width = 4;
  290. txconf.dst_maxburst = 4;
  291. } else {
  292. txconf.dst_addr = spfi->phys + SPFI_TX_8BIT_VALID_DATA;
  293. txconf.dst_addr_width = 1;
  294. txconf.dst_maxburst = 4;
  295. }
  296. dmaengine_slave_config(spfi->tx_ch, &txconf);
  297. txdesc = dmaengine_prep_slave_sg(spfi->tx_ch, xfer->tx_sg.sgl,
  298. xfer->tx_sg.nents,
  299. DMA_MEM_TO_DEV,
  300. DMA_PREP_INTERRUPT);
  301. if (!txdesc)
  302. goto stop_dma;
  303. txdesc->callback = img_spfi_dma_tx_cb;
  304. txdesc->callback_param = spfi;
  305. }
  306. if (xfer->rx_buf) {
  307. spfi->rx_dma_busy = true;
  308. dmaengine_submit(rxdesc);
  309. dma_async_issue_pending(spfi->rx_ch);
  310. }
  311. spfi_start(spfi);
  312. if (xfer->tx_buf) {
  313. spfi->tx_dma_busy = true;
  314. dmaengine_submit(txdesc);
  315. dma_async_issue_pending(spfi->tx_ch);
  316. }
  317. return 1;
  318. stop_dma:
  319. dmaengine_terminate_all(spfi->rx_ch);
  320. dmaengine_terminate_all(spfi->tx_ch);
  321. return -EIO;
  322. }
  323. static void img_spfi_handle_err(struct spi_master *master,
  324. struct spi_message *msg)
  325. {
  326. struct img_spfi *spfi = spi_master_get_devdata(master);
  327. unsigned long flags;
  328. /*
  329. * Stop all DMA and reset the controller if the previous transaction
  330. * timed-out and never completed it's DMA.
  331. */
  332. spin_lock_irqsave(&spfi->lock, flags);
  333. if (spfi->tx_dma_busy || spfi->rx_dma_busy) {
  334. spfi->tx_dma_busy = false;
  335. spfi->rx_dma_busy = false;
  336. dmaengine_terminate_all(spfi->tx_ch);
  337. dmaengine_terminate_all(spfi->rx_ch);
  338. }
  339. spin_unlock_irqrestore(&spfi->lock, flags);
  340. }
  341. static int img_spfi_prepare(struct spi_master *master, struct spi_message *msg)
  342. {
  343. struct img_spfi *spfi = spi_master_get_devdata(master);
  344. u32 val;
  345. val = spfi_readl(spfi, SPFI_PORT_STATE);
  346. val &= ~(SPFI_PORT_STATE_DEV_SEL_MASK <<
  347. SPFI_PORT_STATE_DEV_SEL_SHIFT);
  348. val |= msg->spi->chip_select << SPFI_PORT_STATE_DEV_SEL_SHIFT;
  349. if (msg->spi->mode & SPI_CPHA)
  350. val |= SPFI_PORT_STATE_CK_PHASE(msg->spi->chip_select);
  351. else
  352. val &= ~SPFI_PORT_STATE_CK_PHASE(msg->spi->chip_select);
  353. if (msg->spi->mode & SPI_CPOL)
  354. val |= SPFI_PORT_STATE_CK_POL(msg->spi->chip_select);
  355. else
  356. val &= ~SPFI_PORT_STATE_CK_POL(msg->spi->chip_select);
  357. spfi_writel(spfi, val, SPFI_PORT_STATE);
  358. return 0;
  359. }
  360. static int img_spfi_unprepare(struct spi_master *master,
  361. struct spi_message *msg)
  362. {
  363. struct img_spfi *spfi = spi_master_get_devdata(master);
  364. spfi_reset(spfi);
  365. return 0;
  366. }
  367. static void img_spfi_config(struct spi_master *master, struct spi_device *spi,
  368. struct spi_transfer *xfer)
  369. {
  370. struct img_spfi *spfi = spi_master_get_devdata(spi->master);
  371. u32 val, div;
  372. /*
  373. * output = spfi_clk * (BITCLK / 512), where BITCLK must be a
  374. * power of 2 up to 128
  375. */
  376. div = DIV_ROUND_UP(clk_get_rate(spfi->spfi_clk), xfer->speed_hz);
  377. div = clamp(512 / (1 << get_count_order(div)), 1, 128);
  378. val = spfi_readl(spfi, SPFI_DEVICE_PARAMETER(spi->chip_select));
  379. val &= ~(SPFI_DEVICE_PARAMETER_BITCLK_MASK <<
  380. SPFI_DEVICE_PARAMETER_BITCLK_SHIFT);
  381. val |= div << SPFI_DEVICE_PARAMETER_BITCLK_SHIFT;
  382. spfi_writel(spfi, val, SPFI_DEVICE_PARAMETER(spi->chip_select));
  383. spfi_writel(spfi, xfer->len << SPFI_TRANSACTION_TSIZE_SHIFT,
  384. SPFI_TRANSACTION);
  385. val = spfi_readl(spfi, SPFI_CONTROL);
  386. val &= ~(SPFI_CONTROL_SEND_DMA | SPFI_CONTROL_GET_DMA);
  387. if (xfer->tx_buf)
  388. val |= SPFI_CONTROL_SEND_DMA;
  389. if (xfer->rx_buf)
  390. val |= SPFI_CONTROL_GET_DMA;
  391. val &= ~(SPFI_CONTROL_TMODE_MASK << SPFI_CONTROL_TMODE_SHIFT);
  392. if (xfer->tx_nbits == SPI_NBITS_DUAL &&
  393. xfer->rx_nbits == SPI_NBITS_DUAL)
  394. val |= SPFI_CONTROL_TMODE_DUAL << SPFI_CONTROL_TMODE_SHIFT;
  395. else if (xfer->tx_nbits == SPI_NBITS_QUAD &&
  396. xfer->rx_nbits == SPI_NBITS_QUAD)
  397. val |= SPFI_CONTROL_TMODE_QUAD << SPFI_CONTROL_TMODE_SHIFT;
  398. val |= SPFI_CONTROL_SE;
  399. spfi_writel(spfi, val, SPFI_CONTROL);
  400. }
  401. static int img_spfi_transfer_one(struct spi_master *master,
  402. struct spi_device *spi,
  403. struct spi_transfer *xfer)
  404. {
  405. struct img_spfi *spfi = spi_master_get_devdata(spi->master);
  406. int ret;
  407. if (xfer->len > SPFI_TRANSACTION_TSIZE_MASK) {
  408. dev_err(spfi->dev,
  409. "Transfer length (%d) is greater than the max supported (%d)",
  410. xfer->len, SPFI_TRANSACTION_TSIZE_MASK);
  411. return -EINVAL;
  412. }
  413. img_spfi_config(master, spi, xfer);
  414. if (master->can_dma && master->can_dma(master, spi, xfer))
  415. ret = img_spfi_start_dma(master, spi, xfer);
  416. else
  417. ret = img_spfi_start_pio(master, spi, xfer);
  418. return ret;
  419. }
  420. static bool img_spfi_can_dma(struct spi_master *master, struct spi_device *spi,
  421. struct spi_transfer *xfer)
  422. {
  423. if (xfer->len > SPFI_32BIT_FIFO_SIZE)
  424. return true;
  425. return false;
  426. }
  427. static irqreturn_t img_spfi_irq(int irq, void *dev_id)
  428. {
  429. struct img_spfi *spfi = (struct img_spfi *)dev_id;
  430. u32 status;
  431. status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
  432. if (status & SPFI_INTERRUPT_IACCESS) {
  433. spfi_writel(spfi, SPFI_INTERRUPT_IACCESS, SPFI_INTERRUPT_CLEAR);
  434. dev_err(spfi->dev, "Illegal access interrupt");
  435. return IRQ_HANDLED;
  436. }
  437. return IRQ_NONE;
  438. }
  439. static int img_spfi_probe(struct platform_device *pdev)
  440. {
  441. struct spi_master *master;
  442. struct img_spfi *spfi;
  443. struct resource *res;
  444. int ret;
  445. u32 max_speed_hz;
  446. master = spi_alloc_master(&pdev->dev, sizeof(*spfi));
  447. if (!master)
  448. return -ENOMEM;
  449. platform_set_drvdata(pdev, master);
  450. spfi = spi_master_get_devdata(master);
  451. spfi->dev = &pdev->dev;
  452. spfi->master = master;
  453. spin_lock_init(&spfi->lock);
  454. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  455. spfi->regs = devm_ioremap_resource(spfi->dev, res);
  456. if (IS_ERR(spfi->regs)) {
  457. ret = PTR_ERR(spfi->regs);
  458. goto put_spi;
  459. }
  460. spfi->phys = res->start;
  461. spfi->irq = platform_get_irq(pdev, 0);
  462. if (spfi->irq < 0) {
  463. ret = spfi->irq;
  464. goto put_spi;
  465. }
  466. ret = devm_request_irq(spfi->dev, spfi->irq, img_spfi_irq,
  467. IRQ_TYPE_LEVEL_HIGH, dev_name(spfi->dev), spfi);
  468. if (ret)
  469. goto put_spi;
  470. spfi->sys_clk = devm_clk_get(spfi->dev, "sys");
  471. if (IS_ERR(spfi->sys_clk)) {
  472. ret = PTR_ERR(spfi->sys_clk);
  473. goto put_spi;
  474. }
  475. spfi->spfi_clk = devm_clk_get(spfi->dev, "spfi");
  476. if (IS_ERR(spfi->spfi_clk)) {
  477. ret = PTR_ERR(spfi->spfi_clk);
  478. goto put_spi;
  479. }
  480. ret = clk_prepare_enable(spfi->sys_clk);
  481. if (ret)
  482. goto put_spi;
  483. ret = clk_prepare_enable(spfi->spfi_clk);
  484. if (ret)
  485. goto disable_pclk;
  486. spfi_reset(spfi);
  487. /*
  488. * Only enable the error (IACCESS) interrupt. In PIO mode we'll
  489. * poll the status of the FIFOs.
  490. */
  491. spfi_writel(spfi, SPFI_INTERRUPT_IACCESS, SPFI_INTERRUPT_ENABLE);
  492. master->auto_runtime_pm = true;
  493. master->bus_num = pdev->id;
  494. master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_TX_DUAL | SPI_RX_DUAL;
  495. if (of_property_read_bool(spfi->dev->of_node, "img,supports-quad-mode"))
  496. master->mode_bits |= SPI_TX_QUAD | SPI_RX_QUAD;
  497. master->dev.of_node = pdev->dev.of_node;
  498. master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(8);
  499. master->max_speed_hz = clk_get_rate(spfi->spfi_clk) / 4;
  500. master->min_speed_hz = clk_get_rate(spfi->spfi_clk) / 512;
  501. /*
  502. * Maximum speed supported by spfi is limited to the lower value
  503. * between 1/4 of the SPFI clock or to "spfi-max-frequency"
  504. * defined in the device tree.
  505. * If no value is defined in the device tree assume the maximum
  506. * speed supported to be 1/4 of the SPFI clock.
  507. */
  508. if (!of_property_read_u32(spfi->dev->of_node, "spfi-max-frequency",
  509. &max_speed_hz)) {
  510. if (master->max_speed_hz > max_speed_hz)
  511. master->max_speed_hz = max_speed_hz;
  512. }
  513. master->transfer_one = img_spfi_transfer_one;
  514. master->prepare_message = img_spfi_prepare;
  515. master->unprepare_message = img_spfi_unprepare;
  516. master->handle_err = img_spfi_handle_err;
  517. master->use_gpio_descriptors = true;
  518. spfi->tx_ch = dma_request_chan(spfi->dev, "tx");
  519. if (IS_ERR(spfi->tx_ch)) {
  520. ret = PTR_ERR(spfi->tx_ch);
  521. spfi->tx_ch = NULL;
  522. if (ret == -EPROBE_DEFER)
  523. goto disable_pm;
  524. }
  525. spfi->rx_ch = dma_request_chan(spfi->dev, "rx");
  526. if (IS_ERR(spfi->rx_ch)) {
  527. ret = PTR_ERR(spfi->rx_ch);
  528. spfi->rx_ch = NULL;
  529. if (ret == -EPROBE_DEFER)
  530. goto disable_pm;
  531. }
  532. if (!spfi->tx_ch || !spfi->rx_ch) {
  533. if (spfi->tx_ch)
  534. dma_release_channel(spfi->tx_ch);
  535. if (spfi->rx_ch)
  536. dma_release_channel(spfi->rx_ch);
  537. spfi->tx_ch = NULL;
  538. spfi->rx_ch = NULL;
  539. dev_warn(spfi->dev, "Failed to get DMA channels, falling back to PIO mode\n");
  540. } else {
  541. master->dma_tx = spfi->tx_ch;
  542. master->dma_rx = spfi->rx_ch;
  543. master->can_dma = img_spfi_can_dma;
  544. }
  545. pm_runtime_set_active(spfi->dev);
  546. pm_runtime_enable(spfi->dev);
  547. ret = devm_spi_register_master(spfi->dev, master);
  548. if (ret)
  549. goto disable_pm;
  550. return 0;
  551. disable_pm:
  552. pm_runtime_disable(spfi->dev);
  553. if (spfi->rx_ch)
  554. dma_release_channel(spfi->rx_ch);
  555. if (spfi->tx_ch)
  556. dma_release_channel(spfi->tx_ch);
  557. clk_disable_unprepare(spfi->spfi_clk);
  558. disable_pclk:
  559. clk_disable_unprepare(spfi->sys_clk);
  560. put_spi:
  561. spi_master_put(master);
  562. return ret;
  563. }
  564. static int img_spfi_remove(struct platform_device *pdev)
  565. {
  566. struct spi_master *master = platform_get_drvdata(pdev);
  567. struct img_spfi *spfi = spi_master_get_devdata(master);
  568. if (spfi->tx_ch)
  569. dma_release_channel(spfi->tx_ch);
  570. if (spfi->rx_ch)
  571. dma_release_channel(spfi->rx_ch);
  572. pm_runtime_disable(spfi->dev);
  573. if (!pm_runtime_status_suspended(spfi->dev)) {
  574. clk_disable_unprepare(spfi->spfi_clk);
  575. clk_disable_unprepare(spfi->sys_clk);
  576. }
  577. return 0;
  578. }
  579. #ifdef CONFIG_PM
  580. static int img_spfi_runtime_suspend(struct device *dev)
  581. {
  582. struct spi_master *master = dev_get_drvdata(dev);
  583. struct img_spfi *spfi = spi_master_get_devdata(master);
  584. clk_disable_unprepare(spfi->spfi_clk);
  585. clk_disable_unprepare(spfi->sys_clk);
  586. return 0;
  587. }
  588. static int img_spfi_runtime_resume(struct device *dev)
  589. {
  590. struct spi_master *master = dev_get_drvdata(dev);
  591. struct img_spfi *spfi = spi_master_get_devdata(master);
  592. int ret;
  593. ret = clk_prepare_enable(spfi->sys_clk);
  594. if (ret)
  595. return ret;
  596. ret = clk_prepare_enable(spfi->spfi_clk);
  597. if (ret) {
  598. clk_disable_unprepare(spfi->sys_clk);
  599. return ret;
  600. }
  601. return 0;
  602. }
  603. #endif /* CONFIG_PM */
  604. #ifdef CONFIG_PM_SLEEP
  605. static int img_spfi_suspend(struct device *dev)
  606. {
  607. struct spi_master *master = dev_get_drvdata(dev);
  608. return spi_master_suspend(master);
  609. }
  610. static int img_spfi_resume(struct device *dev)
  611. {
  612. struct spi_master *master = dev_get_drvdata(dev);
  613. struct img_spfi *spfi = spi_master_get_devdata(master);
  614. int ret;
  615. ret = pm_runtime_get_sync(dev);
  616. if (ret) {
  617. pm_runtime_put_noidle(dev);
  618. return ret;
  619. }
  620. spfi_reset(spfi);
  621. pm_runtime_put(dev);
  622. return spi_master_resume(master);
  623. }
  624. #endif /* CONFIG_PM_SLEEP */
  625. static const struct dev_pm_ops img_spfi_pm_ops = {
  626. SET_RUNTIME_PM_OPS(img_spfi_runtime_suspend, img_spfi_runtime_resume,
  627. NULL)
  628. SET_SYSTEM_SLEEP_PM_OPS(img_spfi_suspend, img_spfi_resume)
  629. };
  630. static const struct of_device_id img_spfi_of_match[] = {
  631. { .compatible = "img,spfi", },
  632. { },
  633. };
  634. MODULE_DEVICE_TABLE(of, img_spfi_of_match);
  635. static struct platform_driver img_spfi_driver = {
  636. .driver = {
  637. .name = "img-spfi",
  638. .pm = &img_spfi_pm_ops,
  639. .of_match_table = of_match_ptr(img_spfi_of_match),
  640. },
  641. .probe = img_spfi_probe,
  642. .remove = img_spfi_remove,
  643. };
  644. module_platform_driver(img_spfi_driver);
  645. MODULE_DESCRIPTION("IMG SPFI controller driver");
  646. MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>");
  647. MODULE_LICENSE("GPL v2");