spi-fsl-spi.h 1.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * Freescale SPI controller driver.
  4. *
  5. * Maintainer: Kumar Gala
  6. *
  7. * Copyright (C) 2006 Polycom, Inc.
  8. * Copyright 2010 Freescale Semiconductor, Inc.
  9. *
  10. * CPM SPI and QE buffer descriptors mode support:
  11. * Copyright (c) 2009 MontaVista Software, Inc.
  12. * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
  13. *
  14. * GRLIB support:
  15. * Copyright (c) 2012 Aeroflex Gaisler AB.
  16. * Author: Andreas Larsson <andreas@gaisler.com>
  17. */
  18. #ifndef __SPI_FSL_SPI_H__
  19. #define __SPI_FSL_SPI_H__
  20. /* SPI Controller registers */
  21. struct fsl_spi_reg {
  22. __be32 cap; /* TYPE_GRLIB specific */
  23. u8 res1[0x1C];
  24. __be32 mode;
  25. __be32 event;
  26. __be32 mask;
  27. __be32 command;
  28. __be32 transmit;
  29. __be32 receive;
  30. __be32 slvsel; /* TYPE_GRLIB specific */
  31. };
  32. /* SPI Controller mode register definitions */
  33. #define SPMODE_LOOP (1 << 30)
  34. #define SPMODE_CI_INACTIVEHIGH (1 << 29)
  35. #define SPMODE_CP_BEGIN_EDGECLK (1 << 28)
  36. #define SPMODE_DIV16 (1 << 27)
  37. #define SPMODE_REV (1 << 26)
  38. #define SPMODE_MS (1 << 25)
  39. #define SPMODE_ENABLE (1 << 24)
  40. #define SPMODE_LEN(x) ((x) << 20)
  41. #define SPMODE_PM(x) ((x) << 16)
  42. #define SPMODE_OP (1 << 14)
  43. #define SPMODE_CG(x) ((x) << 7)
  44. /* TYPE_GRLIB SPI Controller capability register definitions */
  45. #define SPCAP_SSEN(x) (((x) >> 16) & 0x1)
  46. #define SPCAP_SSSZ(x) (((x) >> 24) & 0xff)
  47. #define SPCAP_MAXWLEN(x) (((x) >> 20) & 0xf)
  48. /*
  49. * Default for SPI Mode:
  50. * SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
  51. */
  52. #define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
  53. SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
  54. /* SPIE register values */
  55. #define SPIE_NE 0x00000200 /* Not empty */
  56. #define SPIE_NF 0x00000100 /* Not full */
  57. /* SPIM register values */
  58. #define SPIM_NE 0x00000200 /* Not empty */
  59. #define SPIM_NF 0x00000100 /* Not full */
  60. #endif /* __SPI_FSL_SPI_H__ */