spi-fsl-cpm.c 9.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Freescale SPI controller driver cpm functions.
  4. *
  5. * Maintainer: Kumar Gala
  6. *
  7. * Copyright (C) 2006 Polycom, Inc.
  8. * Copyright 2010 Freescale Semiconductor, Inc.
  9. *
  10. * CPM SPI and QE buffer descriptors mode support:
  11. * Copyright (c) 2009 MontaVista Software, Inc.
  12. * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
  13. */
  14. #include <asm/cpm.h>
  15. #include <soc/fsl/qe/qe.h>
  16. #include <linux/dma-mapping.h>
  17. #include <linux/fsl_devices.h>
  18. #include <linux/kernel.h>
  19. #include <linux/module.h>
  20. #include <linux/of_address.h>
  21. #include <linux/spi/spi.h>
  22. #include <linux/types.h>
  23. #include <linux/platform_device.h>
  24. #include "spi-fsl-cpm.h"
  25. #include "spi-fsl-lib.h"
  26. #include "spi-fsl-spi.h"
  27. /* CPM1 and CPM2 are mutually exclusive. */
  28. #ifdef CONFIG_CPM1
  29. #include <asm/cpm1.h>
  30. #define CPM_SPI_CMD mk_cr_cmd(CPM_CR_CH_SPI, 0)
  31. #else
  32. #include <asm/cpm2.h>
  33. #define CPM_SPI_CMD mk_cr_cmd(CPM_CR_SPI_PAGE, CPM_CR_SPI_SBLOCK, 0, 0)
  34. #endif
  35. #define SPIE_TXB 0x00000200 /* Last char is written to tx fifo */
  36. #define SPIE_RXB 0x00000100 /* Last char is written to rx buf */
  37. /* SPCOM register values */
  38. #define SPCOM_STR (1 << 23) /* Start transmit */
  39. #define SPI_PRAM_SIZE 0x100
  40. #define SPI_MRBLR ((unsigned int)PAGE_SIZE)
  41. static void *fsl_dummy_rx;
  42. static DEFINE_MUTEX(fsl_dummy_rx_lock);
  43. static int fsl_dummy_rx_refcnt;
  44. void fsl_spi_cpm_reinit_txrx(struct mpc8xxx_spi *mspi)
  45. {
  46. if (mspi->flags & SPI_QE) {
  47. qe_issue_cmd(QE_INIT_TX_RX, mspi->subblock,
  48. QE_CR_PROTOCOL_UNSPECIFIED, 0);
  49. } else {
  50. if (mspi->flags & SPI_CPM1) {
  51. out_be32(&mspi->pram->rstate, 0);
  52. out_be16(&mspi->pram->rbptr,
  53. in_be16(&mspi->pram->rbase));
  54. out_be32(&mspi->pram->tstate, 0);
  55. out_be16(&mspi->pram->tbptr,
  56. in_be16(&mspi->pram->tbase));
  57. } else {
  58. cpm_command(CPM_SPI_CMD, CPM_CR_INIT_TRX);
  59. }
  60. }
  61. }
  62. EXPORT_SYMBOL_GPL(fsl_spi_cpm_reinit_txrx);
  63. static void fsl_spi_cpm_bufs_start(struct mpc8xxx_spi *mspi)
  64. {
  65. struct cpm_buf_desc __iomem *tx_bd = mspi->tx_bd;
  66. struct cpm_buf_desc __iomem *rx_bd = mspi->rx_bd;
  67. unsigned int xfer_len = min(mspi->count, SPI_MRBLR);
  68. unsigned int xfer_ofs;
  69. struct fsl_spi_reg *reg_base = mspi->reg_base;
  70. xfer_ofs = mspi->xfer_in_progress->len - mspi->count;
  71. if (mspi->rx_dma == mspi->dma_dummy_rx)
  72. out_be32(&rx_bd->cbd_bufaddr, mspi->rx_dma);
  73. else
  74. out_be32(&rx_bd->cbd_bufaddr, mspi->rx_dma + xfer_ofs);
  75. out_be16(&rx_bd->cbd_datlen, 0);
  76. out_be16(&rx_bd->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT | BD_SC_WRAP);
  77. if (mspi->tx_dma == mspi->dma_dummy_tx)
  78. out_be32(&tx_bd->cbd_bufaddr, mspi->tx_dma);
  79. else
  80. out_be32(&tx_bd->cbd_bufaddr, mspi->tx_dma + xfer_ofs);
  81. out_be16(&tx_bd->cbd_datlen, xfer_len);
  82. out_be16(&tx_bd->cbd_sc, BD_SC_READY | BD_SC_INTRPT | BD_SC_WRAP |
  83. BD_SC_LAST);
  84. /* start transfer */
  85. mpc8xxx_spi_write_reg(&reg_base->command, SPCOM_STR);
  86. }
  87. int fsl_spi_cpm_bufs(struct mpc8xxx_spi *mspi,
  88. struct spi_transfer *t, bool is_dma_mapped)
  89. {
  90. struct device *dev = mspi->dev;
  91. struct fsl_spi_reg *reg_base = mspi->reg_base;
  92. if (is_dma_mapped) {
  93. mspi->map_tx_dma = 0;
  94. mspi->map_rx_dma = 0;
  95. } else {
  96. mspi->map_tx_dma = 1;
  97. mspi->map_rx_dma = 1;
  98. }
  99. if (!t->tx_buf) {
  100. mspi->tx_dma = mspi->dma_dummy_tx;
  101. mspi->map_tx_dma = 0;
  102. }
  103. if (!t->rx_buf) {
  104. mspi->rx_dma = mspi->dma_dummy_rx;
  105. mspi->map_rx_dma = 0;
  106. }
  107. if (mspi->map_tx_dma) {
  108. void *nonconst_tx = (void *)mspi->tx; /* shut up gcc */
  109. mspi->tx_dma = dma_map_single(dev, nonconst_tx, t->len,
  110. DMA_TO_DEVICE);
  111. if (dma_mapping_error(dev, mspi->tx_dma)) {
  112. dev_err(dev, "unable to map tx dma\n");
  113. return -ENOMEM;
  114. }
  115. } else if (t->tx_buf) {
  116. mspi->tx_dma = t->tx_dma;
  117. }
  118. if (mspi->map_rx_dma) {
  119. mspi->rx_dma = dma_map_single(dev, mspi->rx, t->len,
  120. DMA_FROM_DEVICE);
  121. if (dma_mapping_error(dev, mspi->rx_dma)) {
  122. dev_err(dev, "unable to map rx dma\n");
  123. goto err_rx_dma;
  124. }
  125. } else if (t->rx_buf) {
  126. mspi->rx_dma = t->rx_dma;
  127. }
  128. /* enable rx ints */
  129. mpc8xxx_spi_write_reg(&reg_base->mask, SPIE_RXB);
  130. mspi->xfer_in_progress = t;
  131. mspi->count = t->len;
  132. /* start CPM transfers */
  133. fsl_spi_cpm_bufs_start(mspi);
  134. return 0;
  135. err_rx_dma:
  136. if (mspi->map_tx_dma)
  137. dma_unmap_single(dev, mspi->tx_dma, t->len, DMA_TO_DEVICE);
  138. return -ENOMEM;
  139. }
  140. EXPORT_SYMBOL_GPL(fsl_spi_cpm_bufs);
  141. void fsl_spi_cpm_bufs_complete(struct mpc8xxx_spi *mspi)
  142. {
  143. struct device *dev = mspi->dev;
  144. struct spi_transfer *t = mspi->xfer_in_progress;
  145. if (mspi->map_tx_dma)
  146. dma_unmap_single(dev, mspi->tx_dma, t->len, DMA_TO_DEVICE);
  147. if (mspi->map_rx_dma)
  148. dma_unmap_single(dev, mspi->rx_dma, t->len, DMA_FROM_DEVICE);
  149. mspi->xfer_in_progress = NULL;
  150. }
  151. EXPORT_SYMBOL_GPL(fsl_spi_cpm_bufs_complete);
  152. void fsl_spi_cpm_irq(struct mpc8xxx_spi *mspi, u32 events)
  153. {
  154. u16 len;
  155. struct fsl_spi_reg *reg_base = mspi->reg_base;
  156. dev_dbg(mspi->dev, "%s: bd datlen %d, count %d\n", __func__,
  157. in_be16(&mspi->rx_bd->cbd_datlen), mspi->count);
  158. len = in_be16(&mspi->rx_bd->cbd_datlen);
  159. if (len > mspi->count) {
  160. WARN_ON(1);
  161. len = mspi->count;
  162. }
  163. /* Clear the events */
  164. mpc8xxx_spi_write_reg(&reg_base->event, events);
  165. mspi->count -= len;
  166. if (mspi->count)
  167. fsl_spi_cpm_bufs_start(mspi);
  168. else
  169. complete(&mspi->done);
  170. }
  171. EXPORT_SYMBOL_GPL(fsl_spi_cpm_irq);
  172. static void *fsl_spi_alloc_dummy_rx(void)
  173. {
  174. mutex_lock(&fsl_dummy_rx_lock);
  175. if (!fsl_dummy_rx)
  176. fsl_dummy_rx = kmalloc(SPI_MRBLR, GFP_KERNEL);
  177. if (fsl_dummy_rx)
  178. fsl_dummy_rx_refcnt++;
  179. mutex_unlock(&fsl_dummy_rx_lock);
  180. return fsl_dummy_rx;
  181. }
  182. static void fsl_spi_free_dummy_rx(void)
  183. {
  184. mutex_lock(&fsl_dummy_rx_lock);
  185. switch (fsl_dummy_rx_refcnt) {
  186. case 0:
  187. WARN_ON(1);
  188. break;
  189. case 1:
  190. kfree(fsl_dummy_rx);
  191. fsl_dummy_rx = NULL;
  192. fallthrough;
  193. default:
  194. fsl_dummy_rx_refcnt--;
  195. break;
  196. }
  197. mutex_unlock(&fsl_dummy_rx_lock);
  198. }
  199. static unsigned long fsl_spi_cpm_get_pram(struct mpc8xxx_spi *mspi)
  200. {
  201. struct device *dev = mspi->dev;
  202. struct device_node *np = dev->of_node;
  203. const u32 *iprop;
  204. int size;
  205. void __iomem *spi_base;
  206. unsigned long pram_ofs = -ENOMEM;
  207. /* Can't use of_address_to_resource(), QE muram isn't at 0. */
  208. iprop = of_get_property(np, "reg", &size);
  209. /* QE with a fixed pram location? */
  210. if (mspi->flags & SPI_QE && iprop && size == sizeof(*iprop) * 4)
  211. return cpm_muram_alloc_fixed(iprop[2], SPI_PRAM_SIZE);
  212. /* QE but with a dynamic pram location? */
  213. if (mspi->flags & SPI_QE) {
  214. pram_ofs = cpm_muram_alloc(SPI_PRAM_SIZE, 64);
  215. qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, mspi->subblock,
  216. QE_CR_PROTOCOL_UNSPECIFIED, pram_ofs);
  217. return pram_ofs;
  218. }
  219. spi_base = of_iomap(np, 1);
  220. if (spi_base == NULL)
  221. return -EINVAL;
  222. if (mspi->flags & SPI_CPM2) {
  223. pram_ofs = cpm_muram_alloc(SPI_PRAM_SIZE, 64);
  224. out_be16(spi_base, pram_ofs);
  225. }
  226. iounmap(spi_base);
  227. return pram_ofs;
  228. }
  229. int fsl_spi_cpm_init(struct mpc8xxx_spi *mspi)
  230. {
  231. struct device *dev = mspi->dev;
  232. struct device_node *np = dev->of_node;
  233. const u32 *iprop;
  234. int size;
  235. unsigned long bds_ofs;
  236. if (!(mspi->flags & SPI_CPM_MODE))
  237. return 0;
  238. if (!fsl_spi_alloc_dummy_rx())
  239. return -ENOMEM;
  240. if (mspi->flags & SPI_QE) {
  241. iprop = of_get_property(np, "cell-index", &size);
  242. if (iprop && size == sizeof(*iprop))
  243. mspi->subblock = *iprop;
  244. switch (mspi->subblock) {
  245. default:
  246. dev_warn(dev, "cell-index unspecified, assuming SPI1\n");
  247. fallthrough;
  248. case 0:
  249. mspi->subblock = QE_CR_SUBBLOCK_SPI1;
  250. break;
  251. case 1:
  252. mspi->subblock = QE_CR_SUBBLOCK_SPI2;
  253. break;
  254. }
  255. }
  256. if (mspi->flags & SPI_CPM1) {
  257. void *pram;
  258. pram = devm_platform_ioremap_resource(to_platform_device(dev),
  259. 1);
  260. if (IS_ERR(pram))
  261. mspi->pram = NULL;
  262. else
  263. mspi->pram = pram;
  264. } else {
  265. unsigned long pram_ofs = fsl_spi_cpm_get_pram(mspi);
  266. if (IS_ERR_VALUE(pram_ofs))
  267. mspi->pram = NULL;
  268. else
  269. mspi->pram = cpm_muram_addr(pram_ofs);
  270. }
  271. if (mspi->pram == NULL) {
  272. dev_err(dev, "can't allocate spi parameter ram\n");
  273. goto err_pram;
  274. }
  275. bds_ofs = cpm_muram_alloc(sizeof(*mspi->tx_bd) +
  276. sizeof(*mspi->rx_bd), 8);
  277. if (IS_ERR_VALUE(bds_ofs)) {
  278. dev_err(dev, "can't allocate bds\n");
  279. goto err_bds;
  280. }
  281. mspi->dma_dummy_tx = dma_map_single(dev, empty_zero_page, PAGE_SIZE,
  282. DMA_TO_DEVICE);
  283. if (dma_mapping_error(dev, mspi->dma_dummy_tx)) {
  284. dev_err(dev, "unable to map dummy tx buffer\n");
  285. goto err_dummy_tx;
  286. }
  287. mspi->dma_dummy_rx = dma_map_single(dev, fsl_dummy_rx, SPI_MRBLR,
  288. DMA_FROM_DEVICE);
  289. if (dma_mapping_error(dev, mspi->dma_dummy_rx)) {
  290. dev_err(dev, "unable to map dummy rx buffer\n");
  291. goto err_dummy_rx;
  292. }
  293. mspi->tx_bd = cpm_muram_addr(bds_ofs);
  294. mspi->rx_bd = cpm_muram_addr(bds_ofs + sizeof(*mspi->tx_bd));
  295. /* Initialize parameter ram. */
  296. out_be16(&mspi->pram->tbase, cpm_muram_offset(mspi->tx_bd));
  297. out_be16(&mspi->pram->rbase, cpm_muram_offset(mspi->rx_bd));
  298. out_8(&mspi->pram->tfcr, CPMFCR_EB | CPMFCR_GBL);
  299. out_8(&mspi->pram->rfcr, CPMFCR_EB | CPMFCR_GBL);
  300. out_be16(&mspi->pram->mrblr, SPI_MRBLR);
  301. out_be32(&mspi->pram->rstate, 0);
  302. out_be32(&mspi->pram->rdp, 0);
  303. out_be16(&mspi->pram->rbptr, 0);
  304. out_be16(&mspi->pram->rbc, 0);
  305. out_be32(&mspi->pram->rxtmp, 0);
  306. out_be32(&mspi->pram->tstate, 0);
  307. out_be32(&mspi->pram->tdp, 0);
  308. out_be16(&mspi->pram->tbptr, 0);
  309. out_be16(&mspi->pram->tbc, 0);
  310. out_be32(&mspi->pram->txtmp, 0);
  311. return 0;
  312. err_dummy_rx:
  313. dma_unmap_single(dev, mspi->dma_dummy_tx, PAGE_SIZE, DMA_TO_DEVICE);
  314. err_dummy_tx:
  315. cpm_muram_free(bds_ofs);
  316. err_bds:
  317. if (!(mspi->flags & SPI_CPM1))
  318. cpm_muram_free(cpm_muram_offset(mspi->pram));
  319. err_pram:
  320. fsl_spi_free_dummy_rx();
  321. return -ENOMEM;
  322. }
  323. EXPORT_SYMBOL_GPL(fsl_spi_cpm_init);
  324. void fsl_spi_cpm_free(struct mpc8xxx_spi *mspi)
  325. {
  326. struct device *dev = mspi->dev;
  327. if (!(mspi->flags & SPI_CPM_MODE))
  328. return;
  329. dma_unmap_single(dev, mspi->dma_dummy_rx, SPI_MRBLR, DMA_FROM_DEVICE);
  330. dma_unmap_single(dev, mspi->dma_dummy_tx, PAGE_SIZE, DMA_TO_DEVICE);
  331. cpm_muram_free(cpm_muram_offset(mspi->tx_bd));
  332. if (!(mspi->flags & SPI_CPM1))
  333. cpm_muram_free(cpm_muram_offset(mspi->pram));
  334. fsl_spi_free_dummy_rx();
  335. }
  336. EXPORT_SYMBOL_GPL(fsl_spi_cpm_free);
  337. MODULE_LICENSE("GPL");