spi-falcon.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. *
  4. * Copyright (C) 2012 Thomas Langer <thomas.langer@lantiq.com>
  5. */
  6. #include <linux/module.h>
  7. #include <linux/device.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/spi/spi.h>
  10. #include <linux/delay.h>
  11. #include <linux/of.h>
  12. #include <linux/of_platform.h>
  13. #include <lantiq_soc.h>
  14. #define DRV_NAME "sflash-falcon"
  15. #define FALCON_SPI_XFER_BEGIN (1 << 0)
  16. #define FALCON_SPI_XFER_END (1 << 1)
  17. /* Bus Read Configuration Register0 */
  18. #define BUSRCON0 0x00000010
  19. /* Bus Write Configuration Register0 */
  20. #define BUSWCON0 0x00000018
  21. /* Serial Flash Configuration Register */
  22. #define SFCON 0x00000080
  23. /* Serial Flash Time Register */
  24. #define SFTIME 0x00000084
  25. /* Serial Flash Status Register */
  26. #define SFSTAT 0x00000088
  27. /* Serial Flash Command Register */
  28. #define SFCMD 0x0000008C
  29. /* Serial Flash Address Register */
  30. #define SFADDR 0x00000090
  31. /* Serial Flash Data Register */
  32. #define SFDATA 0x00000094
  33. /* Serial Flash I/O Control Register */
  34. #define SFIO 0x00000098
  35. /* EBU Clock Control Register */
  36. #define EBUCC 0x000000C4
  37. /* Dummy Phase Length */
  38. #define SFCMD_DUMLEN_OFFSET 16
  39. #define SFCMD_DUMLEN_MASK 0x000F0000
  40. /* Chip Select */
  41. #define SFCMD_CS_OFFSET 24
  42. #define SFCMD_CS_MASK 0x07000000
  43. /* field offset */
  44. #define SFCMD_ALEN_OFFSET 20
  45. #define SFCMD_ALEN_MASK 0x00700000
  46. /* SCK Rise-edge Position */
  47. #define SFTIME_SCKR_POS_OFFSET 8
  48. #define SFTIME_SCKR_POS_MASK 0x00000F00
  49. /* SCK Period */
  50. #define SFTIME_SCK_PER_OFFSET 0
  51. #define SFTIME_SCK_PER_MASK 0x0000000F
  52. /* SCK Fall-edge Position */
  53. #define SFTIME_SCKF_POS_OFFSET 12
  54. #define SFTIME_SCKF_POS_MASK 0x0000F000
  55. /* Device Size */
  56. #define SFCON_DEV_SIZE_A23_0 0x03000000
  57. #define SFCON_DEV_SIZE_MASK 0x0F000000
  58. /* Read Data Position */
  59. #define SFTIME_RD_POS_MASK 0x000F0000
  60. /* Data Output */
  61. #define SFIO_UNUSED_WD_MASK 0x0000000F
  62. /* Command Opcode mask */
  63. #define SFCMD_OPC_MASK 0x000000FF
  64. /* dlen bytes of data to write */
  65. #define SFCMD_DIR_WRITE 0x00000100
  66. /* Data Length offset */
  67. #define SFCMD_DLEN_OFFSET 9
  68. /* Command Error */
  69. #define SFSTAT_CMD_ERR 0x20000000
  70. /* Access Command Pending */
  71. #define SFSTAT_CMD_PEND 0x00400000
  72. /* Frequency set to 100MHz. */
  73. #define EBUCC_EBUDIV_SELF100 0x00000001
  74. /* Serial Flash */
  75. #define BUSRCON0_AGEN_SERIAL_FLASH 0xF0000000
  76. /* 8-bit multiplexed */
  77. #define BUSRCON0_PORTW_8_BIT_MUX 0x00000000
  78. /* Serial Flash */
  79. #define BUSWCON0_AGEN_SERIAL_FLASH 0xF0000000
  80. /* Chip Select after opcode */
  81. #define SFCMD_KEEP_CS_KEEP_SELECTED 0x00008000
  82. #define CLOCK_100M 100000000
  83. #define CLOCK_50M 50000000
  84. struct falcon_sflash {
  85. u32 sfcmd; /* for caching of opcode, direction, ... */
  86. struct spi_master *master;
  87. };
  88. int falcon_sflash_xfer(struct spi_device *spi, struct spi_transfer *t,
  89. unsigned long flags)
  90. {
  91. struct device *dev = &spi->dev;
  92. struct falcon_sflash *priv = spi_master_get_devdata(spi->master);
  93. const u8 *txp = t->tx_buf;
  94. u8 *rxp = t->rx_buf;
  95. unsigned int bytelen = ((8 * t->len + 7) / 8);
  96. unsigned int len, alen, dumlen;
  97. u32 val;
  98. enum {
  99. state_init,
  100. state_command_prepare,
  101. state_write,
  102. state_read,
  103. state_disable_cs,
  104. state_end
  105. } state = state_init;
  106. do {
  107. switch (state) {
  108. case state_init: /* detect phase of upper layer sequence */
  109. {
  110. /* initial write ? */
  111. if (flags & FALCON_SPI_XFER_BEGIN) {
  112. if (!txp) {
  113. dev_err(dev,
  114. "BEGIN without tx data!\n");
  115. return -ENODATA;
  116. }
  117. /*
  118. * Prepare the parts of the sfcmd register,
  119. * which should not change during a sequence!
  120. * Only exception are the length fields,
  121. * especially alen and dumlen.
  122. */
  123. priv->sfcmd = ((spi->chip_select
  124. << SFCMD_CS_OFFSET)
  125. & SFCMD_CS_MASK);
  126. priv->sfcmd |= SFCMD_KEEP_CS_KEEP_SELECTED;
  127. priv->sfcmd |= *txp;
  128. txp++;
  129. bytelen--;
  130. if (bytelen) {
  131. /*
  132. * more data:
  133. * maybe address and/or dummy
  134. */
  135. state = state_command_prepare;
  136. break;
  137. } else {
  138. dev_dbg(dev, "write cmd %02X\n",
  139. priv->sfcmd & SFCMD_OPC_MASK);
  140. }
  141. }
  142. /* continued write ? */
  143. if (txp && bytelen) {
  144. state = state_write;
  145. break;
  146. }
  147. /* read data? */
  148. if (rxp && bytelen) {
  149. state = state_read;
  150. break;
  151. }
  152. /* end of sequence? */
  153. if (flags & FALCON_SPI_XFER_END)
  154. state = state_disable_cs;
  155. else
  156. state = state_end;
  157. break;
  158. }
  159. /* collect tx data for address and dummy phase */
  160. case state_command_prepare:
  161. {
  162. /* txp is valid, already checked */
  163. val = 0;
  164. alen = 0;
  165. dumlen = 0;
  166. while (bytelen > 0) {
  167. if (alen < 3) {
  168. val = (val << 8) | (*txp++);
  169. alen++;
  170. } else if ((dumlen < 15) && (*txp == 0)) {
  171. /*
  172. * assume dummy bytes are set to 0
  173. * from upper layer
  174. */
  175. dumlen++;
  176. txp++;
  177. } else {
  178. break;
  179. }
  180. bytelen--;
  181. }
  182. priv->sfcmd &= ~(SFCMD_ALEN_MASK | SFCMD_DUMLEN_MASK);
  183. priv->sfcmd |= (alen << SFCMD_ALEN_OFFSET) |
  184. (dumlen << SFCMD_DUMLEN_OFFSET);
  185. if (alen > 0)
  186. ltq_ebu_w32(val, SFADDR);
  187. dev_dbg(dev, "wr %02X, alen=%d (addr=%06X) dlen=%d\n",
  188. priv->sfcmd & SFCMD_OPC_MASK,
  189. alen, val, dumlen);
  190. if (bytelen > 0) {
  191. /* continue with write */
  192. state = state_write;
  193. } else if (flags & FALCON_SPI_XFER_END) {
  194. /* end of sequence? */
  195. state = state_disable_cs;
  196. } else {
  197. /*
  198. * go to end and expect another
  199. * call (read or write)
  200. */
  201. state = state_end;
  202. }
  203. break;
  204. }
  205. case state_write:
  206. {
  207. /* txp still valid */
  208. priv->sfcmd |= SFCMD_DIR_WRITE;
  209. len = 0;
  210. val = 0;
  211. do {
  212. if (bytelen--)
  213. val |= (*txp++) << (8 * len++);
  214. if ((flags & FALCON_SPI_XFER_END)
  215. && (bytelen == 0)) {
  216. priv->sfcmd &=
  217. ~SFCMD_KEEP_CS_KEEP_SELECTED;
  218. }
  219. if ((len == 4) || (bytelen == 0)) {
  220. ltq_ebu_w32(val, SFDATA);
  221. ltq_ebu_w32(priv->sfcmd
  222. | (len<<SFCMD_DLEN_OFFSET),
  223. SFCMD);
  224. len = 0;
  225. val = 0;
  226. priv->sfcmd &= ~(SFCMD_ALEN_MASK
  227. | SFCMD_DUMLEN_MASK);
  228. }
  229. } while (bytelen);
  230. state = state_end;
  231. break;
  232. }
  233. case state_read:
  234. {
  235. /* read data */
  236. priv->sfcmd &= ~SFCMD_DIR_WRITE;
  237. do {
  238. if ((flags & FALCON_SPI_XFER_END)
  239. && (bytelen <= 4)) {
  240. priv->sfcmd &=
  241. ~SFCMD_KEEP_CS_KEEP_SELECTED;
  242. }
  243. len = (bytelen > 4) ? 4 : bytelen;
  244. bytelen -= len;
  245. ltq_ebu_w32(priv->sfcmd
  246. | (len << SFCMD_DLEN_OFFSET), SFCMD);
  247. priv->sfcmd &= ~(SFCMD_ALEN_MASK
  248. | SFCMD_DUMLEN_MASK);
  249. do {
  250. val = ltq_ebu_r32(SFSTAT);
  251. if (val & SFSTAT_CMD_ERR) {
  252. /* reset error status */
  253. dev_err(dev, "SFSTAT: CMD_ERR");
  254. dev_err(dev, " (%x)\n", val);
  255. ltq_ebu_w32(SFSTAT_CMD_ERR,
  256. SFSTAT);
  257. return -EBADE;
  258. }
  259. } while (val & SFSTAT_CMD_PEND);
  260. val = ltq_ebu_r32(SFDATA);
  261. do {
  262. *rxp = (val & 0xFF);
  263. rxp++;
  264. val >>= 8;
  265. len--;
  266. } while (len);
  267. } while (bytelen);
  268. state = state_end;
  269. break;
  270. }
  271. case state_disable_cs:
  272. {
  273. priv->sfcmd &= ~SFCMD_KEEP_CS_KEEP_SELECTED;
  274. ltq_ebu_w32(priv->sfcmd | (0 << SFCMD_DLEN_OFFSET),
  275. SFCMD);
  276. val = ltq_ebu_r32(SFSTAT);
  277. if (val & SFSTAT_CMD_ERR) {
  278. /* reset error status */
  279. dev_err(dev, "SFSTAT: CMD_ERR (%x)\n", val);
  280. ltq_ebu_w32(SFSTAT_CMD_ERR, SFSTAT);
  281. return -EBADE;
  282. }
  283. state = state_end;
  284. break;
  285. }
  286. case state_end:
  287. break;
  288. }
  289. } while (state != state_end);
  290. return 0;
  291. }
  292. static int falcon_sflash_setup(struct spi_device *spi)
  293. {
  294. unsigned int i;
  295. unsigned long flags;
  296. spin_lock_irqsave(&ebu_lock, flags);
  297. if (spi->max_speed_hz >= CLOCK_100M) {
  298. /* set EBU clock to 100 MHz */
  299. ltq_sys1_w32_mask(0, EBUCC_EBUDIV_SELF100, EBUCC);
  300. i = 1; /* divider */
  301. } else {
  302. /* set EBU clock to 50 MHz */
  303. ltq_sys1_w32_mask(EBUCC_EBUDIV_SELF100, 0, EBUCC);
  304. /* search for suitable divider */
  305. for (i = 1; i < 7; i++) {
  306. if (CLOCK_50M / i <= spi->max_speed_hz)
  307. break;
  308. }
  309. }
  310. /* setup period of serial clock */
  311. ltq_ebu_w32_mask(SFTIME_SCKF_POS_MASK
  312. | SFTIME_SCKR_POS_MASK
  313. | SFTIME_SCK_PER_MASK,
  314. (i << SFTIME_SCKR_POS_OFFSET)
  315. | (i << (SFTIME_SCK_PER_OFFSET + 1)),
  316. SFTIME);
  317. /*
  318. * set some bits of unused_wd, to not trigger HOLD/WP
  319. * signals on non QUAD flashes
  320. */
  321. ltq_ebu_w32((SFIO_UNUSED_WD_MASK & (0x8 | 0x4)), SFIO);
  322. ltq_ebu_w32(BUSRCON0_AGEN_SERIAL_FLASH | BUSRCON0_PORTW_8_BIT_MUX,
  323. BUSRCON0);
  324. ltq_ebu_w32(BUSWCON0_AGEN_SERIAL_FLASH, BUSWCON0);
  325. /* set address wrap around to maximum for 24-bit addresses */
  326. ltq_ebu_w32_mask(SFCON_DEV_SIZE_MASK, SFCON_DEV_SIZE_A23_0, SFCON);
  327. spin_unlock_irqrestore(&ebu_lock, flags);
  328. return 0;
  329. }
  330. static int falcon_sflash_xfer_one(struct spi_master *master,
  331. struct spi_message *m)
  332. {
  333. struct falcon_sflash *priv = spi_master_get_devdata(master);
  334. struct spi_transfer *t;
  335. unsigned long spi_flags;
  336. unsigned long flags;
  337. int ret = 0;
  338. priv->sfcmd = 0;
  339. m->actual_length = 0;
  340. spi_flags = FALCON_SPI_XFER_BEGIN;
  341. list_for_each_entry(t, &m->transfers, transfer_list) {
  342. if (list_is_last(&t->transfer_list, &m->transfers))
  343. spi_flags |= FALCON_SPI_XFER_END;
  344. spin_lock_irqsave(&ebu_lock, flags);
  345. ret = falcon_sflash_xfer(m->spi, t, spi_flags);
  346. spin_unlock_irqrestore(&ebu_lock, flags);
  347. if (ret)
  348. break;
  349. m->actual_length += t->len;
  350. WARN_ON(t->delay_usecs || t->delay.value || t->cs_change);
  351. spi_flags = 0;
  352. }
  353. m->status = ret;
  354. spi_finalize_current_message(master);
  355. return 0;
  356. }
  357. static int falcon_sflash_probe(struct platform_device *pdev)
  358. {
  359. struct falcon_sflash *priv;
  360. struct spi_master *master;
  361. int ret;
  362. master = spi_alloc_master(&pdev->dev, sizeof(*priv));
  363. if (!master)
  364. return -ENOMEM;
  365. priv = spi_master_get_devdata(master);
  366. priv->master = master;
  367. master->mode_bits = SPI_MODE_3;
  368. master->flags = SPI_MASTER_HALF_DUPLEX;
  369. master->setup = falcon_sflash_setup;
  370. master->transfer_one_message = falcon_sflash_xfer_one;
  371. master->dev.of_node = pdev->dev.of_node;
  372. ret = devm_spi_register_master(&pdev->dev, master);
  373. if (ret)
  374. spi_master_put(master);
  375. return ret;
  376. }
  377. static const struct of_device_id falcon_sflash_match[] = {
  378. { .compatible = "lantiq,sflash-falcon" },
  379. {},
  380. };
  381. MODULE_DEVICE_TABLE(of, falcon_sflash_match);
  382. static struct platform_driver falcon_sflash_driver = {
  383. .probe = falcon_sflash_probe,
  384. .driver = {
  385. .name = DRV_NAME,
  386. .of_match_table = falcon_sflash_match,
  387. }
  388. };
  389. module_platform_driver(falcon_sflash_driver);
  390. MODULE_LICENSE("GPL");
  391. MODULE_DESCRIPTION("Lantiq Falcon SPI/SFLASH controller driver");