spi-dw-pci.c 4.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * PCI interface driver for DW SPI Core
  4. *
  5. * Copyright (c) 2009, 2014 Intel Corporation.
  6. */
  7. #include <linux/pci.h>
  8. #include <linux/pm_runtime.h>
  9. #include <linux/slab.h>
  10. #include <linux/spi/spi.h>
  11. #include <linux/module.h>
  12. #include "spi-dw.h"
  13. #define DRIVER_NAME "dw_spi_pci"
  14. /* HW info for MRST Clk Control Unit, 32b reg per controller */
  15. #define MRST_SPI_CLK_BASE 100000000 /* 100m */
  16. #define MRST_CLK_SPI_REG 0xff11d86c
  17. #define CLK_SPI_BDIV_OFFSET 0
  18. #define CLK_SPI_BDIV_MASK 0x00000007
  19. #define CLK_SPI_CDIV_OFFSET 9
  20. #define CLK_SPI_CDIV_MASK 0x00000e00
  21. #define CLK_SPI_DISABLE_OFFSET 8
  22. struct spi_pci_desc {
  23. int (*setup)(struct dw_spi *);
  24. u16 num_cs;
  25. u16 bus_num;
  26. u32 max_freq;
  27. };
  28. static int spi_mid_init(struct dw_spi *dws)
  29. {
  30. void __iomem *clk_reg;
  31. u32 clk_cdiv;
  32. clk_reg = ioremap(MRST_CLK_SPI_REG, 16);
  33. if (!clk_reg)
  34. return -ENOMEM;
  35. /* Get SPI controller operating freq info */
  36. clk_cdiv = readl(clk_reg + dws->bus_num * sizeof(u32));
  37. clk_cdiv &= CLK_SPI_CDIV_MASK;
  38. clk_cdiv >>= CLK_SPI_CDIV_OFFSET;
  39. dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);
  40. iounmap(clk_reg);
  41. dw_spi_dma_setup_mfld(dws);
  42. return 0;
  43. }
  44. static int spi_generic_init(struct dw_spi *dws)
  45. {
  46. dw_spi_dma_setup_generic(dws);
  47. return 0;
  48. }
  49. static struct spi_pci_desc spi_pci_mid_desc_1 = {
  50. .setup = spi_mid_init,
  51. .num_cs = 5,
  52. .bus_num = 0,
  53. };
  54. static struct spi_pci_desc spi_pci_mid_desc_2 = {
  55. .setup = spi_mid_init,
  56. .num_cs = 2,
  57. .bus_num = 1,
  58. };
  59. static struct spi_pci_desc spi_pci_ehl_desc = {
  60. .setup = spi_generic_init,
  61. .num_cs = 2,
  62. .bus_num = -1,
  63. .max_freq = 100000000,
  64. };
  65. static int spi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  66. {
  67. struct dw_spi *dws;
  68. struct spi_pci_desc *desc = (struct spi_pci_desc *)ent->driver_data;
  69. int pci_bar = 0;
  70. int ret;
  71. ret = pcim_enable_device(pdev);
  72. if (ret)
  73. return ret;
  74. dws = devm_kzalloc(&pdev->dev, sizeof(*dws), GFP_KERNEL);
  75. if (!dws)
  76. return -ENOMEM;
  77. /* Get basic io resource and map it */
  78. dws->paddr = pci_resource_start(pdev, pci_bar);
  79. pci_set_master(pdev);
  80. ret = pcim_iomap_regions(pdev, 1 << pci_bar, pci_name(pdev));
  81. if (ret)
  82. return ret;
  83. ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
  84. if (ret < 0)
  85. return ret;
  86. dws->regs = pcim_iomap_table(pdev)[pci_bar];
  87. dws->irq = pci_irq_vector(pdev, 0);
  88. /*
  89. * Specific handling for platforms, like dma setup,
  90. * clock rate, FIFO depth.
  91. */
  92. if (desc) {
  93. dws->num_cs = desc->num_cs;
  94. dws->bus_num = desc->bus_num;
  95. dws->max_freq = desc->max_freq;
  96. if (desc->setup) {
  97. ret = desc->setup(dws);
  98. if (ret)
  99. goto err_free_irq_vectors;
  100. }
  101. } else {
  102. ret = -ENODEV;
  103. goto err_free_irq_vectors;
  104. }
  105. ret = dw_spi_add_host(&pdev->dev, dws);
  106. if (ret)
  107. goto err_free_irq_vectors;
  108. /* PCI hook and SPI hook use the same drv data */
  109. pci_set_drvdata(pdev, dws);
  110. dev_info(&pdev->dev, "found PCI SPI controller(ID: %04x:%04x)\n",
  111. pdev->vendor, pdev->device);
  112. pm_runtime_set_autosuspend_delay(&pdev->dev, 1000);
  113. pm_runtime_use_autosuspend(&pdev->dev);
  114. pm_runtime_put_autosuspend(&pdev->dev);
  115. pm_runtime_allow(&pdev->dev);
  116. return 0;
  117. err_free_irq_vectors:
  118. pci_free_irq_vectors(pdev);
  119. return ret;
  120. }
  121. static void spi_pci_remove(struct pci_dev *pdev)
  122. {
  123. struct dw_spi *dws = pci_get_drvdata(pdev);
  124. pm_runtime_forbid(&pdev->dev);
  125. pm_runtime_get_noresume(&pdev->dev);
  126. dw_spi_remove_host(dws);
  127. pci_free_irq_vectors(pdev);
  128. }
  129. #ifdef CONFIG_PM_SLEEP
  130. static int spi_suspend(struct device *dev)
  131. {
  132. struct dw_spi *dws = dev_get_drvdata(dev);
  133. return dw_spi_suspend_host(dws);
  134. }
  135. static int spi_resume(struct device *dev)
  136. {
  137. struct dw_spi *dws = dev_get_drvdata(dev);
  138. return dw_spi_resume_host(dws);
  139. }
  140. #endif
  141. static SIMPLE_DEV_PM_OPS(dw_spi_pm_ops, spi_suspend, spi_resume);
  142. static const struct pci_device_id pci_ids[] = {
  143. /* Intel MID platform SPI controller 0 */
  144. /*
  145. * The access to the device 8086:0801 is disabled by HW, since it's
  146. * exclusively used by SCU to communicate with MSIC.
  147. */
  148. /* Intel MID platform SPI controller 1 */
  149. { PCI_VDEVICE(INTEL, 0x0800), (kernel_ulong_t)&spi_pci_mid_desc_1},
  150. /* Intel MID platform SPI controller 2 */
  151. { PCI_VDEVICE(INTEL, 0x0812), (kernel_ulong_t)&spi_pci_mid_desc_2},
  152. /* Intel Elkhart Lake PSE SPI controllers */
  153. { PCI_VDEVICE(INTEL, 0x4b84), (kernel_ulong_t)&spi_pci_ehl_desc},
  154. { PCI_VDEVICE(INTEL, 0x4b85), (kernel_ulong_t)&spi_pci_ehl_desc},
  155. { PCI_VDEVICE(INTEL, 0x4b86), (kernel_ulong_t)&spi_pci_ehl_desc},
  156. { PCI_VDEVICE(INTEL, 0x4b87), (kernel_ulong_t)&spi_pci_ehl_desc},
  157. {},
  158. };
  159. MODULE_DEVICE_TABLE(pci, pci_ids);
  160. static struct pci_driver dw_spi_driver = {
  161. .name = DRIVER_NAME,
  162. .id_table = pci_ids,
  163. .probe = spi_pci_probe,
  164. .remove = spi_pci_remove,
  165. .driver = {
  166. .pm = &dw_spi_pm_ops,
  167. },
  168. };
  169. module_pci_driver(dw_spi_driver);
  170. MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
  171. MODULE_DESCRIPTION("PCI interface driver for DW SPI Core");
  172. MODULE_LICENSE("GPL v2");