spi-dw-bt1.c 8.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. //
  3. // Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
  4. //
  5. // Authors:
  6. // Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
  7. // Serge Semin <Sergey.Semin@baikalelectronics.ru>
  8. //
  9. // Baikal-T1 DW APB SPI and System Boot SPI driver
  10. //
  11. #include <linux/clk.h>
  12. #include <linux/cpumask.h>
  13. #include <linux/err.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/module.h>
  16. #include <linux/mux/consumer.h>
  17. #include <linux/of.h>
  18. #include <linux/of_platform.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/pm_runtime.h>
  21. #include <linux/property.h>
  22. #include <linux/slab.h>
  23. #include <linux/spi/spi-mem.h>
  24. #include <linux/spi/spi.h>
  25. #include "spi-dw.h"
  26. #define BT1_BOOT_DIRMAP 0
  27. #define BT1_BOOT_REGS 1
  28. struct dw_spi_bt1 {
  29. struct dw_spi dws;
  30. struct clk *clk;
  31. struct mux_control *mux;
  32. #ifdef CONFIG_SPI_DW_BT1_DIRMAP
  33. void __iomem *map;
  34. resource_size_t map_len;
  35. #endif
  36. };
  37. #define to_dw_spi_bt1(_ctlr) \
  38. container_of(spi_controller_get_devdata(_ctlr), struct dw_spi_bt1, dws)
  39. typedef int (*dw_spi_bt1_init_cb)(struct platform_device *pdev,
  40. struct dw_spi_bt1 *dwsbt1);
  41. #ifdef CONFIG_SPI_DW_BT1_DIRMAP
  42. static int dw_spi_bt1_dirmap_create(struct spi_mem_dirmap_desc *desc)
  43. {
  44. struct dw_spi_bt1 *dwsbt1 = to_dw_spi_bt1(desc->mem->spi->controller);
  45. if (!dwsbt1->map ||
  46. !dwsbt1->dws.mem_ops.supports_op(desc->mem, &desc->info.op_tmpl))
  47. return -EOPNOTSUPP;
  48. /*
  49. * Make sure the requested region doesn't go out of the physically
  50. * mapped flash memory bounds and the operation is read-only.
  51. */
  52. if (desc->info.offset + desc->info.length > dwsbt1->map_len ||
  53. desc->info.op_tmpl.data.dir != SPI_MEM_DATA_IN)
  54. return -EOPNOTSUPP;
  55. return 0;
  56. }
  57. /*
  58. * Directly mapped SPI memory region is only accessible in the dword chunks.
  59. * That's why we have to create a dedicated read-method to copy data from there
  60. * to the passed buffer.
  61. */
  62. static void dw_spi_bt1_dirmap_copy_from_map(void *to, void __iomem *from, size_t len)
  63. {
  64. size_t shift, chunk;
  65. u32 data;
  66. /*
  67. * We split the copying up into the next three stages: unaligned head,
  68. * aligned body, unaligned tail.
  69. */
  70. shift = (size_t)from & 0x3;
  71. if (shift) {
  72. chunk = min_t(size_t, 4 - shift, len);
  73. data = readl_relaxed(from - shift);
  74. memcpy(to, (char *)&data + shift, chunk);
  75. from += chunk;
  76. to += chunk;
  77. len -= chunk;
  78. }
  79. while (len >= 4) {
  80. data = readl_relaxed(from);
  81. memcpy(to, &data, 4);
  82. from += 4;
  83. to += 4;
  84. len -= 4;
  85. }
  86. if (len) {
  87. data = readl_relaxed(from);
  88. memcpy(to, &data, len);
  89. }
  90. }
  91. static ssize_t dw_spi_bt1_dirmap_read(struct spi_mem_dirmap_desc *desc,
  92. u64 offs, size_t len, void *buf)
  93. {
  94. struct dw_spi_bt1 *dwsbt1 = to_dw_spi_bt1(desc->mem->spi->controller);
  95. struct dw_spi *dws = &dwsbt1->dws;
  96. struct spi_mem *mem = desc->mem;
  97. struct dw_spi_cfg cfg;
  98. int ret;
  99. /*
  100. * Make sure the requested operation length is valid. Truncate the
  101. * length if it's greater than the length of the MMIO region.
  102. */
  103. if (offs >= dwsbt1->map_len || !len)
  104. return 0;
  105. len = min_t(size_t, len, dwsbt1->map_len - offs);
  106. /* Collect the controller configuration required by the operation */
  107. cfg.tmode = SPI_TMOD_EPROMREAD;
  108. cfg.dfs = 8;
  109. cfg.ndf = 4;
  110. cfg.freq = mem->spi->max_speed_hz;
  111. /* Make sure the corresponding CS is de-asserted on transmission */
  112. dw_spi_set_cs(mem->spi, false);
  113. spi_enable_chip(dws, 0);
  114. dw_spi_update_config(dws, mem->spi, &cfg);
  115. spi_umask_intr(dws, SPI_INT_RXFI);
  116. spi_enable_chip(dws, 1);
  117. /*
  118. * Enable the transparent mode of the System Boot Controller.
  119. * The SPI core IO should have been locked before calling this method
  120. * so noone would be touching the controller' registers during the
  121. * dirmap operation.
  122. */
  123. ret = mux_control_select(dwsbt1->mux, BT1_BOOT_DIRMAP);
  124. if (ret)
  125. return ret;
  126. dw_spi_bt1_dirmap_copy_from_map(buf, dwsbt1->map + offs, len);
  127. mux_control_deselect(dwsbt1->mux);
  128. dw_spi_set_cs(mem->spi, true);
  129. ret = dw_spi_check_status(dws, true);
  130. return ret ?: len;
  131. }
  132. #endif /* CONFIG_SPI_DW_BT1_DIRMAP */
  133. static int dw_spi_bt1_std_init(struct platform_device *pdev,
  134. struct dw_spi_bt1 *dwsbt1)
  135. {
  136. struct dw_spi *dws = &dwsbt1->dws;
  137. dws->irq = platform_get_irq(pdev, 0);
  138. if (dws->irq < 0)
  139. return dws->irq;
  140. dws->num_cs = 4;
  141. /*
  142. * Baikal-T1 Normal SPI Controllers don't always keep up with full SPI
  143. * bus speed especially when it comes to the concurrent access to the
  144. * APB bus resources. Thus we have no choice but to set a constraint on
  145. * the SPI bus frequency for the memory operations which require to
  146. * read/write data as fast as possible.
  147. */
  148. dws->max_mem_freq = 20000000U;
  149. dw_spi_dma_setup_generic(dws);
  150. return 0;
  151. }
  152. static int dw_spi_bt1_sys_init(struct platform_device *pdev,
  153. struct dw_spi_bt1 *dwsbt1)
  154. {
  155. struct resource *mem __maybe_unused;
  156. struct dw_spi *dws = &dwsbt1->dws;
  157. /*
  158. * Baikal-T1 System Boot Controller is equipped with a mux, which
  159. * switches between the directly mapped SPI flash access mode and
  160. * IO access to the DW APB SSI registers. Note the mux controller
  161. * must be setup to preserve the registers being accessible by default
  162. * (on idle-state).
  163. */
  164. dwsbt1->mux = devm_mux_control_get(&pdev->dev, NULL);
  165. if (IS_ERR(dwsbt1->mux))
  166. return PTR_ERR(dwsbt1->mux);
  167. /*
  168. * Directly mapped SPI flash memory is a 16MB MMIO region, which can be
  169. * used to access a peripheral memory device just by reading/writing
  170. * data from/to it. Note the system APB bus will stall during each IO
  171. * from/to the dirmap region until the operation is finished. So don't
  172. * use it concurrently with time-critical tasks (like the SPI memory
  173. * operations implemented in the DW APB SSI driver).
  174. */
  175. #ifdef CONFIG_SPI_DW_BT1_DIRMAP
  176. mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  177. if (mem) {
  178. dwsbt1->map = devm_ioremap_resource(&pdev->dev, mem);
  179. if (!IS_ERR(dwsbt1->map)) {
  180. dwsbt1->map_len = (mem->end - mem->start + 1);
  181. dws->mem_ops.dirmap_create = dw_spi_bt1_dirmap_create;
  182. dws->mem_ops.dirmap_read = dw_spi_bt1_dirmap_read;
  183. } else {
  184. dwsbt1->map = NULL;
  185. }
  186. }
  187. #endif /* CONFIG_SPI_DW_BT1_DIRMAP */
  188. /*
  189. * There is no IRQ, no DMA and just one CS available on the System Boot
  190. * SPI controller.
  191. */
  192. dws->irq = IRQ_NOTCONNECTED;
  193. dws->num_cs = 1;
  194. /*
  195. * Baikal-T1 System Boot SPI Controller doesn't keep up with the full
  196. * SPI bus speed due to relatively slow APB bus and races for it'
  197. * resources from different CPUs. The situation is worsen by a small
  198. * FIFOs depth (just 8 words). It works better in a single CPU mode
  199. * though, but still tends to be not fast enough at low CPU
  200. * frequencies.
  201. */
  202. if (num_possible_cpus() > 1)
  203. dws->max_mem_freq = 10000000U;
  204. else
  205. dws->max_mem_freq = 20000000U;
  206. return 0;
  207. }
  208. static int dw_spi_bt1_probe(struct platform_device *pdev)
  209. {
  210. dw_spi_bt1_init_cb init_func;
  211. struct dw_spi_bt1 *dwsbt1;
  212. struct resource *mem;
  213. struct dw_spi *dws;
  214. int ret;
  215. dwsbt1 = devm_kzalloc(&pdev->dev, sizeof(struct dw_spi_bt1), GFP_KERNEL);
  216. if (!dwsbt1)
  217. return -ENOMEM;
  218. dws = &dwsbt1->dws;
  219. dws->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
  220. if (IS_ERR(dws->regs))
  221. return PTR_ERR(dws->regs);
  222. dws->paddr = mem->start;
  223. dwsbt1->clk = devm_clk_get(&pdev->dev, NULL);
  224. if (IS_ERR(dwsbt1->clk))
  225. return PTR_ERR(dwsbt1->clk);
  226. ret = clk_prepare_enable(dwsbt1->clk);
  227. if (ret)
  228. return ret;
  229. dws->bus_num = pdev->id;
  230. dws->reg_io_width = 4;
  231. dws->max_freq = clk_get_rate(dwsbt1->clk);
  232. if (!dws->max_freq) {
  233. ret = -EINVAL;
  234. goto err_disable_clk;
  235. }
  236. init_func = device_get_match_data(&pdev->dev);
  237. ret = init_func(pdev, dwsbt1);
  238. if (ret)
  239. goto err_disable_clk;
  240. pm_runtime_enable(&pdev->dev);
  241. ret = dw_spi_add_host(&pdev->dev, dws);
  242. if (ret)
  243. goto err_disable_clk;
  244. platform_set_drvdata(pdev, dwsbt1);
  245. return 0;
  246. err_disable_clk:
  247. clk_disable_unprepare(dwsbt1->clk);
  248. return ret;
  249. }
  250. static int dw_spi_bt1_remove(struct platform_device *pdev)
  251. {
  252. struct dw_spi_bt1 *dwsbt1 = platform_get_drvdata(pdev);
  253. dw_spi_remove_host(&dwsbt1->dws);
  254. pm_runtime_disable(&pdev->dev);
  255. clk_disable_unprepare(dwsbt1->clk);
  256. return 0;
  257. }
  258. static const struct of_device_id dw_spi_bt1_of_match[] = {
  259. { .compatible = "baikal,bt1-ssi", .data = dw_spi_bt1_std_init},
  260. { .compatible = "baikal,bt1-sys-ssi", .data = dw_spi_bt1_sys_init},
  261. { }
  262. };
  263. MODULE_DEVICE_TABLE(of, dw_spi_bt1_of_match);
  264. static struct platform_driver dw_spi_bt1_driver = {
  265. .probe = dw_spi_bt1_probe,
  266. .remove = dw_spi_bt1_remove,
  267. .driver = {
  268. .name = "bt1-sys-ssi",
  269. .of_match_table = dw_spi_bt1_of_match,
  270. },
  271. };
  272. module_platform_driver(dw_spi_bt1_driver);
  273. MODULE_AUTHOR("Serge Semin <Sergey.Semin@baikalelectronics.ru>");
  274. MODULE_DESCRIPTION("Baikal-T1 System Boot SPI Controller driver");
  275. MODULE_LICENSE("GPL v2");