spi-dln2.c 21 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Driver for the Diolan DLN-2 USB-SPI adapter
  4. *
  5. * Copyright (c) 2014 Intel Corporation
  6. */
  7. #include <linux/kernel.h>
  8. #include <linux/module.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/mfd/dln2.h>
  11. #include <linux/spi/spi.h>
  12. #include <linux/pm_runtime.h>
  13. #include <asm/unaligned.h>
  14. #define DLN2_SPI_MODULE_ID 0x02
  15. #define DLN2_SPI_CMD(cmd) DLN2_CMD(cmd, DLN2_SPI_MODULE_ID)
  16. /* SPI commands */
  17. #define DLN2_SPI_GET_PORT_COUNT DLN2_SPI_CMD(0x00)
  18. #define DLN2_SPI_ENABLE DLN2_SPI_CMD(0x11)
  19. #define DLN2_SPI_DISABLE DLN2_SPI_CMD(0x12)
  20. #define DLN2_SPI_IS_ENABLED DLN2_SPI_CMD(0x13)
  21. #define DLN2_SPI_SET_MODE DLN2_SPI_CMD(0x14)
  22. #define DLN2_SPI_GET_MODE DLN2_SPI_CMD(0x15)
  23. #define DLN2_SPI_SET_FRAME_SIZE DLN2_SPI_CMD(0x16)
  24. #define DLN2_SPI_GET_FRAME_SIZE DLN2_SPI_CMD(0x17)
  25. #define DLN2_SPI_SET_FREQUENCY DLN2_SPI_CMD(0x18)
  26. #define DLN2_SPI_GET_FREQUENCY DLN2_SPI_CMD(0x19)
  27. #define DLN2_SPI_READ_WRITE DLN2_SPI_CMD(0x1A)
  28. #define DLN2_SPI_READ DLN2_SPI_CMD(0x1B)
  29. #define DLN2_SPI_WRITE DLN2_SPI_CMD(0x1C)
  30. #define DLN2_SPI_SET_DELAY_BETWEEN_SS DLN2_SPI_CMD(0x20)
  31. #define DLN2_SPI_GET_DELAY_BETWEEN_SS DLN2_SPI_CMD(0x21)
  32. #define DLN2_SPI_SET_DELAY_AFTER_SS DLN2_SPI_CMD(0x22)
  33. #define DLN2_SPI_GET_DELAY_AFTER_SS DLN2_SPI_CMD(0x23)
  34. #define DLN2_SPI_SET_DELAY_BETWEEN_FRAMES DLN2_SPI_CMD(0x24)
  35. #define DLN2_SPI_GET_DELAY_BETWEEN_FRAMES DLN2_SPI_CMD(0x25)
  36. #define DLN2_SPI_SET_SS DLN2_SPI_CMD(0x26)
  37. #define DLN2_SPI_GET_SS DLN2_SPI_CMD(0x27)
  38. #define DLN2_SPI_RELEASE_SS DLN2_SPI_CMD(0x28)
  39. #define DLN2_SPI_SS_VARIABLE_ENABLE DLN2_SPI_CMD(0x2B)
  40. #define DLN2_SPI_SS_VARIABLE_DISABLE DLN2_SPI_CMD(0x2C)
  41. #define DLN2_SPI_SS_VARIABLE_IS_ENABLED DLN2_SPI_CMD(0x2D)
  42. #define DLN2_SPI_SS_AAT_ENABLE DLN2_SPI_CMD(0x2E)
  43. #define DLN2_SPI_SS_AAT_DISABLE DLN2_SPI_CMD(0x2F)
  44. #define DLN2_SPI_SS_AAT_IS_ENABLED DLN2_SPI_CMD(0x30)
  45. #define DLN2_SPI_SS_BETWEEN_FRAMES_ENABLE DLN2_SPI_CMD(0x31)
  46. #define DLN2_SPI_SS_BETWEEN_FRAMES_DISABLE DLN2_SPI_CMD(0x32)
  47. #define DLN2_SPI_SS_BETWEEN_FRAMES_IS_ENABLED DLN2_SPI_CMD(0x33)
  48. #define DLN2_SPI_SET_CPHA DLN2_SPI_CMD(0x34)
  49. #define DLN2_SPI_GET_CPHA DLN2_SPI_CMD(0x35)
  50. #define DLN2_SPI_SET_CPOL DLN2_SPI_CMD(0x36)
  51. #define DLN2_SPI_GET_CPOL DLN2_SPI_CMD(0x37)
  52. #define DLN2_SPI_SS_MULTI_ENABLE DLN2_SPI_CMD(0x38)
  53. #define DLN2_SPI_SS_MULTI_DISABLE DLN2_SPI_CMD(0x39)
  54. #define DLN2_SPI_SS_MULTI_IS_ENABLED DLN2_SPI_CMD(0x3A)
  55. #define DLN2_SPI_GET_SUPPORTED_MODES DLN2_SPI_CMD(0x40)
  56. #define DLN2_SPI_GET_SUPPORTED_CPHA_VALUES DLN2_SPI_CMD(0x41)
  57. #define DLN2_SPI_GET_SUPPORTED_CPOL_VALUES DLN2_SPI_CMD(0x42)
  58. #define DLN2_SPI_GET_SUPPORTED_FRAME_SIZES DLN2_SPI_CMD(0x43)
  59. #define DLN2_SPI_GET_SS_COUNT DLN2_SPI_CMD(0x44)
  60. #define DLN2_SPI_GET_MIN_FREQUENCY DLN2_SPI_CMD(0x45)
  61. #define DLN2_SPI_GET_MAX_FREQUENCY DLN2_SPI_CMD(0x46)
  62. #define DLN2_SPI_GET_MIN_DELAY_BETWEEN_SS DLN2_SPI_CMD(0x47)
  63. #define DLN2_SPI_GET_MAX_DELAY_BETWEEN_SS DLN2_SPI_CMD(0x48)
  64. #define DLN2_SPI_GET_MIN_DELAY_AFTER_SS DLN2_SPI_CMD(0x49)
  65. #define DLN2_SPI_GET_MAX_DELAY_AFTER_SS DLN2_SPI_CMD(0x4A)
  66. #define DLN2_SPI_GET_MIN_DELAY_BETWEEN_FRAMES DLN2_SPI_CMD(0x4B)
  67. #define DLN2_SPI_GET_MAX_DELAY_BETWEEN_FRAMES DLN2_SPI_CMD(0x4C)
  68. #define DLN2_SPI_MAX_XFER_SIZE 256
  69. #define DLN2_SPI_BUF_SIZE (DLN2_SPI_MAX_XFER_SIZE + 16)
  70. #define DLN2_SPI_ATTR_LEAVE_SS_LOW BIT(0)
  71. #define DLN2_TRANSFERS_WAIT_COMPLETE 1
  72. #define DLN2_TRANSFERS_CANCEL 0
  73. #define DLN2_RPM_AUTOSUSPEND_TIMEOUT 2000
  74. struct dln2_spi {
  75. struct platform_device *pdev;
  76. struct spi_master *master;
  77. u8 port;
  78. /*
  79. * This buffer will be used mainly for read/write operations. Since
  80. * they're quite large, we cannot use the stack. Protection is not
  81. * needed because all SPI communication is serialized by the SPI core.
  82. */
  83. void *buf;
  84. u8 bpw;
  85. u32 speed;
  86. u16 mode;
  87. u8 cs;
  88. };
  89. /*
  90. * Enable/Disable SPI module. The disable command will wait for transfers to
  91. * complete first.
  92. */
  93. static int dln2_spi_enable(struct dln2_spi *dln2, bool enable)
  94. {
  95. u16 cmd;
  96. struct {
  97. u8 port;
  98. u8 wait_for_completion;
  99. } tx;
  100. unsigned len = sizeof(tx);
  101. tx.port = dln2->port;
  102. if (enable) {
  103. cmd = DLN2_SPI_ENABLE;
  104. len -= sizeof(tx.wait_for_completion);
  105. } else {
  106. tx.wait_for_completion = DLN2_TRANSFERS_WAIT_COMPLETE;
  107. cmd = DLN2_SPI_DISABLE;
  108. }
  109. return dln2_transfer_tx(dln2->pdev, cmd, &tx, len);
  110. }
  111. /*
  112. * Select/unselect multiple CS lines. The selected lines will be automatically
  113. * toggled LOW/HIGH by the board firmware during transfers, provided they're
  114. * enabled first.
  115. *
  116. * Ex: cs_mask = 0x03 -> CS0 & CS1 will be selected and the next WR/RD operation
  117. * will toggle the lines LOW/HIGH automatically.
  118. */
  119. static int dln2_spi_cs_set(struct dln2_spi *dln2, u8 cs_mask)
  120. {
  121. struct {
  122. u8 port;
  123. u8 cs;
  124. } tx;
  125. tx.port = dln2->port;
  126. /*
  127. * According to Diolan docs, "a slave device can be selected by changing
  128. * the corresponding bit value to 0". The rest must be set to 1. Hence
  129. * the bitwise NOT in front.
  130. */
  131. tx.cs = ~cs_mask;
  132. return dln2_transfer_tx(dln2->pdev, DLN2_SPI_SET_SS, &tx, sizeof(tx));
  133. }
  134. /*
  135. * Select one CS line. The other lines will be un-selected.
  136. */
  137. static int dln2_spi_cs_set_one(struct dln2_spi *dln2, u8 cs)
  138. {
  139. return dln2_spi_cs_set(dln2, BIT(cs));
  140. }
  141. /*
  142. * Enable/disable CS lines for usage. The module has to be disabled first.
  143. */
  144. static int dln2_spi_cs_enable(struct dln2_spi *dln2, u8 cs_mask, bool enable)
  145. {
  146. struct {
  147. u8 port;
  148. u8 cs;
  149. } tx;
  150. u16 cmd;
  151. tx.port = dln2->port;
  152. tx.cs = cs_mask;
  153. cmd = enable ? DLN2_SPI_SS_MULTI_ENABLE : DLN2_SPI_SS_MULTI_DISABLE;
  154. return dln2_transfer_tx(dln2->pdev, cmd, &tx, sizeof(tx));
  155. }
  156. static int dln2_spi_cs_enable_all(struct dln2_spi *dln2, bool enable)
  157. {
  158. u8 cs_mask = GENMASK(dln2->master->num_chipselect - 1, 0);
  159. return dln2_spi_cs_enable(dln2, cs_mask, enable);
  160. }
  161. static int dln2_spi_get_cs_num(struct dln2_spi *dln2, u16 *cs_num)
  162. {
  163. int ret;
  164. struct {
  165. u8 port;
  166. } tx;
  167. struct {
  168. __le16 cs_count;
  169. } rx;
  170. unsigned rx_len = sizeof(rx);
  171. tx.port = dln2->port;
  172. ret = dln2_transfer(dln2->pdev, DLN2_SPI_GET_SS_COUNT, &tx, sizeof(tx),
  173. &rx, &rx_len);
  174. if (ret < 0)
  175. return ret;
  176. if (rx_len < sizeof(rx))
  177. return -EPROTO;
  178. *cs_num = le16_to_cpu(rx.cs_count);
  179. dev_dbg(&dln2->pdev->dev, "cs_num = %d\n", *cs_num);
  180. return 0;
  181. }
  182. static int dln2_spi_get_speed(struct dln2_spi *dln2, u16 cmd, u32 *freq)
  183. {
  184. int ret;
  185. struct {
  186. u8 port;
  187. } tx;
  188. struct {
  189. __le32 speed;
  190. } rx;
  191. unsigned rx_len = sizeof(rx);
  192. tx.port = dln2->port;
  193. ret = dln2_transfer(dln2->pdev, cmd, &tx, sizeof(tx), &rx, &rx_len);
  194. if (ret < 0)
  195. return ret;
  196. if (rx_len < sizeof(rx))
  197. return -EPROTO;
  198. *freq = le32_to_cpu(rx.speed);
  199. return 0;
  200. }
  201. /*
  202. * Get bus min/max frequencies.
  203. */
  204. static int dln2_spi_get_speed_range(struct dln2_spi *dln2, u32 *fmin, u32 *fmax)
  205. {
  206. int ret;
  207. ret = dln2_spi_get_speed(dln2, DLN2_SPI_GET_MIN_FREQUENCY, fmin);
  208. if (ret < 0)
  209. return ret;
  210. ret = dln2_spi_get_speed(dln2, DLN2_SPI_GET_MAX_FREQUENCY, fmax);
  211. if (ret < 0)
  212. return ret;
  213. dev_dbg(&dln2->pdev->dev, "freq_min = %d, freq_max = %d\n",
  214. *fmin, *fmax);
  215. return 0;
  216. }
  217. /*
  218. * Set the bus speed. The module will automatically round down to the closest
  219. * available frequency and returns it. The module has to be disabled first.
  220. */
  221. static int dln2_spi_set_speed(struct dln2_spi *dln2, u32 speed)
  222. {
  223. int ret;
  224. struct {
  225. u8 port;
  226. __le32 speed;
  227. } __packed tx;
  228. struct {
  229. __le32 speed;
  230. } rx;
  231. int rx_len = sizeof(rx);
  232. tx.port = dln2->port;
  233. tx.speed = cpu_to_le32(speed);
  234. ret = dln2_transfer(dln2->pdev, DLN2_SPI_SET_FREQUENCY, &tx, sizeof(tx),
  235. &rx, &rx_len);
  236. if (ret < 0)
  237. return ret;
  238. if (rx_len < sizeof(rx))
  239. return -EPROTO;
  240. return 0;
  241. }
  242. /*
  243. * Change CPOL & CPHA. The module has to be disabled first.
  244. */
  245. static int dln2_spi_set_mode(struct dln2_spi *dln2, u8 mode)
  246. {
  247. struct {
  248. u8 port;
  249. u8 mode;
  250. } tx;
  251. tx.port = dln2->port;
  252. tx.mode = mode;
  253. return dln2_transfer_tx(dln2->pdev, DLN2_SPI_SET_MODE, &tx, sizeof(tx));
  254. }
  255. /*
  256. * Change frame size. The module has to be disabled first.
  257. */
  258. static int dln2_spi_set_bpw(struct dln2_spi *dln2, u8 bpw)
  259. {
  260. struct {
  261. u8 port;
  262. u8 bpw;
  263. } tx;
  264. tx.port = dln2->port;
  265. tx.bpw = bpw;
  266. return dln2_transfer_tx(dln2->pdev, DLN2_SPI_SET_FRAME_SIZE,
  267. &tx, sizeof(tx));
  268. }
  269. static int dln2_spi_get_supported_frame_sizes(struct dln2_spi *dln2,
  270. u32 *bpw_mask)
  271. {
  272. int ret;
  273. struct {
  274. u8 port;
  275. } tx;
  276. struct {
  277. u8 count;
  278. u8 frame_sizes[36];
  279. } *rx = dln2->buf;
  280. unsigned rx_len = sizeof(*rx);
  281. int i;
  282. tx.port = dln2->port;
  283. ret = dln2_transfer(dln2->pdev, DLN2_SPI_GET_SUPPORTED_FRAME_SIZES,
  284. &tx, sizeof(tx), rx, &rx_len);
  285. if (ret < 0)
  286. return ret;
  287. if (rx_len < sizeof(*rx))
  288. return -EPROTO;
  289. if (rx->count > ARRAY_SIZE(rx->frame_sizes))
  290. return -EPROTO;
  291. *bpw_mask = 0;
  292. for (i = 0; i < rx->count; i++)
  293. *bpw_mask |= BIT(rx->frame_sizes[i] - 1);
  294. dev_dbg(&dln2->pdev->dev, "bpw_mask = 0x%X\n", *bpw_mask);
  295. return 0;
  296. }
  297. /*
  298. * Copy the data to DLN2 buffer and change the byte order to LE, requested by
  299. * DLN2 module. SPI core makes sure that the data length is a multiple of word
  300. * size.
  301. */
  302. static int dln2_spi_copy_to_buf(u8 *dln2_buf, const u8 *src, u16 len, u8 bpw)
  303. {
  304. #ifdef __LITTLE_ENDIAN
  305. memcpy(dln2_buf, src, len);
  306. #else
  307. if (bpw <= 8) {
  308. memcpy(dln2_buf, src, len);
  309. } else if (bpw <= 16) {
  310. __le16 *d = (__le16 *)dln2_buf;
  311. u16 *s = (u16 *)src;
  312. len = len / 2;
  313. while (len--)
  314. *d++ = cpu_to_le16p(s++);
  315. } else {
  316. __le32 *d = (__le32 *)dln2_buf;
  317. u32 *s = (u32 *)src;
  318. len = len / 4;
  319. while (len--)
  320. *d++ = cpu_to_le32p(s++);
  321. }
  322. #endif
  323. return 0;
  324. }
  325. /*
  326. * Copy the data from DLN2 buffer and convert to CPU byte order since the DLN2
  327. * buffer is LE ordered. SPI core makes sure that the data length is a multiple
  328. * of word size. The RX dln2_buf is 2 byte aligned so, for BE, we have to make
  329. * sure we avoid unaligned accesses for 32 bit case.
  330. */
  331. static int dln2_spi_copy_from_buf(u8 *dest, const u8 *dln2_buf, u16 len, u8 bpw)
  332. {
  333. #ifdef __LITTLE_ENDIAN
  334. memcpy(dest, dln2_buf, len);
  335. #else
  336. if (bpw <= 8) {
  337. memcpy(dest, dln2_buf, len);
  338. } else if (bpw <= 16) {
  339. u16 *d = (u16 *)dest;
  340. __le16 *s = (__le16 *)dln2_buf;
  341. len = len / 2;
  342. while (len--)
  343. *d++ = le16_to_cpup(s++);
  344. } else {
  345. u32 *d = (u32 *)dest;
  346. __le32 *s = (__le32 *)dln2_buf;
  347. len = len / 4;
  348. while (len--)
  349. *d++ = get_unaligned_le32(s++);
  350. }
  351. #endif
  352. return 0;
  353. }
  354. /*
  355. * Perform one write operation.
  356. */
  357. static int dln2_spi_write_one(struct dln2_spi *dln2, const u8 *data,
  358. u16 data_len, u8 attr)
  359. {
  360. struct {
  361. u8 port;
  362. __le16 size;
  363. u8 attr;
  364. u8 buf[DLN2_SPI_MAX_XFER_SIZE];
  365. } __packed *tx = dln2->buf;
  366. unsigned tx_len;
  367. BUILD_BUG_ON(sizeof(*tx) > DLN2_SPI_BUF_SIZE);
  368. if (data_len > DLN2_SPI_MAX_XFER_SIZE)
  369. return -EINVAL;
  370. tx->port = dln2->port;
  371. tx->size = cpu_to_le16(data_len);
  372. tx->attr = attr;
  373. dln2_spi_copy_to_buf(tx->buf, data, data_len, dln2->bpw);
  374. tx_len = sizeof(*tx) + data_len - DLN2_SPI_MAX_XFER_SIZE;
  375. return dln2_transfer_tx(dln2->pdev, DLN2_SPI_WRITE, tx, tx_len);
  376. }
  377. /*
  378. * Perform one read operation.
  379. */
  380. static int dln2_spi_read_one(struct dln2_spi *dln2, u8 *data,
  381. u16 data_len, u8 attr)
  382. {
  383. int ret;
  384. struct {
  385. u8 port;
  386. __le16 size;
  387. u8 attr;
  388. } __packed tx;
  389. struct {
  390. __le16 size;
  391. u8 buf[DLN2_SPI_MAX_XFER_SIZE];
  392. } __packed *rx = dln2->buf;
  393. unsigned rx_len = sizeof(*rx);
  394. BUILD_BUG_ON(sizeof(*rx) > DLN2_SPI_BUF_SIZE);
  395. if (data_len > DLN2_SPI_MAX_XFER_SIZE)
  396. return -EINVAL;
  397. tx.port = dln2->port;
  398. tx.size = cpu_to_le16(data_len);
  399. tx.attr = attr;
  400. ret = dln2_transfer(dln2->pdev, DLN2_SPI_READ, &tx, sizeof(tx),
  401. rx, &rx_len);
  402. if (ret < 0)
  403. return ret;
  404. if (rx_len < sizeof(rx->size) + data_len)
  405. return -EPROTO;
  406. if (le16_to_cpu(rx->size) != data_len)
  407. return -EPROTO;
  408. dln2_spi_copy_from_buf(data, rx->buf, data_len, dln2->bpw);
  409. return 0;
  410. }
  411. /*
  412. * Perform one write & read operation.
  413. */
  414. static int dln2_spi_read_write_one(struct dln2_spi *dln2, const u8 *tx_data,
  415. u8 *rx_data, u16 data_len, u8 attr)
  416. {
  417. int ret;
  418. struct {
  419. u8 port;
  420. __le16 size;
  421. u8 attr;
  422. u8 buf[DLN2_SPI_MAX_XFER_SIZE];
  423. } __packed *tx;
  424. struct {
  425. __le16 size;
  426. u8 buf[DLN2_SPI_MAX_XFER_SIZE];
  427. } __packed *rx;
  428. unsigned tx_len, rx_len;
  429. BUILD_BUG_ON(sizeof(*tx) > DLN2_SPI_BUF_SIZE ||
  430. sizeof(*rx) > DLN2_SPI_BUF_SIZE);
  431. if (data_len > DLN2_SPI_MAX_XFER_SIZE)
  432. return -EINVAL;
  433. /*
  434. * Since this is a pseudo full-duplex communication, we're perfectly
  435. * safe to use the same buffer for both tx and rx. When DLN2 sends the
  436. * response back, with the rx data, we don't need the tx buffer anymore.
  437. */
  438. tx = dln2->buf;
  439. rx = dln2->buf;
  440. tx->port = dln2->port;
  441. tx->size = cpu_to_le16(data_len);
  442. tx->attr = attr;
  443. dln2_spi_copy_to_buf(tx->buf, tx_data, data_len, dln2->bpw);
  444. tx_len = sizeof(*tx) + data_len - DLN2_SPI_MAX_XFER_SIZE;
  445. rx_len = sizeof(*rx);
  446. ret = dln2_transfer(dln2->pdev, DLN2_SPI_READ_WRITE, tx, tx_len,
  447. rx, &rx_len);
  448. if (ret < 0)
  449. return ret;
  450. if (rx_len < sizeof(rx->size) + data_len)
  451. return -EPROTO;
  452. if (le16_to_cpu(rx->size) != data_len)
  453. return -EPROTO;
  454. dln2_spi_copy_from_buf(rx_data, rx->buf, data_len, dln2->bpw);
  455. return 0;
  456. }
  457. /*
  458. * Read/Write wrapper. It will automatically split an operation into multiple
  459. * single ones due to device buffer constraints.
  460. */
  461. static int dln2_spi_rdwr(struct dln2_spi *dln2, const u8 *tx_data,
  462. u8 *rx_data, u16 data_len, u8 attr) {
  463. int ret;
  464. u16 len;
  465. u8 temp_attr;
  466. u16 remaining = data_len;
  467. u16 offset;
  468. do {
  469. if (remaining > DLN2_SPI_MAX_XFER_SIZE) {
  470. len = DLN2_SPI_MAX_XFER_SIZE;
  471. temp_attr = DLN2_SPI_ATTR_LEAVE_SS_LOW;
  472. } else {
  473. len = remaining;
  474. temp_attr = attr;
  475. }
  476. offset = data_len - remaining;
  477. if (tx_data && rx_data) {
  478. ret = dln2_spi_read_write_one(dln2,
  479. tx_data + offset,
  480. rx_data + offset,
  481. len, temp_attr);
  482. } else if (tx_data) {
  483. ret = dln2_spi_write_one(dln2,
  484. tx_data + offset,
  485. len, temp_attr);
  486. } else if (rx_data) {
  487. ret = dln2_spi_read_one(dln2,
  488. rx_data + offset,
  489. len, temp_attr);
  490. } else {
  491. return -EINVAL;
  492. }
  493. if (ret < 0)
  494. return ret;
  495. remaining -= len;
  496. } while (remaining);
  497. return 0;
  498. }
  499. static int dln2_spi_prepare_message(struct spi_master *master,
  500. struct spi_message *message)
  501. {
  502. int ret;
  503. struct dln2_spi *dln2 = spi_master_get_devdata(master);
  504. struct spi_device *spi = message->spi;
  505. if (dln2->cs != spi->chip_select) {
  506. ret = dln2_spi_cs_set_one(dln2, spi->chip_select);
  507. if (ret < 0)
  508. return ret;
  509. dln2->cs = spi->chip_select;
  510. }
  511. return 0;
  512. }
  513. static int dln2_spi_transfer_setup(struct dln2_spi *dln2, u32 speed,
  514. u8 bpw, u8 mode)
  515. {
  516. int ret;
  517. bool bus_setup_change;
  518. bus_setup_change = dln2->speed != speed || dln2->mode != mode ||
  519. dln2->bpw != bpw;
  520. if (!bus_setup_change)
  521. return 0;
  522. ret = dln2_spi_enable(dln2, false);
  523. if (ret < 0)
  524. return ret;
  525. if (dln2->speed != speed) {
  526. ret = dln2_spi_set_speed(dln2, speed);
  527. if (ret < 0)
  528. return ret;
  529. dln2->speed = speed;
  530. }
  531. if (dln2->mode != mode) {
  532. ret = dln2_spi_set_mode(dln2, mode & 0x3);
  533. if (ret < 0)
  534. return ret;
  535. dln2->mode = mode;
  536. }
  537. if (dln2->bpw != bpw) {
  538. ret = dln2_spi_set_bpw(dln2, bpw);
  539. if (ret < 0)
  540. return ret;
  541. dln2->bpw = bpw;
  542. }
  543. return dln2_spi_enable(dln2, true);
  544. }
  545. static int dln2_spi_transfer_one(struct spi_master *master,
  546. struct spi_device *spi,
  547. struct spi_transfer *xfer)
  548. {
  549. struct dln2_spi *dln2 = spi_master_get_devdata(master);
  550. int status;
  551. u8 attr = 0;
  552. status = dln2_spi_transfer_setup(dln2, xfer->speed_hz,
  553. xfer->bits_per_word,
  554. spi->mode);
  555. if (status < 0) {
  556. dev_err(&dln2->pdev->dev, "Cannot setup transfer\n");
  557. return status;
  558. }
  559. if (!xfer->cs_change && !spi_transfer_is_last(master, xfer))
  560. attr = DLN2_SPI_ATTR_LEAVE_SS_LOW;
  561. status = dln2_spi_rdwr(dln2, xfer->tx_buf, xfer->rx_buf,
  562. xfer->len, attr);
  563. if (status < 0)
  564. dev_err(&dln2->pdev->dev, "write/read failed!\n");
  565. return status;
  566. }
  567. static int dln2_spi_probe(struct platform_device *pdev)
  568. {
  569. struct spi_master *master;
  570. struct dln2_spi *dln2;
  571. struct dln2_platform_data *pdata = dev_get_platdata(&pdev->dev);
  572. struct device *dev = &pdev->dev;
  573. int ret;
  574. master = spi_alloc_master(&pdev->dev, sizeof(*dln2));
  575. if (!master)
  576. return -ENOMEM;
  577. platform_set_drvdata(pdev, master);
  578. dln2 = spi_master_get_devdata(master);
  579. dln2->buf = devm_kmalloc(&pdev->dev, DLN2_SPI_BUF_SIZE, GFP_KERNEL);
  580. if (!dln2->buf) {
  581. ret = -ENOMEM;
  582. goto exit_free_master;
  583. }
  584. dln2->master = master;
  585. dln2->master->dev.of_node = dev->of_node;
  586. dln2->pdev = pdev;
  587. dln2->port = pdata->port;
  588. /* cs/mode can never be 0xff, so the first transfer will set them */
  589. dln2->cs = 0xff;
  590. dln2->mode = 0xff;
  591. /* disable SPI module before continuing with the setup */
  592. ret = dln2_spi_enable(dln2, false);
  593. if (ret < 0) {
  594. dev_err(&pdev->dev, "Failed to disable SPI module\n");
  595. goto exit_free_master;
  596. }
  597. ret = dln2_spi_get_cs_num(dln2, &master->num_chipselect);
  598. if (ret < 0) {
  599. dev_err(&pdev->dev, "Failed to get number of CS pins\n");
  600. goto exit_free_master;
  601. }
  602. ret = dln2_spi_get_speed_range(dln2,
  603. &master->min_speed_hz,
  604. &master->max_speed_hz);
  605. if (ret < 0) {
  606. dev_err(&pdev->dev, "Failed to read bus min/max freqs\n");
  607. goto exit_free_master;
  608. }
  609. ret = dln2_spi_get_supported_frame_sizes(dln2,
  610. &master->bits_per_word_mask);
  611. if (ret < 0) {
  612. dev_err(&pdev->dev, "Failed to read supported frame sizes\n");
  613. goto exit_free_master;
  614. }
  615. ret = dln2_spi_cs_enable_all(dln2, true);
  616. if (ret < 0) {
  617. dev_err(&pdev->dev, "Failed to enable CS pins\n");
  618. goto exit_free_master;
  619. }
  620. master->bus_num = -1;
  621. master->mode_bits = SPI_CPOL | SPI_CPHA;
  622. master->prepare_message = dln2_spi_prepare_message;
  623. master->transfer_one = dln2_spi_transfer_one;
  624. master->auto_runtime_pm = true;
  625. /* enable SPI module, we're good to go */
  626. ret = dln2_spi_enable(dln2, true);
  627. if (ret < 0) {
  628. dev_err(&pdev->dev, "Failed to enable SPI module\n");
  629. goto exit_free_master;
  630. }
  631. pm_runtime_set_autosuspend_delay(&pdev->dev,
  632. DLN2_RPM_AUTOSUSPEND_TIMEOUT);
  633. pm_runtime_use_autosuspend(&pdev->dev);
  634. pm_runtime_set_active(&pdev->dev);
  635. pm_runtime_enable(&pdev->dev);
  636. ret = devm_spi_register_master(&pdev->dev, master);
  637. if (ret < 0) {
  638. dev_err(&pdev->dev, "Failed to register master\n");
  639. goto exit_register;
  640. }
  641. return ret;
  642. exit_register:
  643. pm_runtime_disable(&pdev->dev);
  644. pm_runtime_set_suspended(&pdev->dev);
  645. if (dln2_spi_enable(dln2, false) < 0)
  646. dev_err(&pdev->dev, "Failed to disable SPI module\n");
  647. exit_free_master:
  648. spi_master_put(master);
  649. return ret;
  650. }
  651. static int dln2_spi_remove(struct platform_device *pdev)
  652. {
  653. struct spi_master *master = platform_get_drvdata(pdev);
  654. struct dln2_spi *dln2 = spi_master_get_devdata(master);
  655. pm_runtime_disable(&pdev->dev);
  656. if (dln2_spi_enable(dln2, false) < 0)
  657. dev_err(&pdev->dev, "Failed to disable SPI module\n");
  658. return 0;
  659. }
  660. #ifdef CONFIG_PM_SLEEP
  661. static int dln2_spi_suspend(struct device *dev)
  662. {
  663. int ret;
  664. struct spi_master *master = dev_get_drvdata(dev);
  665. struct dln2_spi *dln2 = spi_master_get_devdata(master);
  666. ret = spi_master_suspend(master);
  667. if (ret < 0)
  668. return ret;
  669. if (!pm_runtime_suspended(dev)) {
  670. ret = dln2_spi_enable(dln2, false);
  671. if (ret < 0)
  672. return ret;
  673. }
  674. /*
  675. * USB power may be cut off during sleep. Resetting the following
  676. * parameters will force the board to be set up before first transfer.
  677. */
  678. dln2->cs = 0xff;
  679. dln2->speed = 0;
  680. dln2->bpw = 0;
  681. dln2->mode = 0xff;
  682. return 0;
  683. }
  684. static int dln2_spi_resume(struct device *dev)
  685. {
  686. int ret;
  687. struct spi_master *master = dev_get_drvdata(dev);
  688. struct dln2_spi *dln2 = spi_master_get_devdata(master);
  689. if (!pm_runtime_suspended(dev)) {
  690. ret = dln2_spi_cs_enable_all(dln2, true);
  691. if (ret < 0)
  692. return ret;
  693. ret = dln2_spi_enable(dln2, true);
  694. if (ret < 0)
  695. return ret;
  696. }
  697. return spi_master_resume(master);
  698. }
  699. #endif /* CONFIG_PM_SLEEP */
  700. #ifdef CONFIG_PM
  701. static int dln2_spi_runtime_suspend(struct device *dev)
  702. {
  703. struct spi_master *master = dev_get_drvdata(dev);
  704. struct dln2_spi *dln2 = spi_master_get_devdata(master);
  705. return dln2_spi_enable(dln2, false);
  706. }
  707. static int dln2_spi_runtime_resume(struct device *dev)
  708. {
  709. struct spi_master *master = dev_get_drvdata(dev);
  710. struct dln2_spi *dln2 = spi_master_get_devdata(master);
  711. return dln2_spi_enable(dln2, true);
  712. }
  713. #endif /* CONFIG_PM */
  714. static const struct dev_pm_ops dln2_spi_pm = {
  715. SET_SYSTEM_SLEEP_PM_OPS(dln2_spi_suspend, dln2_spi_resume)
  716. SET_RUNTIME_PM_OPS(dln2_spi_runtime_suspend,
  717. dln2_spi_runtime_resume, NULL)
  718. };
  719. static struct platform_driver spi_dln2_driver = {
  720. .driver = {
  721. .name = "dln2-spi",
  722. .pm = &dln2_spi_pm,
  723. },
  724. .probe = dln2_spi_probe,
  725. .remove = dln2_spi_remove,
  726. };
  727. module_platform_driver(spi_dln2_driver);
  728. MODULE_DESCRIPTION("Driver for the Diolan DLN2 SPI master interface");
  729. MODULE_AUTHOR("Laurentiu Palcu <laurentiu.palcu@intel.com>");
  730. MODULE_LICENSE("GPL v2");
  731. MODULE_ALIAS("platform:dln2-spi");