spi-coldfire-qspi.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Freescale/Motorola Coldfire Queued SPI driver
  4. *
  5. * Copyright 2010 Steven King <sfking@fdwdc.com>
  6. */
  7. #include <linux/kernel.h>
  8. #include <linux/module.h>
  9. #include <linux/interrupt.h>
  10. #include <linux/errno.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/sched.h>
  13. #include <linux/delay.h>
  14. #include <linux/io.h>
  15. #include <linux/clk.h>
  16. #include <linux/err.h>
  17. #include <linux/spi/spi.h>
  18. #include <linux/pm_runtime.h>
  19. #include <asm/coldfire.h>
  20. #include <asm/mcfsim.h>
  21. #include <asm/mcfqspi.h>
  22. #define DRIVER_NAME "mcfqspi"
  23. #define MCFQSPI_BUSCLK (MCF_BUSCLK / 2)
  24. #define MCFQSPI_QMR 0x00
  25. #define MCFQSPI_QMR_MSTR 0x8000
  26. #define MCFQSPI_QMR_CPOL 0x0200
  27. #define MCFQSPI_QMR_CPHA 0x0100
  28. #define MCFQSPI_QDLYR 0x04
  29. #define MCFQSPI_QDLYR_SPE 0x8000
  30. #define MCFQSPI_QWR 0x08
  31. #define MCFQSPI_QWR_HALT 0x8000
  32. #define MCFQSPI_QWR_WREN 0x4000
  33. #define MCFQSPI_QWR_CSIV 0x1000
  34. #define MCFQSPI_QIR 0x0C
  35. #define MCFQSPI_QIR_WCEFB 0x8000
  36. #define MCFQSPI_QIR_ABRTB 0x4000
  37. #define MCFQSPI_QIR_ABRTL 0x1000
  38. #define MCFQSPI_QIR_WCEFE 0x0800
  39. #define MCFQSPI_QIR_ABRTE 0x0400
  40. #define MCFQSPI_QIR_SPIFE 0x0100
  41. #define MCFQSPI_QIR_WCEF 0x0008
  42. #define MCFQSPI_QIR_ABRT 0x0004
  43. #define MCFQSPI_QIR_SPIF 0x0001
  44. #define MCFQSPI_QAR 0x010
  45. #define MCFQSPI_QAR_TXBUF 0x00
  46. #define MCFQSPI_QAR_RXBUF 0x10
  47. #define MCFQSPI_QAR_CMDBUF 0x20
  48. #define MCFQSPI_QDR 0x014
  49. #define MCFQSPI_QCR 0x014
  50. #define MCFQSPI_QCR_CONT 0x8000
  51. #define MCFQSPI_QCR_BITSE 0x4000
  52. #define MCFQSPI_QCR_DT 0x2000
  53. struct mcfqspi {
  54. void __iomem *iobase;
  55. int irq;
  56. struct clk *clk;
  57. struct mcfqspi_cs_control *cs_control;
  58. wait_queue_head_t waitq;
  59. };
  60. static void mcfqspi_wr_qmr(struct mcfqspi *mcfqspi, u16 val)
  61. {
  62. writew(val, mcfqspi->iobase + MCFQSPI_QMR);
  63. }
  64. static void mcfqspi_wr_qdlyr(struct mcfqspi *mcfqspi, u16 val)
  65. {
  66. writew(val, mcfqspi->iobase + MCFQSPI_QDLYR);
  67. }
  68. static u16 mcfqspi_rd_qdlyr(struct mcfqspi *mcfqspi)
  69. {
  70. return readw(mcfqspi->iobase + MCFQSPI_QDLYR);
  71. }
  72. static void mcfqspi_wr_qwr(struct mcfqspi *mcfqspi, u16 val)
  73. {
  74. writew(val, mcfqspi->iobase + MCFQSPI_QWR);
  75. }
  76. static void mcfqspi_wr_qir(struct mcfqspi *mcfqspi, u16 val)
  77. {
  78. writew(val, mcfqspi->iobase + MCFQSPI_QIR);
  79. }
  80. static void mcfqspi_wr_qar(struct mcfqspi *mcfqspi, u16 val)
  81. {
  82. writew(val, mcfqspi->iobase + MCFQSPI_QAR);
  83. }
  84. static void mcfqspi_wr_qdr(struct mcfqspi *mcfqspi, u16 val)
  85. {
  86. writew(val, mcfqspi->iobase + MCFQSPI_QDR);
  87. }
  88. static u16 mcfqspi_rd_qdr(struct mcfqspi *mcfqspi)
  89. {
  90. return readw(mcfqspi->iobase + MCFQSPI_QDR);
  91. }
  92. static void mcfqspi_cs_select(struct mcfqspi *mcfqspi, u8 chip_select,
  93. bool cs_high)
  94. {
  95. mcfqspi->cs_control->select(mcfqspi->cs_control, chip_select, cs_high);
  96. }
  97. static void mcfqspi_cs_deselect(struct mcfqspi *mcfqspi, u8 chip_select,
  98. bool cs_high)
  99. {
  100. mcfqspi->cs_control->deselect(mcfqspi->cs_control, chip_select, cs_high);
  101. }
  102. static int mcfqspi_cs_setup(struct mcfqspi *mcfqspi)
  103. {
  104. return (mcfqspi->cs_control->setup) ?
  105. mcfqspi->cs_control->setup(mcfqspi->cs_control) : 0;
  106. }
  107. static void mcfqspi_cs_teardown(struct mcfqspi *mcfqspi)
  108. {
  109. if (mcfqspi->cs_control->teardown)
  110. mcfqspi->cs_control->teardown(mcfqspi->cs_control);
  111. }
  112. static u8 mcfqspi_qmr_baud(u32 speed_hz)
  113. {
  114. return clamp((MCFQSPI_BUSCLK + speed_hz - 1) / speed_hz, 2u, 255u);
  115. }
  116. static bool mcfqspi_qdlyr_spe(struct mcfqspi *mcfqspi)
  117. {
  118. return mcfqspi_rd_qdlyr(mcfqspi) & MCFQSPI_QDLYR_SPE;
  119. }
  120. static irqreturn_t mcfqspi_irq_handler(int this_irq, void *dev_id)
  121. {
  122. struct mcfqspi *mcfqspi = dev_id;
  123. /* clear interrupt */
  124. mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE | MCFQSPI_QIR_SPIF);
  125. wake_up(&mcfqspi->waitq);
  126. return IRQ_HANDLED;
  127. }
  128. static void mcfqspi_transfer_msg8(struct mcfqspi *mcfqspi, unsigned count,
  129. const u8 *txbuf, u8 *rxbuf)
  130. {
  131. unsigned i, n, offset = 0;
  132. n = min(count, 16u);
  133. mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_CMDBUF);
  134. for (i = 0; i < n; ++i)
  135. mcfqspi_wr_qdr(mcfqspi, MCFQSPI_QCR_BITSE);
  136. mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_TXBUF);
  137. if (txbuf)
  138. for (i = 0; i < n; ++i)
  139. mcfqspi_wr_qdr(mcfqspi, *txbuf++);
  140. else
  141. for (i = 0; i < count; ++i)
  142. mcfqspi_wr_qdr(mcfqspi, 0);
  143. count -= n;
  144. if (count) {
  145. u16 qwr = 0xf08;
  146. mcfqspi_wr_qwr(mcfqspi, 0x700);
  147. mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
  148. do {
  149. wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
  150. mcfqspi_wr_qwr(mcfqspi, qwr);
  151. mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
  152. if (rxbuf) {
  153. mcfqspi_wr_qar(mcfqspi,
  154. MCFQSPI_QAR_RXBUF + offset);
  155. for (i = 0; i < 8; ++i)
  156. *rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
  157. }
  158. n = min(count, 8u);
  159. if (txbuf) {
  160. mcfqspi_wr_qar(mcfqspi,
  161. MCFQSPI_QAR_TXBUF + offset);
  162. for (i = 0; i < n; ++i)
  163. mcfqspi_wr_qdr(mcfqspi, *txbuf++);
  164. }
  165. qwr = (offset ? 0x808 : 0) + ((n - 1) << 8);
  166. offset ^= 8;
  167. count -= n;
  168. } while (count);
  169. wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
  170. mcfqspi_wr_qwr(mcfqspi, qwr);
  171. mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
  172. if (rxbuf) {
  173. mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
  174. for (i = 0; i < 8; ++i)
  175. *rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
  176. offset ^= 8;
  177. }
  178. } else {
  179. mcfqspi_wr_qwr(mcfqspi, (n - 1) << 8);
  180. mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
  181. }
  182. wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
  183. if (rxbuf) {
  184. mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
  185. for (i = 0; i < n; ++i)
  186. *rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
  187. }
  188. }
  189. static void mcfqspi_transfer_msg16(struct mcfqspi *mcfqspi, unsigned count,
  190. const u16 *txbuf, u16 *rxbuf)
  191. {
  192. unsigned i, n, offset = 0;
  193. n = min(count, 16u);
  194. mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_CMDBUF);
  195. for (i = 0; i < n; ++i)
  196. mcfqspi_wr_qdr(mcfqspi, MCFQSPI_QCR_BITSE);
  197. mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_TXBUF);
  198. if (txbuf)
  199. for (i = 0; i < n; ++i)
  200. mcfqspi_wr_qdr(mcfqspi, *txbuf++);
  201. else
  202. for (i = 0; i < count; ++i)
  203. mcfqspi_wr_qdr(mcfqspi, 0);
  204. count -= n;
  205. if (count) {
  206. u16 qwr = 0xf08;
  207. mcfqspi_wr_qwr(mcfqspi, 0x700);
  208. mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
  209. do {
  210. wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
  211. mcfqspi_wr_qwr(mcfqspi, qwr);
  212. mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
  213. if (rxbuf) {
  214. mcfqspi_wr_qar(mcfqspi,
  215. MCFQSPI_QAR_RXBUF + offset);
  216. for (i = 0; i < 8; ++i)
  217. *rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
  218. }
  219. n = min(count, 8u);
  220. if (txbuf) {
  221. mcfqspi_wr_qar(mcfqspi,
  222. MCFQSPI_QAR_TXBUF + offset);
  223. for (i = 0; i < n; ++i)
  224. mcfqspi_wr_qdr(mcfqspi, *txbuf++);
  225. }
  226. qwr = (offset ? 0x808 : 0x000) + ((n - 1) << 8);
  227. offset ^= 8;
  228. count -= n;
  229. } while (count);
  230. wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
  231. mcfqspi_wr_qwr(mcfqspi, qwr);
  232. mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
  233. if (rxbuf) {
  234. mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
  235. for (i = 0; i < 8; ++i)
  236. *rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
  237. offset ^= 8;
  238. }
  239. } else {
  240. mcfqspi_wr_qwr(mcfqspi, (n - 1) << 8);
  241. mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
  242. }
  243. wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
  244. if (rxbuf) {
  245. mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
  246. for (i = 0; i < n; ++i)
  247. *rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
  248. }
  249. }
  250. static void mcfqspi_set_cs(struct spi_device *spi, bool enable)
  251. {
  252. struct mcfqspi *mcfqspi = spi_master_get_devdata(spi->master);
  253. bool cs_high = spi->mode & SPI_CS_HIGH;
  254. if (enable)
  255. mcfqspi_cs_select(mcfqspi, spi->chip_select, cs_high);
  256. else
  257. mcfqspi_cs_deselect(mcfqspi, spi->chip_select, cs_high);
  258. }
  259. static int mcfqspi_transfer_one(struct spi_master *master,
  260. struct spi_device *spi,
  261. struct spi_transfer *t)
  262. {
  263. struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
  264. u16 qmr = MCFQSPI_QMR_MSTR;
  265. qmr |= t->bits_per_word << 10;
  266. if (spi->mode & SPI_CPHA)
  267. qmr |= MCFQSPI_QMR_CPHA;
  268. if (spi->mode & SPI_CPOL)
  269. qmr |= MCFQSPI_QMR_CPOL;
  270. qmr |= mcfqspi_qmr_baud(t->speed_hz);
  271. mcfqspi_wr_qmr(mcfqspi, qmr);
  272. mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE);
  273. if (t->bits_per_word == 8)
  274. mcfqspi_transfer_msg8(mcfqspi, t->len, t->tx_buf, t->rx_buf);
  275. else
  276. mcfqspi_transfer_msg16(mcfqspi, t->len / 2, t->tx_buf,
  277. t->rx_buf);
  278. mcfqspi_wr_qir(mcfqspi, 0);
  279. return 0;
  280. }
  281. static int mcfqspi_setup(struct spi_device *spi)
  282. {
  283. mcfqspi_cs_deselect(spi_master_get_devdata(spi->master),
  284. spi->chip_select, spi->mode & SPI_CS_HIGH);
  285. dev_dbg(&spi->dev,
  286. "bits per word %d, chip select %d, speed %d KHz\n",
  287. spi->bits_per_word, spi->chip_select,
  288. (MCFQSPI_BUSCLK / mcfqspi_qmr_baud(spi->max_speed_hz))
  289. / 1000);
  290. return 0;
  291. }
  292. static int mcfqspi_probe(struct platform_device *pdev)
  293. {
  294. struct spi_master *master;
  295. struct mcfqspi *mcfqspi;
  296. struct mcfqspi_platform_data *pdata;
  297. int status;
  298. pdata = dev_get_platdata(&pdev->dev);
  299. if (!pdata) {
  300. dev_dbg(&pdev->dev, "platform data is missing\n");
  301. return -ENOENT;
  302. }
  303. if (!pdata->cs_control) {
  304. dev_dbg(&pdev->dev, "pdata->cs_control is NULL\n");
  305. return -EINVAL;
  306. }
  307. master = spi_alloc_master(&pdev->dev, sizeof(*mcfqspi));
  308. if (master == NULL) {
  309. dev_dbg(&pdev->dev, "spi_alloc_master failed\n");
  310. return -ENOMEM;
  311. }
  312. mcfqspi = spi_master_get_devdata(master);
  313. mcfqspi->iobase = devm_platform_ioremap_resource(pdev, 0);
  314. if (IS_ERR(mcfqspi->iobase)) {
  315. status = PTR_ERR(mcfqspi->iobase);
  316. goto fail0;
  317. }
  318. mcfqspi->irq = platform_get_irq(pdev, 0);
  319. if (mcfqspi->irq < 0) {
  320. dev_dbg(&pdev->dev, "platform_get_irq failed\n");
  321. status = -ENXIO;
  322. goto fail0;
  323. }
  324. status = devm_request_irq(&pdev->dev, mcfqspi->irq, mcfqspi_irq_handler,
  325. 0, pdev->name, mcfqspi);
  326. if (status) {
  327. dev_dbg(&pdev->dev, "request_irq failed\n");
  328. goto fail0;
  329. }
  330. mcfqspi->clk = devm_clk_get(&pdev->dev, "qspi_clk");
  331. if (IS_ERR(mcfqspi->clk)) {
  332. dev_dbg(&pdev->dev, "clk_get failed\n");
  333. status = PTR_ERR(mcfqspi->clk);
  334. goto fail0;
  335. }
  336. clk_prepare_enable(mcfqspi->clk);
  337. master->bus_num = pdata->bus_num;
  338. master->num_chipselect = pdata->num_chipselect;
  339. mcfqspi->cs_control = pdata->cs_control;
  340. status = mcfqspi_cs_setup(mcfqspi);
  341. if (status) {
  342. dev_dbg(&pdev->dev, "error initializing cs_control\n");
  343. goto fail1;
  344. }
  345. init_waitqueue_head(&mcfqspi->waitq);
  346. master->mode_bits = SPI_CS_HIGH | SPI_CPOL | SPI_CPHA;
  347. master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
  348. master->setup = mcfqspi_setup;
  349. master->set_cs = mcfqspi_set_cs;
  350. master->transfer_one = mcfqspi_transfer_one;
  351. master->auto_runtime_pm = true;
  352. platform_set_drvdata(pdev, master);
  353. pm_runtime_enable(&pdev->dev);
  354. status = devm_spi_register_master(&pdev->dev, master);
  355. if (status) {
  356. dev_dbg(&pdev->dev, "spi_register_master failed\n");
  357. goto fail2;
  358. }
  359. dev_info(&pdev->dev, "Coldfire QSPI bus driver\n");
  360. return 0;
  361. fail2:
  362. pm_runtime_disable(&pdev->dev);
  363. mcfqspi_cs_teardown(mcfqspi);
  364. fail1:
  365. clk_disable_unprepare(mcfqspi->clk);
  366. fail0:
  367. spi_master_put(master);
  368. dev_dbg(&pdev->dev, "Coldfire QSPI probe failed\n");
  369. return status;
  370. }
  371. static int mcfqspi_remove(struct platform_device *pdev)
  372. {
  373. struct spi_master *master = platform_get_drvdata(pdev);
  374. struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
  375. pm_runtime_disable(&pdev->dev);
  376. /* disable the hardware (set the baud rate to 0) */
  377. mcfqspi_wr_qmr(mcfqspi, MCFQSPI_QMR_MSTR);
  378. mcfqspi_cs_teardown(mcfqspi);
  379. clk_disable_unprepare(mcfqspi->clk);
  380. return 0;
  381. }
  382. #ifdef CONFIG_PM_SLEEP
  383. static int mcfqspi_suspend(struct device *dev)
  384. {
  385. struct spi_master *master = dev_get_drvdata(dev);
  386. struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
  387. int ret;
  388. ret = spi_master_suspend(master);
  389. if (ret)
  390. return ret;
  391. clk_disable(mcfqspi->clk);
  392. return 0;
  393. }
  394. static int mcfqspi_resume(struct device *dev)
  395. {
  396. struct spi_master *master = dev_get_drvdata(dev);
  397. struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
  398. clk_enable(mcfqspi->clk);
  399. return spi_master_resume(master);
  400. }
  401. #endif
  402. #ifdef CONFIG_PM
  403. static int mcfqspi_runtime_suspend(struct device *dev)
  404. {
  405. struct spi_master *master = dev_get_drvdata(dev);
  406. struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
  407. clk_disable(mcfqspi->clk);
  408. return 0;
  409. }
  410. static int mcfqspi_runtime_resume(struct device *dev)
  411. {
  412. struct spi_master *master = dev_get_drvdata(dev);
  413. struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
  414. clk_enable(mcfqspi->clk);
  415. return 0;
  416. }
  417. #endif
  418. static const struct dev_pm_ops mcfqspi_pm = {
  419. SET_SYSTEM_SLEEP_PM_OPS(mcfqspi_suspend, mcfqspi_resume)
  420. SET_RUNTIME_PM_OPS(mcfqspi_runtime_suspend, mcfqspi_runtime_resume,
  421. NULL)
  422. };
  423. static struct platform_driver mcfqspi_driver = {
  424. .driver.name = DRIVER_NAME,
  425. .driver.owner = THIS_MODULE,
  426. .driver.pm = &mcfqspi_pm,
  427. .probe = mcfqspi_probe,
  428. .remove = mcfqspi_remove,
  429. };
  430. module_platform_driver(mcfqspi_driver);
  431. MODULE_AUTHOR("Steven King <sfking@fdwdc.com>");
  432. MODULE_DESCRIPTION("Coldfire QSPI Controller Driver");
  433. MODULE_LICENSE("GPL");
  434. MODULE_ALIAS("platform:" DRIVER_NAME);