spi-au1550.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * au1550 psc spi controller driver
  4. * may work also with au1200, au1210, au1250
  5. * will not work on au1000, au1100 and au1500 (no full spi controller there)
  6. *
  7. * Copyright (c) 2006 ATRON electronic GmbH
  8. * Author: Jan Nikitenko <jan.nikitenko@gmail.com>
  9. */
  10. #include <linux/init.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/slab.h>
  13. #include <linux/errno.h>
  14. #include <linux/module.h>
  15. #include <linux/device.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/resource.h>
  18. #include <linux/spi/spi.h>
  19. #include <linux/spi/spi_bitbang.h>
  20. #include <linux/dma-mapping.h>
  21. #include <linux/completion.h>
  22. #include <asm/mach-au1x00/au1000.h>
  23. #include <asm/mach-au1x00/au1xxx_psc.h>
  24. #include <asm/mach-au1x00/au1xxx_dbdma.h>
  25. #include <asm/mach-au1x00/au1550_spi.h>
  26. static unsigned usedma = 1;
  27. module_param(usedma, uint, 0644);
  28. /*
  29. #define AU1550_SPI_DEBUG_LOOPBACK
  30. */
  31. #define AU1550_SPI_DBDMA_DESCRIPTORS 1
  32. #define AU1550_SPI_DMA_RXTMP_MINSIZE 2048U
  33. struct au1550_spi {
  34. struct spi_bitbang bitbang;
  35. volatile psc_spi_t __iomem *regs;
  36. int irq;
  37. unsigned len;
  38. unsigned tx_count;
  39. unsigned rx_count;
  40. const u8 *tx;
  41. u8 *rx;
  42. void (*rx_word)(struct au1550_spi *hw);
  43. void (*tx_word)(struct au1550_spi *hw);
  44. int (*txrx_bufs)(struct spi_device *spi, struct spi_transfer *t);
  45. irqreturn_t (*irq_callback)(struct au1550_spi *hw);
  46. struct completion master_done;
  47. unsigned usedma;
  48. u32 dma_tx_id;
  49. u32 dma_rx_id;
  50. u32 dma_tx_ch;
  51. u32 dma_rx_ch;
  52. u8 *dma_rx_tmpbuf;
  53. unsigned dma_rx_tmpbuf_size;
  54. u32 dma_rx_tmpbuf_addr;
  55. struct spi_master *master;
  56. struct device *dev;
  57. struct au1550_spi_info *pdata;
  58. struct resource *ioarea;
  59. };
  60. /* we use an 8-bit memory device for dma transfers to/from spi fifo */
  61. static dbdev_tab_t au1550_spi_mem_dbdev =
  62. {
  63. .dev_id = DBDMA_MEM_CHAN,
  64. .dev_flags = DEV_FLAGS_ANYUSE|DEV_FLAGS_SYNC,
  65. .dev_tsize = 0,
  66. .dev_devwidth = 8,
  67. .dev_physaddr = 0x00000000,
  68. .dev_intlevel = 0,
  69. .dev_intpolarity = 0
  70. };
  71. static int ddma_memid; /* id to above mem dma device */
  72. static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw);
  73. /*
  74. * compute BRG and DIV bits to setup spi clock based on main input clock rate
  75. * that was specified in platform data structure
  76. * according to au1550 datasheet:
  77. * psc_tempclk = psc_mainclk / (2 << DIV)
  78. * spiclk = psc_tempclk / (2 * (BRG + 1))
  79. * BRG valid range is 4..63
  80. * DIV valid range is 0..3
  81. */
  82. static u32 au1550_spi_baudcfg(struct au1550_spi *hw, unsigned speed_hz)
  83. {
  84. u32 mainclk_hz = hw->pdata->mainclk_hz;
  85. u32 div, brg;
  86. for (div = 0; div < 4; div++) {
  87. brg = mainclk_hz / speed_hz / (4 << div);
  88. /* now we have BRG+1 in brg, so count with that */
  89. if (brg < (4 + 1)) {
  90. brg = (4 + 1); /* speed_hz too big */
  91. break; /* set lowest brg (div is == 0) */
  92. }
  93. if (brg <= (63 + 1))
  94. break; /* we have valid brg and div */
  95. }
  96. if (div == 4) {
  97. div = 3; /* speed_hz too small */
  98. brg = (63 + 1); /* set highest brg and div */
  99. }
  100. brg--;
  101. return PSC_SPICFG_SET_BAUD(brg) | PSC_SPICFG_SET_DIV(div);
  102. }
  103. static inline void au1550_spi_mask_ack_all(struct au1550_spi *hw)
  104. {
  105. hw->regs->psc_spimsk =
  106. PSC_SPIMSK_MM | PSC_SPIMSK_RR | PSC_SPIMSK_RO
  107. | PSC_SPIMSK_RU | PSC_SPIMSK_TR | PSC_SPIMSK_TO
  108. | PSC_SPIMSK_TU | PSC_SPIMSK_SD | PSC_SPIMSK_MD;
  109. wmb(); /* drain writebuffer */
  110. hw->regs->psc_spievent =
  111. PSC_SPIEVNT_MM | PSC_SPIEVNT_RR | PSC_SPIEVNT_RO
  112. | PSC_SPIEVNT_RU | PSC_SPIEVNT_TR | PSC_SPIEVNT_TO
  113. | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD | PSC_SPIEVNT_MD;
  114. wmb(); /* drain writebuffer */
  115. }
  116. static void au1550_spi_reset_fifos(struct au1550_spi *hw)
  117. {
  118. u32 pcr;
  119. hw->regs->psc_spipcr = PSC_SPIPCR_RC | PSC_SPIPCR_TC;
  120. wmb(); /* drain writebuffer */
  121. do {
  122. pcr = hw->regs->psc_spipcr;
  123. wmb(); /* drain writebuffer */
  124. } while (pcr != 0);
  125. }
  126. /*
  127. * dma transfers are used for the most common spi word size of 8-bits
  128. * we cannot easily change already set up dma channels' width, so if we wanted
  129. * dma support for more than 8-bit words (up to 24 bits), we would need to
  130. * setup dma channels from scratch on each spi transfer, based on bits_per_word
  131. * instead we have pre set up 8 bit dma channels supporting spi 4 to 8 bits
  132. * transfers, and 9 to 24 bits spi transfers will be done in pio irq based mode
  133. * callbacks to handle dma or pio are set up in au1550_spi_bits_handlers_set()
  134. */
  135. static void au1550_spi_chipsel(struct spi_device *spi, int value)
  136. {
  137. struct au1550_spi *hw = spi_master_get_devdata(spi->master);
  138. unsigned cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
  139. u32 cfg, stat;
  140. switch (value) {
  141. case BITBANG_CS_INACTIVE:
  142. if (hw->pdata->deactivate_cs)
  143. hw->pdata->deactivate_cs(hw->pdata, spi->chip_select,
  144. cspol);
  145. break;
  146. case BITBANG_CS_ACTIVE:
  147. au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
  148. cfg = hw->regs->psc_spicfg;
  149. wmb(); /* drain writebuffer */
  150. hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
  151. wmb(); /* drain writebuffer */
  152. if (spi->mode & SPI_CPOL)
  153. cfg |= PSC_SPICFG_BI;
  154. else
  155. cfg &= ~PSC_SPICFG_BI;
  156. if (spi->mode & SPI_CPHA)
  157. cfg &= ~PSC_SPICFG_CDE;
  158. else
  159. cfg |= PSC_SPICFG_CDE;
  160. if (spi->mode & SPI_LSB_FIRST)
  161. cfg |= PSC_SPICFG_MLF;
  162. else
  163. cfg &= ~PSC_SPICFG_MLF;
  164. if (hw->usedma && spi->bits_per_word <= 8)
  165. cfg &= ~PSC_SPICFG_DD_DISABLE;
  166. else
  167. cfg |= PSC_SPICFG_DD_DISABLE;
  168. cfg = PSC_SPICFG_CLR_LEN(cfg);
  169. cfg |= PSC_SPICFG_SET_LEN(spi->bits_per_word);
  170. cfg = PSC_SPICFG_CLR_BAUD(cfg);
  171. cfg &= ~PSC_SPICFG_SET_DIV(3);
  172. cfg |= au1550_spi_baudcfg(hw, spi->max_speed_hz);
  173. hw->regs->psc_spicfg = cfg | PSC_SPICFG_DE_ENABLE;
  174. wmb(); /* drain writebuffer */
  175. do {
  176. stat = hw->regs->psc_spistat;
  177. wmb(); /* drain writebuffer */
  178. } while ((stat & PSC_SPISTAT_DR) == 0);
  179. if (hw->pdata->activate_cs)
  180. hw->pdata->activate_cs(hw->pdata, spi->chip_select,
  181. cspol);
  182. break;
  183. }
  184. }
  185. static int au1550_spi_setupxfer(struct spi_device *spi, struct spi_transfer *t)
  186. {
  187. struct au1550_spi *hw = spi_master_get_devdata(spi->master);
  188. unsigned bpw, hz;
  189. u32 cfg, stat;
  190. if (t) {
  191. bpw = t->bits_per_word;
  192. hz = t->speed_hz;
  193. } else {
  194. bpw = spi->bits_per_word;
  195. hz = spi->max_speed_hz;
  196. }
  197. if (!hz)
  198. return -EINVAL;
  199. au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
  200. cfg = hw->regs->psc_spicfg;
  201. wmb(); /* drain writebuffer */
  202. hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
  203. wmb(); /* drain writebuffer */
  204. if (hw->usedma && bpw <= 8)
  205. cfg &= ~PSC_SPICFG_DD_DISABLE;
  206. else
  207. cfg |= PSC_SPICFG_DD_DISABLE;
  208. cfg = PSC_SPICFG_CLR_LEN(cfg);
  209. cfg |= PSC_SPICFG_SET_LEN(bpw);
  210. cfg = PSC_SPICFG_CLR_BAUD(cfg);
  211. cfg &= ~PSC_SPICFG_SET_DIV(3);
  212. cfg |= au1550_spi_baudcfg(hw, hz);
  213. hw->regs->psc_spicfg = cfg;
  214. wmb(); /* drain writebuffer */
  215. if (cfg & PSC_SPICFG_DE_ENABLE) {
  216. do {
  217. stat = hw->regs->psc_spistat;
  218. wmb(); /* drain writebuffer */
  219. } while ((stat & PSC_SPISTAT_DR) == 0);
  220. }
  221. au1550_spi_reset_fifos(hw);
  222. au1550_spi_mask_ack_all(hw);
  223. return 0;
  224. }
  225. /*
  226. * for dma spi transfers, we have to setup rx channel, otherwise there is
  227. * no reliable way how to recognize that spi transfer is done
  228. * dma complete callbacks are called before real spi transfer is finished
  229. * and if only tx dma channel is set up (and rx fifo overflow event masked)
  230. * spi master done event irq is not generated unless rx fifo is empty (emptied)
  231. * so we need rx tmp buffer to use for rx dma if user does not provide one
  232. */
  233. static int au1550_spi_dma_rxtmp_alloc(struct au1550_spi *hw, unsigned size)
  234. {
  235. hw->dma_rx_tmpbuf = kmalloc(size, GFP_KERNEL);
  236. if (!hw->dma_rx_tmpbuf)
  237. return -ENOMEM;
  238. hw->dma_rx_tmpbuf_size = size;
  239. hw->dma_rx_tmpbuf_addr = dma_map_single(hw->dev, hw->dma_rx_tmpbuf,
  240. size, DMA_FROM_DEVICE);
  241. if (dma_mapping_error(hw->dev, hw->dma_rx_tmpbuf_addr)) {
  242. kfree(hw->dma_rx_tmpbuf);
  243. hw->dma_rx_tmpbuf = 0;
  244. hw->dma_rx_tmpbuf_size = 0;
  245. return -EFAULT;
  246. }
  247. return 0;
  248. }
  249. static void au1550_spi_dma_rxtmp_free(struct au1550_spi *hw)
  250. {
  251. dma_unmap_single(hw->dev, hw->dma_rx_tmpbuf_addr,
  252. hw->dma_rx_tmpbuf_size, DMA_FROM_DEVICE);
  253. kfree(hw->dma_rx_tmpbuf);
  254. hw->dma_rx_tmpbuf = 0;
  255. hw->dma_rx_tmpbuf_size = 0;
  256. }
  257. static int au1550_spi_dma_txrxb(struct spi_device *spi, struct spi_transfer *t)
  258. {
  259. struct au1550_spi *hw = spi_master_get_devdata(spi->master);
  260. dma_addr_t dma_tx_addr;
  261. dma_addr_t dma_rx_addr;
  262. u32 res;
  263. hw->len = t->len;
  264. hw->tx_count = 0;
  265. hw->rx_count = 0;
  266. hw->tx = t->tx_buf;
  267. hw->rx = t->rx_buf;
  268. dma_tx_addr = t->tx_dma;
  269. dma_rx_addr = t->rx_dma;
  270. /*
  271. * check if buffers are already dma mapped, map them otherwise:
  272. * - first map the TX buffer, so cache data gets written to memory
  273. * - then map the RX buffer, so that cache entries (with
  274. * soon-to-be-stale data) get removed
  275. * use rx buffer in place of tx if tx buffer was not provided
  276. * use temp rx buffer (preallocated or realloc to fit) for rx dma
  277. */
  278. if (t->tx_buf) {
  279. if (t->tx_dma == 0) { /* if DMA_ADDR_INVALID, map it */
  280. dma_tx_addr = dma_map_single(hw->dev,
  281. (void *)t->tx_buf,
  282. t->len, DMA_TO_DEVICE);
  283. if (dma_mapping_error(hw->dev, dma_tx_addr))
  284. dev_err(hw->dev, "tx dma map error\n");
  285. }
  286. }
  287. if (t->rx_buf) {
  288. if (t->rx_dma == 0) { /* if DMA_ADDR_INVALID, map it */
  289. dma_rx_addr = dma_map_single(hw->dev,
  290. (void *)t->rx_buf,
  291. t->len, DMA_FROM_DEVICE);
  292. if (dma_mapping_error(hw->dev, dma_rx_addr))
  293. dev_err(hw->dev, "rx dma map error\n");
  294. }
  295. } else {
  296. if (t->len > hw->dma_rx_tmpbuf_size) {
  297. int ret;
  298. au1550_spi_dma_rxtmp_free(hw);
  299. ret = au1550_spi_dma_rxtmp_alloc(hw, max(t->len,
  300. AU1550_SPI_DMA_RXTMP_MINSIZE));
  301. if (ret < 0)
  302. return ret;
  303. }
  304. hw->rx = hw->dma_rx_tmpbuf;
  305. dma_rx_addr = hw->dma_rx_tmpbuf_addr;
  306. dma_sync_single_for_device(hw->dev, dma_rx_addr,
  307. t->len, DMA_FROM_DEVICE);
  308. }
  309. if (!t->tx_buf) {
  310. dma_sync_single_for_device(hw->dev, dma_rx_addr,
  311. t->len, DMA_BIDIRECTIONAL);
  312. hw->tx = hw->rx;
  313. }
  314. /* put buffers on the ring */
  315. res = au1xxx_dbdma_put_dest(hw->dma_rx_ch, virt_to_phys(hw->rx),
  316. t->len, DDMA_FLAGS_IE);
  317. if (!res)
  318. dev_err(hw->dev, "rx dma put dest error\n");
  319. res = au1xxx_dbdma_put_source(hw->dma_tx_ch, virt_to_phys(hw->tx),
  320. t->len, DDMA_FLAGS_IE);
  321. if (!res)
  322. dev_err(hw->dev, "tx dma put source error\n");
  323. au1xxx_dbdma_start(hw->dma_rx_ch);
  324. au1xxx_dbdma_start(hw->dma_tx_ch);
  325. /* by default enable nearly all events interrupt */
  326. hw->regs->psc_spimsk = PSC_SPIMSK_SD;
  327. wmb(); /* drain writebuffer */
  328. /* start the transfer */
  329. hw->regs->psc_spipcr = PSC_SPIPCR_MS;
  330. wmb(); /* drain writebuffer */
  331. wait_for_completion(&hw->master_done);
  332. au1xxx_dbdma_stop(hw->dma_tx_ch);
  333. au1xxx_dbdma_stop(hw->dma_rx_ch);
  334. if (!t->rx_buf) {
  335. /* using the temporal preallocated and premapped buffer */
  336. dma_sync_single_for_cpu(hw->dev, dma_rx_addr, t->len,
  337. DMA_FROM_DEVICE);
  338. }
  339. /* unmap buffers if mapped above */
  340. if (t->rx_buf && t->rx_dma == 0 )
  341. dma_unmap_single(hw->dev, dma_rx_addr, t->len,
  342. DMA_FROM_DEVICE);
  343. if (t->tx_buf && t->tx_dma == 0 )
  344. dma_unmap_single(hw->dev, dma_tx_addr, t->len,
  345. DMA_TO_DEVICE);
  346. return hw->rx_count < hw->tx_count ? hw->rx_count : hw->tx_count;
  347. }
  348. static irqreturn_t au1550_spi_dma_irq_callback(struct au1550_spi *hw)
  349. {
  350. u32 stat, evnt;
  351. stat = hw->regs->psc_spistat;
  352. evnt = hw->regs->psc_spievent;
  353. wmb(); /* drain writebuffer */
  354. if ((stat & PSC_SPISTAT_DI) == 0) {
  355. dev_err(hw->dev, "Unexpected IRQ!\n");
  356. return IRQ_NONE;
  357. }
  358. if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO
  359. | PSC_SPIEVNT_RU | PSC_SPIEVNT_TO
  360. | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD))
  361. != 0) {
  362. /*
  363. * due to an spi error we consider transfer as done,
  364. * so mask all events until before next transfer start
  365. * and stop the possibly running dma immediately
  366. */
  367. au1550_spi_mask_ack_all(hw);
  368. au1xxx_dbdma_stop(hw->dma_rx_ch);
  369. au1xxx_dbdma_stop(hw->dma_tx_ch);
  370. /* get number of transferred bytes */
  371. hw->rx_count = hw->len - au1xxx_get_dma_residue(hw->dma_rx_ch);
  372. hw->tx_count = hw->len - au1xxx_get_dma_residue(hw->dma_tx_ch);
  373. au1xxx_dbdma_reset(hw->dma_rx_ch);
  374. au1xxx_dbdma_reset(hw->dma_tx_ch);
  375. au1550_spi_reset_fifos(hw);
  376. if (evnt == PSC_SPIEVNT_RO)
  377. dev_err(hw->dev,
  378. "dma transfer: receive FIFO overflow!\n");
  379. else
  380. dev_err(hw->dev,
  381. "dma transfer: unexpected SPI error "
  382. "(event=0x%x stat=0x%x)!\n", evnt, stat);
  383. complete(&hw->master_done);
  384. return IRQ_HANDLED;
  385. }
  386. if ((evnt & PSC_SPIEVNT_MD) != 0) {
  387. /* transfer completed successfully */
  388. au1550_spi_mask_ack_all(hw);
  389. hw->rx_count = hw->len;
  390. hw->tx_count = hw->len;
  391. complete(&hw->master_done);
  392. }
  393. return IRQ_HANDLED;
  394. }
  395. /* routines to handle different word sizes in pio mode */
  396. #define AU1550_SPI_RX_WORD(size, mask) \
  397. static void au1550_spi_rx_word_##size(struct au1550_spi *hw) \
  398. { \
  399. u32 fifoword = hw->regs->psc_spitxrx & (u32)(mask); \
  400. wmb(); /* drain writebuffer */ \
  401. if (hw->rx) { \
  402. *(u##size *)hw->rx = (u##size)fifoword; \
  403. hw->rx += (size) / 8; \
  404. } \
  405. hw->rx_count += (size) / 8; \
  406. }
  407. #define AU1550_SPI_TX_WORD(size, mask) \
  408. static void au1550_spi_tx_word_##size(struct au1550_spi *hw) \
  409. { \
  410. u32 fifoword = 0; \
  411. if (hw->tx) { \
  412. fifoword = *(u##size *)hw->tx & (u32)(mask); \
  413. hw->tx += (size) / 8; \
  414. } \
  415. hw->tx_count += (size) / 8; \
  416. if (hw->tx_count >= hw->len) \
  417. fifoword |= PSC_SPITXRX_LC; \
  418. hw->regs->psc_spitxrx = fifoword; \
  419. wmb(); /* drain writebuffer */ \
  420. }
  421. AU1550_SPI_RX_WORD(8,0xff)
  422. AU1550_SPI_RX_WORD(16,0xffff)
  423. AU1550_SPI_RX_WORD(32,0xffffff)
  424. AU1550_SPI_TX_WORD(8,0xff)
  425. AU1550_SPI_TX_WORD(16,0xffff)
  426. AU1550_SPI_TX_WORD(32,0xffffff)
  427. static int au1550_spi_pio_txrxb(struct spi_device *spi, struct spi_transfer *t)
  428. {
  429. u32 stat, mask;
  430. struct au1550_spi *hw = spi_master_get_devdata(spi->master);
  431. hw->tx = t->tx_buf;
  432. hw->rx = t->rx_buf;
  433. hw->len = t->len;
  434. hw->tx_count = 0;
  435. hw->rx_count = 0;
  436. /* by default enable nearly all events after filling tx fifo */
  437. mask = PSC_SPIMSK_SD;
  438. /* fill the transmit FIFO */
  439. while (hw->tx_count < hw->len) {
  440. hw->tx_word(hw);
  441. if (hw->tx_count >= hw->len) {
  442. /* mask tx fifo request interrupt as we are done */
  443. mask |= PSC_SPIMSK_TR;
  444. }
  445. stat = hw->regs->psc_spistat;
  446. wmb(); /* drain writebuffer */
  447. if (stat & PSC_SPISTAT_TF)
  448. break;
  449. }
  450. /* enable event interrupts */
  451. hw->regs->psc_spimsk = mask;
  452. wmb(); /* drain writebuffer */
  453. /* start the transfer */
  454. hw->regs->psc_spipcr = PSC_SPIPCR_MS;
  455. wmb(); /* drain writebuffer */
  456. wait_for_completion(&hw->master_done);
  457. return hw->rx_count < hw->tx_count ? hw->rx_count : hw->tx_count;
  458. }
  459. static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw)
  460. {
  461. int busy;
  462. u32 stat, evnt;
  463. stat = hw->regs->psc_spistat;
  464. evnt = hw->regs->psc_spievent;
  465. wmb(); /* drain writebuffer */
  466. if ((stat & PSC_SPISTAT_DI) == 0) {
  467. dev_err(hw->dev, "Unexpected IRQ!\n");
  468. return IRQ_NONE;
  469. }
  470. if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO
  471. | PSC_SPIEVNT_RU | PSC_SPIEVNT_TO
  472. | PSC_SPIEVNT_SD))
  473. != 0) {
  474. /*
  475. * due to an error we consider transfer as done,
  476. * so mask all events until before next transfer start
  477. */
  478. au1550_spi_mask_ack_all(hw);
  479. au1550_spi_reset_fifos(hw);
  480. dev_err(hw->dev,
  481. "pio transfer: unexpected SPI error "
  482. "(event=0x%x stat=0x%x)!\n", evnt, stat);
  483. complete(&hw->master_done);
  484. return IRQ_HANDLED;
  485. }
  486. /*
  487. * while there is something to read from rx fifo
  488. * or there is a space to write to tx fifo:
  489. */
  490. do {
  491. busy = 0;
  492. stat = hw->regs->psc_spistat;
  493. wmb(); /* drain writebuffer */
  494. /*
  495. * Take care to not let the Rx FIFO overflow.
  496. *
  497. * We only write a byte if we have read one at least. Initially,
  498. * the write fifo is full, so we should read from the read fifo
  499. * first.
  500. * In case we miss a word from the read fifo, we should get a
  501. * RO event and should back out.
  502. */
  503. if (!(stat & PSC_SPISTAT_RE) && hw->rx_count < hw->len) {
  504. hw->rx_word(hw);
  505. busy = 1;
  506. if (!(stat & PSC_SPISTAT_TF) && hw->tx_count < hw->len)
  507. hw->tx_word(hw);
  508. }
  509. } while (busy);
  510. hw->regs->psc_spievent = PSC_SPIEVNT_RR | PSC_SPIEVNT_TR;
  511. wmb(); /* drain writebuffer */
  512. /*
  513. * Restart the SPI transmission in case of a transmit underflow.
  514. * This seems to work despite the notes in the Au1550 data book
  515. * of Figure 8-4 with flowchart for SPI master operation:
  516. *
  517. * """Note 1: An XFR Error Interrupt occurs, unless masked,
  518. * for any of the following events: Tx FIFO Underflow,
  519. * Rx FIFO Overflow, or Multiple-master Error
  520. * Note 2: In case of a Tx Underflow Error, all zeroes are
  521. * transmitted."""
  522. *
  523. * By simply restarting the spi transfer on Tx Underflow Error,
  524. * we assume that spi transfer was paused instead of zeroes
  525. * transmittion mentioned in the Note 2 of Au1550 data book.
  526. */
  527. if (evnt & PSC_SPIEVNT_TU) {
  528. hw->regs->psc_spievent = PSC_SPIEVNT_TU | PSC_SPIEVNT_MD;
  529. wmb(); /* drain writebuffer */
  530. hw->regs->psc_spipcr = PSC_SPIPCR_MS;
  531. wmb(); /* drain writebuffer */
  532. }
  533. if (hw->rx_count >= hw->len) {
  534. /* transfer completed successfully */
  535. au1550_spi_mask_ack_all(hw);
  536. complete(&hw->master_done);
  537. }
  538. return IRQ_HANDLED;
  539. }
  540. static int au1550_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
  541. {
  542. struct au1550_spi *hw = spi_master_get_devdata(spi->master);
  543. return hw->txrx_bufs(spi, t);
  544. }
  545. static irqreturn_t au1550_spi_irq(int irq, void *dev)
  546. {
  547. struct au1550_spi *hw = dev;
  548. return hw->irq_callback(hw);
  549. }
  550. static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw)
  551. {
  552. if (bpw <= 8) {
  553. if (hw->usedma) {
  554. hw->txrx_bufs = &au1550_spi_dma_txrxb;
  555. hw->irq_callback = &au1550_spi_dma_irq_callback;
  556. } else {
  557. hw->rx_word = &au1550_spi_rx_word_8;
  558. hw->tx_word = &au1550_spi_tx_word_8;
  559. hw->txrx_bufs = &au1550_spi_pio_txrxb;
  560. hw->irq_callback = &au1550_spi_pio_irq_callback;
  561. }
  562. } else if (bpw <= 16) {
  563. hw->rx_word = &au1550_spi_rx_word_16;
  564. hw->tx_word = &au1550_spi_tx_word_16;
  565. hw->txrx_bufs = &au1550_spi_pio_txrxb;
  566. hw->irq_callback = &au1550_spi_pio_irq_callback;
  567. } else {
  568. hw->rx_word = &au1550_spi_rx_word_32;
  569. hw->tx_word = &au1550_spi_tx_word_32;
  570. hw->txrx_bufs = &au1550_spi_pio_txrxb;
  571. hw->irq_callback = &au1550_spi_pio_irq_callback;
  572. }
  573. }
  574. static void au1550_spi_setup_psc_as_spi(struct au1550_spi *hw)
  575. {
  576. u32 stat, cfg;
  577. /* set up the PSC for SPI mode */
  578. hw->regs->psc_ctrl = PSC_CTRL_DISABLE;
  579. wmb(); /* drain writebuffer */
  580. hw->regs->psc_sel = PSC_SEL_PS_SPIMODE;
  581. wmb(); /* drain writebuffer */
  582. hw->regs->psc_spicfg = 0;
  583. wmb(); /* drain writebuffer */
  584. hw->regs->psc_ctrl = PSC_CTRL_ENABLE;
  585. wmb(); /* drain writebuffer */
  586. do {
  587. stat = hw->regs->psc_spistat;
  588. wmb(); /* drain writebuffer */
  589. } while ((stat & PSC_SPISTAT_SR) == 0);
  590. cfg = hw->usedma ? 0 : PSC_SPICFG_DD_DISABLE;
  591. cfg |= PSC_SPICFG_SET_LEN(8);
  592. cfg |= PSC_SPICFG_RT_FIFO8 | PSC_SPICFG_TT_FIFO8;
  593. /* use minimal allowed brg and div values as initial setting: */
  594. cfg |= PSC_SPICFG_SET_BAUD(4) | PSC_SPICFG_SET_DIV(0);
  595. #ifdef AU1550_SPI_DEBUG_LOOPBACK
  596. cfg |= PSC_SPICFG_LB;
  597. #endif
  598. hw->regs->psc_spicfg = cfg;
  599. wmb(); /* drain writebuffer */
  600. au1550_spi_mask_ack_all(hw);
  601. hw->regs->psc_spicfg |= PSC_SPICFG_DE_ENABLE;
  602. wmb(); /* drain writebuffer */
  603. do {
  604. stat = hw->regs->psc_spistat;
  605. wmb(); /* drain writebuffer */
  606. } while ((stat & PSC_SPISTAT_DR) == 0);
  607. au1550_spi_reset_fifos(hw);
  608. }
  609. static int au1550_spi_probe(struct platform_device *pdev)
  610. {
  611. struct au1550_spi *hw;
  612. struct spi_master *master;
  613. struct resource *r;
  614. int err = 0;
  615. master = spi_alloc_master(&pdev->dev, sizeof(struct au1550_spi));
  616. if (master == NULL) {
  617. dev_err(&pdev->dev, "No memory for spi_master\n");
  618. err = -ENOMEM;
  619. goto err_nomem;
  620. }
  621. /* the spi->mode bits understood by this driver: */
  622. master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
  623. master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 24);
  624. hw = spi_master_get_devdata(master);
  625. hw->master = master;
  626. hw->pdata = dev_get_platdata(&pdev->dev);
  627. hw->dev = &pdev->dev;
  628. if (hw->pdata == NULL) {
  629. dev_err(&pdev->dev, "No platform data supplied\n");
  630. err = -ENOENT;
  631. goto err_no_pdata;
  632. }
  633. r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  634. if (!r) {
  635. dev_err(&pdev->dev, "no IRQ\n");
  636. err = -ENODEV;
  637. goto err_no_iores;
  638. }
  639. hw->irq = r->start;
  640. hw->usedma = 0;
  641. r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
  642. if (r) {
  643. hw->dma_tx_id = r->start;
  644. r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
  645. if (r) {
  646. hw->dma_rx_id = r->start;
  647. if (usedma && ddma_memid) {
  648. if (pdev->dev.dma_mask == NULL)
  649. dev_warn(&pdev->dev, "no dma mask\n");
  650. else
  651. hw->usedma = 1;
  652. }
  653. }
  654. }
  655. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  656. if (!r) {
  657. dev_err(&pdev->dev, "no mmio resource\n");
  658. err = -ENODEV;
  659. goto err_no_iores;
  660. }
  661. hw->ioarea = request_mem_region(r->start, sizeof(psc_spi_t),
  662. pdev->name);
  663. if (!hw->ioarea) {
  664. dev_err(&pdev->dev, "Cannot reserve iomem region\n");
  665. err = -ENXIO;
  666. goto err_no_iores;
  667. }
  668. hw->regs = (psc_spi_t __iomem *)ioremap(r->start, sizeof(psc_spi_t));
  669. if (!hw->regs) {
  670. dev_err(&pdev->dev, "cannot ioremap\n");
  671. err = -ENXIO;
  672. goto err_ioremap;
  673. }
  674. platform_set_drvdata(pdev, hw);
  675. init_completion(&hw->master_done);
  676. hw->bitbang.master = hw->master;
  677. hw->bitbang.setup_transfer = au1550_spi_setupxfer;
  678. hw->bitbang.chipselect = au1550_spi_chipsel;
  679. hw->bitbang.txrx_bufs = au1550_spi_txrx_bufs;
  680. if (hw->usedma) {
  681. hw->dma_tx_ch = au1xxx_dbdma_chan_alloc(ddma_memid,
  682. hw->dma_tx_id, NULL, (void *)hw);
  683. if (hw->dma_tx_ch == 0) {
  684. dev_err(&pdev->dev,
  685. "Cannot allocate tx dma channel\n");
  686. err = -ENXIO;
  687. goto err_no_txdma;
  688. }
  689. au1xxx_dbdma_set_devwidth(hw->dma_tx_ch, 8);
  690. if (au1xxx_dbdma_ring_alloc(hw->dma_tx_ch,
  691. AU1550_SPI_DBDMA_DESCRIPTORS) == 0) {
  692. dev_err(&pdev->dev,
  693. "Cannot allocate tx dma descriptors\n");
  694. err = -ENXIO;
  695. goto err_no_txdma_descr;
  696. }
  697. hw->dma_rx_ch = au1xxx_dbdma_chan_alloc(hw->dma_rx_id,
  698. ddma_memid, NULL, (void *)hw);
  699. if (hw->dma_rx_ch == 0) {
  700. dev_err(&pdev->dev,
  701. "Cannot allocate rx dma channel\n");
  702. err = -ENXIO;
  703. goto err_no_rxdma;
  704. }
  705. au1xxx_dbdma_set_devwidth(hw->dma_rx_ch, 8);
  706. if (au1xxx_dbdma_ring_alloc(hw->dma_rx_ch,
  707. AU1550_SPI_DBDMA_DESCRIPTORS) == 0) {
  708. dev_err(&pdev->dev,
  709. "Cannot allocate rx dma descriptors\n");
  710. err = -ENXIO;
  711. goto err_no_rxdma_descr;
  712. }
  713. err = au1550_spi_dma_rxtmp_alloc(hw,
  714. AU1550_SPI_DMA_RXTMP_MINSIZE);
  715. if (err < 0) {
  716. dev_err(&pdev->dev,
  717. "Cannot allocate initial rx dma tmp buffer\n");
  718. goto err_dma_rxtmp_alloc;
  719. }
  720. }
  721. au1550_spi_bits_handlers_set(hw, 8);
  722. err = request_irq(hw->irq, au1550_spi_irq, 0, pdev->name, hw);
  723. if (err) {
  724. dev_err(&pdev->dev, "Cannot claim IRQ\n");
  725. goto err_no_irq;
  726. }
  727. master->bus_num = pdev->id;
  728. master->num_chipselect = hw->pdata->num_chipselect;
  729. /*
  730. * precompute valid range for spi freq - from au1550 datasheet:
  731. * psc_tempclk = psc_mainclk / (2 << DIV)
  732. * spiclk = psc_tempclk / (2 * (BRG + 1))
  733. * BRG valid range is 4..63
  734. * DIV valid range is 0..3
  735. * round the min and max frequencies to values that would still
  736. * produce valid brg and div
  737. */
  738. {
  739. int min_div = (2 << 0) * (2 * (4 + 1));
  740. int max_div = (2 << 3) * (2 * (63 + 1));
  741. master->max_speed_hz = hw->pdata->mainclk_hz / min_div;
  742. master->min_speed_hz =
  743. hw->pdata->mainclk_hz / (max_div + 1) + 1;
  744. }
  745. au1550_spi_setup_psc_as_spi(hw);
  746. err = spi_bitbang_start(&hw->bitbang);
  747. if (err) {
  748. dev_err(&pdev->dev, "Failed to register SPI master\n");
  749. goto err_register;
  750. }
  751. dev_info(&pdev->dev,
  752. "spi master registered: bus_num=%d num_chipselect=%d\n",
  753. master->bus_num, master->num_chipselect);
  754. return 0;
  755. err_register:
  756. free_irq(hw->irq, hw);
  757. err_no_irq:
  758. au1550_spi_dma_rxtmp_free(hw);
  759. err_dma_rxtmp_alloc:
  760. err_no_rxdma_descr:
  761. if (hw->usedma)
  762. au1xxx_dbdma_chan_free(hw->dma_rx_ch);
  763. err_no_rxdma:
  764. err_no_txdma_descr:
  765. if (hw->usedma)
  766. au1xxx_dbdma_chan_free(hw->dma_tx_ch);
  767. err_no_txdma:
  768. iounmap((void __iomem *)hw->regs);
  769. err_ioremap:
  770. release_mem_region(r->start, sizeof(psc_spi_t));
  771. err_no_iores:
  772. err_no_pdata:
  773. spi_master_put(hw->master);
  774. err_nomem:
  775. return err;
  776. }
  777. static int au1550_spi_remove(struct platform_device *pdev)
  778. {
  779. struct au1550_spi *hw = platform_get_drvdata(pdev);
  780. dev_info(&pdev->dev, "spi master remove: bus_num=%d\n",
  781. hw->master->bus_num);
  782. spi_bitbang_stop(&hw->bitbang);
  783. free_irq(hw->irq, hw);
  784. iounmap((void __iomem *)hw->regs);
  785. release_mem_region(hw->ioarea->start, sizeof(psc_spi_t));
  786. if (hw->usedma) {
  787. au1550_spi_dma_rxtmp_free(hw);
  788. au1xxx_dbdma_chan_free(hw->dma_rx_ch);
  789. au1xxx_dbdma_chan_free(hw->dma_tx_ch);
  790. }
  791. spi_master_put(hw->master);
  792. return 0;
  793. }
  794. /* work with hotplug and coldplug */
  795. MODULE_ALIAS("platform:au1550-spi");
  796. static struct platform_driver au1550_spi_drv = {
  797. .probe = au1550_spi_probe,
  798. .remove = au1550_spi_remove,
  799. .driver = {
  800. .name = "au1550-spi",
  801. },
  802. };
  803. static int __init au1550_spi_init(void)
  804. {
  805. /*
  806. * create memory device with 8 bits dev_devwidth
  807. * needed for proper byte ordering to spi fifo
  808. */
  809. switch (alchemy_get_cputype()) {
  810. case ALCHEMY_CPU_AU1550:
  811. case ALCHEMY_CPU_AU1200:
  812. case ALCHEMY_CPU_AU1300:
  813. break;
  814. default:
  815. return -ENODEV;
  816. }
  817. if (usedma) {
  818. ddma_memid = au1xxx_ddma_add_device(&au1550_spi_mem_dbdev);
  819. if (!ddma_memid)
  820. printk(KERN_ERR "au1550-spi: cannot add memory"
  821. "dbdma device\n");
  822. }
  823. return platform_driver_register(&au1550_spi_drv);
  824. }
  825. module_init(au1550_spi_init);
  826. static void __exit au1550_spi_exit(void)
  827. {
  828. if (usedma && ddma_memid)
  829. au1xxx_ddma_del_device(ddma_memid);
  830. platform_driver_unregister(&au1550_spi_drv);
  831. }
  832. module_exit(au1550_spi_exit);
  833. MODULE_DESCRIPTION("Au1550 PSC SPI Driver");
  834. MODULE_AUTHOR("Jan Nikitenko <jan.nikitenko@gmail.com>");
  835. MODULE_LICENSE("GPL");