qcom.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (c) 2019, Linaro Limited
  3. #include <linux/clk.h>
  4. #include <linux/completion.h>
  5. #include <linux/interrupt.h>
  6. #include <linux/io.h>
  7. #include <linux/kernel.h>
  8. #include <linux/module.h>
  9. #include <linux/of.h>
  10. #include <linux/of_irq.h>
  11. #include <linux/of_device.h>
  12. #include <linux/regmap.h>
  13. #include <linux/slab.h>
  14. #include <linux/slimbus.h>
  15. #include <linux/soundwire/sdw.h>
  16. #include <linux/soundwire/sdw_registers.h>
  17. #include <sound/pcm_params.h>
  18. #include <sound/soc.h>
  19. #include "bus.h"
  20. #define SWRM_COMP_HW_VERSION 0x00
  21. #define SWRM_COMP_CFG_ADDR 0x04
  22. #define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK BIT(1)
  23. #define SWRM_COMP_CFG_ENABLE_MSK BIT(0)
  24. #define SWRM_COMP_PARAMS 0x100
  25. #define SWRM_COMP_PARAMS_DOUT_PORTS_MASK GENMASK(4, 0)
  26. #define SWRM_COMP_PARAMS_DIN_PORTS_MASK GENMASK(9, 5)
  27. #define SWRM_INTERRUPT_STATUS 0x200
  28. #define SWRM_INTERRUPT_STATUS_RMSK GENMASK(16, 0)
  29. #define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED BIT(1)
  30. #define SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS BIT(2)
  31. #define SWRM_INTERRUPT_STATUS_CMD_ERROR BIT(7)
  32. #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED BIT(10)
  33. #define SWRM_INTERRUPT_MASK_ADDR 0x204
  34. #define SWRM_INTERRUPT_CLEAR 0x208
  35. #define SWRM_INTERRUPT_CPU_EN 0x210
  36. #define SWRM_CMD_FIFO_WR_CMD 0x300
  37. #define SWRM_CMD_FIFO_RD_CMD 0x304
  38. #define SWRM_CMD_FIFO_CMD 0x308
  39. #define SWRM_CMD_FIFO_STATUS 0x30C
  40. #define SWRM_CMD_FIFO_CFG_ADDR 0x314
  41. #define SWRM_RD_WR_CMD_RETRIES 0x7
  42. #define SWRM_CMD_FIFO_RD_FIFO_ADDR 0x318
  43. #define SWRM_ENUMERATOR_CFG_ADDR 0x500
  44. #define SWRM_MCP_FRAME_CTRL_BANK_ADDR(m) (0x101C + 0x40 * (m))
  45. #define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK GENMASK(2, 0)
  46. #define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK GENMASK(7, 3)
  47. #define SWRM_MCP_CFG_ADDR 0x1048
  48. #define SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK GENMASK(21, 17)
  49. #define SWRM_DEF_CMD_NO_PINGS 0x1f
  50. #define SWRM_MCP_STATUS 0x104C
  51. #define SWRM_MCP_STATUS_BANK_NUM_MASK BIT(0)
  52. #define SWRM_MCP_SLV_STATUS 0x1090
  53. #define SWRM_MCP_SLV_STATUS_MASK GENMASK(1, 0)
  54. #define SWRM_DP_PORT_CTRL_BANK(n, m) (0x1124 + 0x100 * (n - 1) + 0x40 * m)
  55. #define SWRM_DP_BLOCK_CTRL3_BANK(n, m) (0x1138 + 0x100 * (n - 1) + 0x40 * m)
  56. #define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT 0x18
  57. #define SWRM_DP_PORT_CTRL_OFFSET2_SHFT 0x10
  58. #define SWRM_DP_PORT_CTRL_OFFSET1_SHFT 0x08
  59. #define SWRM_AHB_BRIDGE_WR_DATA_0 0xc85
  60. #define SWRM_AHB_BRIDGE_WR_ADDR_0 0xc89
  61. #define SWRM_AHB_BRIDGE_RD_ADDR_0 0xc8d
  62. #define SWRM_AHB_BRIDGE_RD_DATA_0 0xc91
  63. #define SWRM_REG_VAL_PACK(data, dev, id, reg) \
  64. ((reg) | ((id) << 16) | ((dev) << 20) | ((data) << 24))
  65. #define SWRM_SPECIAL_CMD_ID 0xF
  66. #define MAX_FREQ_NUM 1
  67. #define TIMEOUT_MS (2 * HZ)
  68. #define QCOM_SWRM_MAX_RD_LEN 0xf
  69. #define QCOM_SDW_MAX_PORTS 14
  70. #define DEFAULT_CLK_FREQ 9600000
  71. #define SWRM_MAX_DAIS 0xF
  72. struct qcom_swrm_port_config {
  73. u8 si;
  74. u8 off1;
  75. u8 off2;
  76. u8 bp_mode;
  77. };
  78. struct qcom_swrm_ctrl {
  79. struct sdw_bus bus;
  80. struct device *dev;
  81. struct regmap *regmap;
  82. void __iomem *mmio;
  83. struct completion *comp;
  84. struct work_struct slave_work;
  85. /* read/write lock */
  86. spinlock_t comp_lock;
  87. /* Port alloc/free lock */
  88. struct mutex port_lock;
  89. struct clk *hclk;
  90. u8 wr_cmd_id;
  91. u8 rd_cmd_id;
  92. int irq;
  93. unsigned int version;
  94. int num_din_ports;
  95. int num_dout_ports;
  96. int cols_index;
  97. int rows_index;
  98. unsigned long dout_port_mask;
  99. unsigned long din_port_mask;
  100. struct qcom_swrm_port_config pconfig[QCOM_SDW_MAX_PORTS];
  101. struct sdw_stream_runtime *sruntime[SWRM_MAX_DAIS];
  102. enum sdw_slave_status status[SDW_MAX_DEVICES];
  103. int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val);
  104. int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val);
  105. };
  106. struct qcom_swrm_data {
  107. u32 default_cols;
  108. u32 default_rows;
  109. };
  110. static struct qcom_swrm_data swrm_v1_3_data = {
  111. .default_rows = 48,
  112. .default_cols = 16,
  113. };
  114. static struct qcom_swrm_data swrm_v1_5_data = {
  115. .default_rows = 50,
  116. .default_cols = 16,
  117. };
  118. #define to_qcom_sdw(b) container_of(b, struct qcom_swrm_ctrl, bus)
  119. static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
  120. u32 *val)
  121. {
  122. struct regmap *wcd_regmap = ctrl->regmap;
  123. int ret;
  124. /* pg register + offset */
  125. ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_RD_ADDR_0,
  126. (u8 *)&reg, 4);
  127. if (ret < 0)
  128. return SDW_CMD_FAIL;
  129. ret = regmap_bulk_read(wcd_regmap, SWRM_AHB_BRIDGE_RD_DATA_0,
  130. val, 4);
  131. if (ret < 0)
  132. return SDW_CMD_FAIL;
  133. return SDW_CMD_OK;
  134. }
  135. static int qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl *ctrl,
  136. int reg, int val)
  137. {
  138. struct regmap *wcd_regmap = ctrl->regmap;
  139. int ret;
  140. /* pg register + offset */
  141. ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_DATA_0,
  142. (u8 *)&val, 4);
  143. if (ret)
  144. return SDW_CMD_FAIL;
  145. /* write address register */
  146. ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_ADDR_0,
  147. (u8 *)&reg, 4);
  148. if (ret)
  149. return SDW_CMD_FAIL;
  150. return SDW_CMD_OK;
  151. }
  152. static int qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
  153. u32 *val)
  154. {
  155. *val = readl(ctrl->mmio + reg);
  156. return SDW_CMD_OK;
  157. }
  158. static int qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl *ctrl, int reg,
  159. int val)
  160. {
  161. writel(val, ctrl->mmio + reg);
  162. return SDW_CMD_OK;
  163. }
  164. static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *ctrl, u8 cmd_data,
  165. u8 dev_addr, u16 reg_addr)
  166. {
  167. DECLARE_COMPLETION_ONSTACK(comp);
  168. unsigned long flags;
  169. u32 val;
  170. int ret;
  171. spin_lock_irqsave(&ctrl->comp_lock, flags);
  172. ctrl->comp = &comp;
  173. spin_unlock_irqrestore(&ctrl->comp_lock, flags);
  174. val = SWRM_REG_VAL_PACK(cmd_data, dev_addr,
  175. SWRM_SPECIAL_CMD_ID, reg_addr);
  176. ret = ctrl->reg_write(ctrl, SWRM_CMD_FIFO_WR_CMD, val);
  177. if (ret)
  178. goto err;
  179. ret = wait_for_completion_timeout(ctrl->comp,
  180. msecs_to_jiffies(TIMEOUT_MS));
  181. if (!ret)
  182. ret = SDW_CMD_IGNORED;
  183. else
  184. ret = SDW_CMD_OK;
  185. err:
  186. spin_lock_irqsave(&ctrl->comp_lock, flags);
  187. ctrl->comp = NULL;
  188. spin_unlock_irqrestore(&ctrl->comp_lock, flags);
  189. return ret;
  190. }
  191. static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *ctrl,
  192. u8 dev_addr, u16 reg_addr,
  193. u32 len, u8 *rval)
  194. {
  195. int i, ret;
  196. u32 val;
  197. DECLARE_COMPLETION_ONSTACK(comp);
  198. unsigned long flags;
  199. spin_lock_irqsave(&ctrl->comp_lock, flags);
  200. ctrl->comp = &comp;
  201. spin_unlock_irqrestore(&ctrl->comp_lock, flags);
  202. val = SWRM_REG_VAL_PACK(len, dev_addr, SWRM_SPECIAL_CMD_ID, reg_addr);
  203. ret = ctrl->reg_write(ctrl, SWRM_CMD_FIFO_RD_CMD, val);
  204. if (ret)
  205. goto err;
  206. ret = wait_for_completion_timeout(ctrl->comp,
  207. msecs_to_jiffies(TIMEOUT_MS));
  208. if (!ret) {
  209. ret = SDW_CMD_IGNORED;
  210. goto err;
  211. } else {
  212. ret = SDW_CMD_OK;
  213. }
  214. for (i = 0; i < len; i++) {
  215. ctrl->reg_read(ctrl, SWRM_CMD_FIFO_RD_FIFO_ADDR, &val);
  216. rval[i] = val & 0xFF;
  217. }
  218. err:
  219. spin_lock_irqsave(&ctrl->comp_lock, flags);
  220. ctrl->comp = NULL;
  221. spin_unlock_irqrestore(&ctrl->comp_lock, flags);
  222. return ret;
  223. }
  224. static void qcom_swrm_get_device_status(struct qcom_swrm_ctrl *ctrl)
  225. {
  226. u32 val;
  227. int i;
  228. ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
  229. for (i = 0; i < SDW_MAX_DEVICES; i++) {
  230. u32 s;
  231. s = (val >> (i * 2));
  232. s &= SWRM_MCP_SLV_STATUS_MASK;
  233. ctrl->status[i] = s;
  234. }
  235. }
  236. static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id)
  237. {
  238. struct qcom_swrm_ctrl *ctrl = dev_id;
  239. u32 sts, value;
  240. unsigned long flags;
  241. ctrl->reg_read(ctrl, SWRM_INTERRUPT_STATUS, &sts);
  242. if (sts & SWRM_INTERRUPT_STATUS_CMD_ERROR) {
  243. ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value);
  244. dev_err_ratelimited(ctrl->dev,
  245. "CMD error, fifo status 0x%x\n",
  246. value);
  247. ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1);
  248. }
  249. if ((sts & SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED) ||
  250. sts & SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS)
  251. schedule_work(&ctrl->slave_work);
  252. /**
  253. * clear the interrupt before complete() is called, as complete can
  254. * schedule new read/writes which require interrupts, clearing the
  255. * interrupt would avoid missing interrupts in such cases.
  256. */
  257. ctrl->reg_write(ctrl, SWRM_INTERRUPT_CLEAR, sts);
  258. if (sts & SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED) {
  259. spin_lock_irqsave(&ctrl->comp_lock, flags);
  260. if (ctrl->comp)
  261. complete(ctrl->comp);
  262. spin_unlock_irqrestore(&ctrl->comp_lock, flags);
  263. }
  264. return IRQ_HANDLED;
  265. }
  266. static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
  267. {
  268. u32 val;
  269. /* Clear Rows and Cols */
  270. val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index);
  271. val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index);
  272. ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val);
  273. /* Disable Auto enumeration */
  274. ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 0);
  275. /* Mask soundwire interrupts */
  276. ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR,
  277. SWRM_INTERRUPT_STATUS_RMSK);
  278. /* Configure No pings */
  279. ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val);
  280. u32p_replace_bits(&val, SWRM_DEF_CMD_NO_PINGS, SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK);
  281. ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val);
  282. /* Configure number of retries of a read/write cmd */
  283. ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR, SWRM_RD_WR_CMD_RETRIES);
  284. /* Set IRQ to PULSE */
  285. ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,
  286. SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK |
  287. SWRM_COMP_CFG_ENABLE_MSK);
  288. /* enable CPU IRQs */
  289. if (ctrl->mmio) {
  290. ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN,
  291. SWRM_INTERRUPT_STATUS_RMSK);
  292. }
  293. return 0;
  294. }
  295. static enum sdw_command_response qcom_swrm_xfer_msg(struct sdw_bus *bus,
  296. struct sdw_msg *msg)
  297. {
  298. struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
  299. int ret, i, len;
  300. if (msg->flags == SDW_MSG_FLAG_READ) {
  301. for (i = 0; i < msg->len;) {
  302. if ((msg->len - i) < QCOM_SWRM_MAX_RD_LEN)
  303. len = msg->len - i;
  304. else
  305. len = QCOM_SWRM_MAX_RD_LEN;
  306. ret = qcom_swrm_cmd_fifo_rd_cmd(ctrl, msg->dev_num,
  307. msg->addr + i, len,
  308. &msg->buf[i]);
  309. if (ret)
  310. return ret;
  311. i = i + len;
  312. }
  313. } else if (msg->flags == SDW_MSG_FLAG_WRITE) {
  314. for (i = 0; i < msg->len; i++) {
  315. ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, msg->buf[i],
  316. msg->dev_num,
  317. msg->addr + i);
  318. if (ret)
  319. return SDW_CMD_IGNORED;
  320. }
  321. }
  322. return SDW_CMD_OK;
  323. }
  324. static int qcom_swrm_pre_bank_switch(struct sdw_bus *bus)
  325. {
  326. u32 reg = SWRM_MCP_FRAME_CTRL_BANK_ADDR(bus->params.next_bank);
  327. struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
  328. u32 val;
  329. ctrl->reg_read(ctrl, reg, &val);
  330. u32p_replace_bits(&val, ctrl->cols_index, SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK);
  331. u32p_replace_bits(&val, ctrl->rows_index, SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK);
  332. return ctrl->reg_write(ctrl, reg, val);
  333. }
  334. static int qcom_swrm_port_params(struct sdw_bus *bus,
  335. struct sdw_port_params *p_params,
  336. unsigned int bank)
  337. {
  338. /* TBD */
  339. return 0;
  340. }
  341. static int qcom_swrm_transport_params(struct sdw_bus *bus,
  342. struct sdw_transport_params *params,
  343. enum sdw_reg_bank bank)
  344. {
  345. struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
  346. u32 value;
  347. int reg = SWRM_DP_PORT_CTRL_BANK((params->port_num), bank);
  348. int ret;
  349. value = params->offset1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT;
  350. value |= params->offset2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT;
  351. value |= params->sample_interval - 1;
  352. ret = ctrl->reg_write(ctrl, reg, value);
  353. if (!ret && params->blk_pkg_mode) {
  354. reg = SWRM_DP_BLOCK_CTRL3_BANK(params->port_num, bank);
  355. ret = ctrl->reg_write(ctrl, reg, 1);
  356. }
  357. return ret;
  358. }
  359. static int qcom_swrm_port_enable(struct sdw_bus *bus,
  360. struct sdw_enable_ch *enable_ch,
  361. unsigned int bank)
  362. {
  363. u32 reg = SWRM_DP_PORT_CTRL_BANK(enable_ch->port_num, bank);
  364. struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
  365. u32 val;
  366. ctrl->reg_read(ctrl, reg, &val);
  367. if (enable_ch->enable)
  368. val |= (enable_ch->ch_mask << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
  369. else
  370. val &= ~(0xff << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
  371. return ctrl->reg_write(ctrl, reg, val);
  372. }
  373. static const struct sdw_master_port_ops qcom_swrm_port_ops = {
  374. .dpn_set_port_params = qcom_swrm_port_params,
  375. .dpn_set_port_transport_params = qcom_swrm_transport_params,
  376. .dpn_port_enable_ch = qcom_swrm_port_enable,
  377. };
  378. static const struct sdw_master_ops qcom_swrm_ops = {
  379. .xfer_msg = qcom_swrm_xfer_msg,
  380. .pre_bank_switch = qcom_swrm_pre_bank_switch,
  381. };
  382. static int qcom_swrm_compute_params(struct sdw_bus *bus)
  383. {
  384. struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
  385. struct sdw_master_runtime *m_rt;
  386. struct sdw_slave_runtime *s_rt;
  387. struct sdw_port_runtime *p_rt;
  388. struct qcom_swrm_port_config *pcfg;
  389. int i = 0;
  390. list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
  391. list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
  392. pcfg = &ctrl->pconfig[p_rt->num - 1];
  393. p_rt->transport_params.port_num = p_rt->num;
  394. p_rt->transport_params.sample_interval = pcfg->si + 1;
  395. p_rt->transport_params.offset1 = pcfg->off1;
  396. p_rt->transport_params.offset2 = pcfg->off2;
  397. p_rt->transport_params.blk_pkg_mode = pcfg->bp_mode;
  398. }
  399. list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
  400. list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
  401. pcfg = &ctrl->pconfig[i];
  402. p_rt->transport_params.port_num = p_rt->num;
  403. p_rt->transport_params.sample_interval =
  404. pcfg->si + 1;
  405. p_rt->transport_params.offset1 = pcfg->off1;
  406. p_rt->transport_params.offset2 = pcfg->off2;
  407. p_rt->transport_params.blk_pkg_mode = pcfg->bp_mode;
  408. i++;
  409. }
  410. }
  411. }
  412. return 0;
  413. }
  414. static u32 qcom_swrm_freq_tbl[MAX_FREQ_NUM] = {
  415. DEFAULT_CLK_FREQ,
  416. };
  417. static void qcom_swrm_slave_wq(struct work_struct *work)
  418. {
  419. struct qcom_swrm_ctrl *ctrl =
  420. container_of(work, struct qcom_swrm_ctrl, slave_work);
  421. qcom_swrm_get_device_status(ctrl);
  422. sdw_handle_slave_status(&ctrl->bus, ctrl->status);
  423. }
  424. static void qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl *ctrl,
  425. struct sdw_stream_runtime *stream)
  426. {
  427. struct sdw_master_runtime *m_rt;
  428. struct sdw_port_runtime *p_rt;
  429. unsigned long *port_mask;
  430. mutex_lock(&ctrl->port_lock);
  431. list_for_each_entry(m_rt, &stream->master_list, stream_node) {
  432. if (m_rt->direction == SDW_DATA_DIR_RX)
  433. port_mask = &ctrl->dout_port_mask;
  434. else
  435. port_mask = &ctrl->din_port_mask;
  436. list_for_each_entry(p_rt, &m_rt->port_list, port_node)
  437. clear_bit(p_rt->num - 1, port_mask);
  438. }
  439. mutex_unlock(&ctrl->port_lock);
  440. }
  441. static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl *ctrl,
  442. struct sdw_stream_runtime *stream,
  443. struct snd_pcm_hw_params *params,
  444. int direction)
  445. {
  446. struct sdw_port_config pconfig[QCOM_SDW_MAX_PORTS];
  447. struct sdw_stream_config sconfig;
  448. struct sdw_master_runtime *m_rt;
  449. struct sdw_slave_runtime *s_rt;
  450. struct sdw_port_runtime *p_rt;
  451. unsigned long *port_mask;
  452. int i, maxport, pn, nports = 0, ret = 0;
  453. mutex_lock(&ctrl->port_lock);
  454. list_for_each_entry(m_rt, &stream->master_list, stream_node) {
  455. if (m_rt->direction == SDW_DATA_DIR_RX) {
  456. maxport = ctrl->num_dout_ports;
  457. port_mask = &ctrl->dout_port_mask;
  458. } else {
  459. maxport = ctrl->num_din_ports;
  460. port_mask = &ctrl->din_port_mask;
  461. }
  462. list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
  463. list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
  464. /* Port numbers start from 1 - 14*/
  465. pn = find_first_zero_bit(port_mask, maxport);
  466. if (pn > (maxport - 1)) {
  467. dev_err(ctrl->dev, "All ports busy\n");
  468. ret = -EBUSY;
  469. goto err;
  470. }
  471. set_bit(pn, port_mask);
  472. pconfig[nports].num = pn + 1;
  473. pconfig[nports].ch_mask = p_rt->ch_mask;
  474. nports++;
  475. }
  476. }
  477. }
  478. if (direction == SNDRV_PCM_STREAM_CAPTURE)
  479. sconfig.direction = SDW_DATA_DIR_TX;
  480. else
  481. sconfig.direction = SDW_DATA_DIR_RX;
  482. /* hw parameters wil be ignored as we only support PDM */
  483. sconfig.ch_count = 1;
  484. sconfig.frame_rate = params_rate(params);
  485. sconfig.type = stream->type;
  486. sconfig.bps = 1;
  487. sdw_stream_add_master(&ctrl->bus, &sconfig, pconfig,
  488. nports, stream);
  489. err:
  490. if (ret) {
  491. for (i = 0; i < nports; i++)
  492. clear_bit(pconfig[i].num - 1, port_mask);
  493. }
  494. mutex_unlock(&ctrl->port_lock);
  495. return ret;
  496. }
  497. static int qcom_swrm_hw_params(struct snd_pcm_substream *substream,
  498. struct snd_pcm_hw_params *params,
  499. struct snd_soc_dai *dai)
  500. {
  501. struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
  502. struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
  503. int ret;
  504. ret = qcom_swrm_stream_alloc_ports(ctrl, sruntime, params,
  505. substream->stream);
  506. if (ret)
  507. qcom_swrm_stream_free_ports(ctrl, sruntime);
  508. return ret;
  509. }
  510. static int qcom_swrm_hw_free(struct snd_pcm_substream *substream,
  511. struct snd_soc_dai *dai)
  512. {
  513. struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
  514. struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
  515. qcom_swrm_stream_free_ports(ctrl, sruntime);
  516. sdw_stream_remove_master(&ctrl->bus, sruntime);
  517. return 0;
  518. }
  519. static int qcom_swrm_set_sdw_stream(struct snd_soc_dai *dai,
  520. void *stream, int direction)
  521. {
  522. struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
  523. ctrl->sruntime[dai->id] = stream;
  524. return 0;
  525. }
  526. static void *qcom_swrm_get_sdw_stream(struct snd_soc_dai *dai, int direction)
  527. {
  528. struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
  529. return ctrl->sruntime[dai->id];
  530. }
  531. static int qcom_swrm_startup(struct snd_pcm_substream *substream,
  532. struct snd_soc_dai *dai)
  533. {
  534. struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
  535. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  536. struct sdw_stream_runtime *sruntime;
  537. struct snd_soc_dai *codec_dai;
  538. int ret, i;
  539. sruntime = sdw_alloc_stream(dai->name);
  540. if (!sruntime)
  541. return -ENOMEM;
  542. ctrl->sruntime[dai->id] = sruntime;
  543. for_each_rtd_codec_dais(rtd, i, codec_dai) {
  544. ret = snd_soc_dai_set_sdw_stream(codec_dai, sruntime,
  545. substream->stream);
  546. if (ret < 0 && ret != -ENOTSUPP) {
  547. dev_err(dai->dev, "Failed to set sdw stream on %s",
  548. codec_dai->name);
  549. sdw_release_stream(sruntime);
  550. return ret;
  551. }
  552. }
  553. return 0;
  554. }
  555. static void qcom_swrm_shutdown(struct snd_pcm_substream *substream,
  556. struct snd_soc_dai *dai)
  557. {
  558. struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
  559. sdw_release_stream(ctrl->sruntime[dai->id]);
  560. ctrl->sruntime[dai->id] = NULL;
  561. }
  562. static const struct snd_soc_dai_ops qcom_swrm_pdm_dai_ops = {
  563. .hw_params = qcom_swrm_hw_params,
  564. .hw_free = qcom_swrm_hw_free,
  565. .startup = qcom_swrm_startup,
  566. .shutdown = qcom_swrm_shutdown,
  567. .set_sdw_stream = qcom_swrm_set_sdw_stream,
  568. .get_sdw_stream = qcom_swrm_get_sdw_stream,
  569. };
  570. static const struct snd_soc_component_driver qcom_swrm_dai_component = {
  571. .name = "soundwire",
  572. };
  573. static int qcom_swrm_register_dais(struct qcom_swrm_ctrl *ctrl)
  574. {
  575. int num_dais = ctrl->num_dout_ports + ctrl->num_din_ports;
  576. struct snd_soc_dai_driver *dais;
  577. struct snd_soc_pcm_stream *stream;
  578. struct device *dev = ctrl->dev;
  579. int i;
  580. /* PDM dais are only tested for now */
  581. dais = devm_kcalloc(dev, num_dais, sizeof(*dais), GFP_KERNEL);
  582. if (!dais)
  583. return -ENOMEM;
  584. for (i = 0; i < num_dais; i++) {
  585. dais[i].name = devm_kasprintf(dev, GFP_KERNEL, "SDW Pin%d", i);
  586. if (!dais[i].name)
  587. return -ENOMEM;
  588. if (i < ctrl->num_dout_ports)
  589. stream = &dais[i].playback;
  590. else
  591. stream = &dais[i].capture;
  592. stream->channels_min = 1;
  593. stream->channels_max = 1;
  594. stream->rates = SNDRV_PCM_RATE_48000;
  595. stream->formats = SNDRV_PCM_FMTBIT_S16_LE;
  596. dais[i].ops = &qcom_swrm_pdm_dai_ops;
  597. dais[i].id = i;
  598. }
  599. return devm_snd_soc_register_component(ctrl->dev,
  600. &qcom_swrm_dai_component,
  601. dais, num_dais);
  602. }
  603. static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl)
  604. {
  605. struct device_node *np = ctrl->dev->of_node;
  606. u8 off1[QCOM_SDW_MAX_PORTS];
  607. u8 off2[QCOM_SDW_MAX_PORTS];
  608. u8 si[QCOM_SDW_MAX_PORTS];
  609. u8 bp_mode[QCOM_SDW_MAX_PORTS] = { 0, };
  610. int i, ret, nports, val;
  611. ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
  612. ctrl->num_dout_ports = FIELD_GET(SWRM_COMP_PARAMS_DOUT_PORTS_MASK, val);
  613. ctrl->num_din_ports = FIELD_GET(SWRM_COMP_PARAMS_DIN_PORTS_MASK, val);
  614. ret = of_property_read_u32(np, "qcom,din-ports", &val);
  615. if (ret)
  616. return ret;
  617. if (val > ctrl->num_din_ports)
  618. return -EINVAL;
  619. ctrl->num_din_ports = val;
  620. ret = of_property_read_u32(np, "qcom,dout-ports", &val);
  621. if (ret)
  622. return ret;
  623. if (val > ctrl->num_dout_ports)
  624. return -EINVAL;
  625. ctrl->num_dout_ports = val;
  626. nports = ctrl->num_dout_ports + ctrl->num_din_ports;
  627. ret = of_property_read_u8_array(np, "qcom,ports-offset1",
  628. off1, nports);
  629. if (ret)
  630. return ret;
  631. ret = of_property_read_u8_array(np, "qcom,ports-offset2",
  632. off2, nports);
  633. if (ret)
  634. return ret;
  635. ret = of_property_read_u8_array(np, "qcom,ports-sinterval-low",
  636. si, nports);
  637. if (ret)
  638. return ret;
  639. ret = of_property_read_u8_array(np, "qcom,ports-block-pack-mode",
  640. bp_mode, nports);
  641. for (i = 0; i < nports; i++) {
  642. ctrl->pconfig[i].si = si[i];
  643. ctrl->pconfig[i].off1 = off1[i];
  644. ctrl->pconfig[i].off2 = off2[i];
  645. ctrl->pconfig[i].bp_mode = bp_mode[i];
  646. }
  647. return 0;
  648. }
  649. static int qcom_swrm_probe(struct platform_device *pdev)
  650. {
  651. struct device *dev = &pdev->dev;
  652. struct sdw_master_prop *prop;
  653. struct sdw_bus_params *params;
  654. struct qcom_swrm_ctrl *ctrl;
  655. const struct qcom_swrm_data *data;
  656. int ret;
  657. u32 val;
  658. ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
  659. if (!ctrl)
  660. return -ENOMEM;
  661. data = of_device_get_match_data(dev);
  662. ctrl->rows_index = sdw_find_row_index(data->default_rows);
  663. ctrl->cols_index = sdw_find_col_index(data->default_cols);
  664. #if IS_REACHABLE(CONFIG_SLIMBUS)
  665. if (dev->parent->bus == &slimbus_bus) {
  666. #else
  667. if (false) {
  668. #endif
  669. ctrl->reg_read = qcom_swrm_ahb_reg_read;
  670. ctrl->reg_write = qcom_swrm_ahb_reg_write;
  671. ctrl->regmap = dev_get_regmap(dev->parent, NULL);
  672. if (!ctrl->regmap)
  673. return -EINVAL;
  674. } else {
  675. ctrl->reg_read = qcom_swrm_cpu_reg_read;
  676. ctrl->reg_write = qcom_swrm_cpu_reg_write;
  677. ctrl->mmio = devm_platform_ioremap_resource(pdev, 0);
  678. if (IS_ERR(ctrl->mmio))
  679. return PTR_ERR(ctrl->mmio);
  680. }
  681. ctrl->irq = of_irq_get(dev->of_node, 0);
  682. if (ctrl->irq < 0) {
  683. ret = ctrl->irq;
  684. goto err_init;
  685. }
  686. ctrl->hclk = devm_clk_get(dev, "iface");
  687. if (IS_ERR(ctrl->hclk)) {
  688. ret = PTR_ERR(ctrl->hclk);
  689. goto err_init;
  690. }
  691. clk_prepare_enable(ctrl->hclk);
  692. ctrl->dev = dev;
  693. dev_set_drvdata(&pdev->dev, ctrl);
  694. spin_lock_init(&ctrl->comp_lock);
  695. mutex_init(&ctrl->port_lock);
  696. INIT_WORK(&ctrl->slave_work, qcom_swrm_slave_wq);
  697. ctrl->bus.ops = &qcom_swrm_ops;
  698. ctrl->bus.port_ops = &qcom_swrm_port_ops;
  699. ctrl->bus.compute_params = &qcom_swrm_compute_params;
  700. ret = qcom_swrm_get_port_config(ctrl);
  701. if (ret)
  702. goto err_clk;
  703. params = &ctrl->bus.params;
  704. params->max_dr_freq = DEFAULT_CLK_FREQ;
  705. params->curr_dr_freq = DEFAULT_CLK_FREQ;
  706. params->col = data->default_cols;
  707. params->row = data->default_rows;
  708. ctrl->reg_read(ctrl, SWRM_MCP_STATUS, &val);
  709. params->curr_bank = val & SWRM_MCP_STATUS_BANK_NUM_MASK;
  710. params->next_bank = !params->curr_bank;
  711. prop = &ctrl->bus.prop;
  712. prop->max_clk_freq = DEFAULT_CLK_FREQ;
  713. prop->num_clk_gears = 0;
  714. prop->num_clk_freq = MAX_FREQ_NUM;
  715. prop->clk_freq = &qcom_swrm_freq_tbl[0];
  716. prop->default_col = data->default_cols;
  717. prop->default_row = data->default_rows;
  718. ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version);
  719. ret = devm_request_threaded_irq(dev, ctrl->irq, NULL,
  720. qcom_swrm_irq_handler,
  721. IRQF_TRIGGER_RISING |
  722. IRQF_ONESHOT,
  723. "soundwire", ctrl);
  724. if (ret) {
  725. dev_err(dev, "Failed to request soundwire irq\n");
  726. goto err_clk;
  727. }
  728. ret = sdw_bus_master_add(&ctrl->bus, dev, dev->fwnode);
  729. if (ret) {
  730. dev_err(dev, "Failed to register Soundwire controller (%d)\n",
  731. ret);
  732. goto err_clk;
  733. }
  734. qcom_swrm_init(ctrl);
  735. ret = qcom_swrm_register_dais(ctrl);
  736. if (ret)
  737. goto err_master_add;
  738. dev_info(dev, "Qualcomm Soundwire controller v%x.%x.%x Registered\n",
  739. (ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff,
  740. ctrl->version & 0xffff);
  741. return 0;
  742. err_master_add:
  743. sdw_bus_master_delete(&ctrl->bus);
  744. err_clk:
  745. clk_disable_unprepare(ctrl->hclk);
  746. err_init:
  747. return ret;
  748. }
  749. static int qcom_swrm_remove(struct platform_device *pdev)
  750. {
  751. struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(&pdev->dev);
  752. sdw_bus_master_delete(&ctrl->bus);
  753. clk_disable_unprepare(ctrl->hclk);
  754. return 0;
  755. }
  756. static const struct of_device_id qcom_swrm_of_match[] = {
  757. { .compatible = "qcom,soundwire-v1.3.0", .data = &swrm_v1_3_data },
  758. { .compatible = "qcom,soundwire-v1.5.1", .data = &swrm_v1_5_data },
  759. {/* sentinel */},
  760. };
  761. MODULE_DEVICE_TABLE(of, qcom_swrm_of_match);
  762. static struct platform_driver qcom_swrm_driver = {
  763. .probe = &qcom_swrm_probe,
  764. .remove = &qcom_swrm_remove,
  765. .driver = {
  766. .name = "qcom-soundwire",
  767. .of_match_table = qcom_swrm_of_match,
  768. }
  769. };
  770. module_platform_driver(qcom_swrm_driver);
  771. MODULE_DESCRIPTION("Qualcomm soundwire driver");
  772. MODULE_LICENSE("GPL v2");