pm33xx.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * AM33XX Power Management Routines
  4. *
  5. * Copyright (C) 2012-2018 Texas Instruments Incorporated - http://www.ti.com/
  6. * Vaibhav Bedia, Dave Gerlach
  7. */
  8. #include <linux/clk.h>
  9. #include <linux/cpu.h>
  10. #include <linux/err.h>
  11. #include <linux/genalloc.h>
  12. #include <linux/kernel.h>
  13. #include <linux/init.h>
  14. #include <linux/io.h>
  15. #include <linux/module.h>
  16. #include <linux/nvmem-consumer.h>
  17. #include <linux/of.h>
  18. #include <linux/of_address.h>
  19. #include <linux/platform_data/pm33xx.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/rtc.h>
  22. #include <linux/rtc/rtc-omap.h>
  23. #include <linux/sizes.h>
  24. #include <linux/sram.h>
  25. #include <linux/suspend.h>
  26. #include <linux/ti-emif-sram.h>
  27. #include <linux/wkup_m3_ipc.h>
  28. #include <asm/proc-fns.h>
  29. #include <asm/suspend.h>
  30. #include <asm/system_misc.h>
  31. #define AMX3_PM_SRAM_SYMBOL_OFFSET(sym) ((unsigned long)(sym) - \
  32. (unsigned long)pm_sram->do_wfi)
  33. #define RTC_SCRATCH_RESUME_REG 0
  34. #define RTC_SCRATCH_MAGIC_REG 1
  35. #define RTC_REG_BOOT_MAGIC 0x8cd0 /* RTC */
  36. #define GIC_INT_SET_PENDING_BASE 0x200
  37. #define AM43XX_GIC_DIST_BASE 0x48241000
  38. static void __iomem *rtc_base_virt;
  39. static struct clk *rtc_fck;
  40. static u32 rtc_magic_val;
  41. static int (*am33xx_do_wfi_sram)(unsigned long unused);
  42. static phys_addr_t am33xx_do_wfi_sram_phys;
  43. static struct gen_pool *sram_pool, *sram_pool_data;
  44. static unsigned long ocmcram_location, ocmcram_location_data;
  45. static struct rtc_device *omap_rtc;
  46. static void __iomem *gic_dist_base;
  47. static struct am33xx_pm_platform_data *pm_ops;
  48. static struct am33xx_pm_sram_addr *pm_sram;
  49. static struct device *pm33xx_dev;
  50. static struct wkup_m3_ipc *m3_ipc;
  51. #ifdef CONFIG_SUSPEND
  52. static int rtc_only_idle;
  53. static int retrigger_irq;
  54. static unsigned long suspend_wfi_flags;
  55. static struct wkup_m3_wakeup_src wakeup_src = {.irq_nr = 0,
  56. .src = "Unknown",
  57. };
  58. static struct wkup_m3_wakeup_src rtc_alarm_wakeup = {
  59. .irq_nr = 108, .src = "RTC Alarm",
  60. };
  61. static struct wkup_m3_wakeup_src rtc_ext_wakeup = {
  62. .irq_nr = 0, .src = "Ext wakeup",
  63. };
  64. #endif
  65. static u32 sram_suspend_address(unsigned long addr)
  66. {
  67. return ((unsigned long)am33xx_do_wfi_sram +
  68. AMX3_PM_SRAM_SYMBOL_OFFSET(addr));
  69. }
  70. static int am33xx_push_sram_idle(void)
  71. {
  72. struct am33xx_pm_ro_sram_data ro_sram_data;
  73. int ret;
  74. u32 table_addr, ro_data_addr;
  75. void *copy_addr;
  76. ro_sram_data.amx3_pm_sram_data_virt = ocmcram_location_data;
  77. ro_sram_data.amx3_pm_sram_data_phys =
  78. gen_pool_virt_to_phys(sram_pool_data, ocmcram_location_data);
  79. ro_sram_data.rtc_base_virt = rtc_base_virt;
  80. /* Save physical address to calculate resume offset during pm init */
  81. am33xx_do_wfi_sram_phys = gen_pool_virt_to_phys(sram_pool,
  82. ocmcram_location);
  83. am33xx_do_wfi_sram = sram_exec_copy(sram_pool, (void *)ocmcram_location,
  84. pm_sram->do_wfi,
  85. *pm_sram->do_wfi_sz);
  86. if (!am33xx_do_wfi_sram) {
  87. dev_err(pm33xx_dev,
  88. "PM: %s: am33xx_do_wfi copy to sram failed\n",
  89. __func__);
  90. return -ENODEV;
  91. }
  92. table_addr =
  93. sram_suspend_address((unsigned long)pm_sram->emif_sram_table);
  94. ret = ti_emif_copy_pm_function_table(sram_pool, (void *)table_addr);
  95. if (ret) {
  96. dev_dbg(pm33xx_dev,
  97. "PM: %s: EMIF function copy failed\n", __func__);
  98. return -EPROBE_DEFER;
  99. }
  100. ro_data_addr =
  101. sram_suspend_address((unsigned long)pm_sram->ro_sram_data);
  102. copy_addr = sram_exec_copy(sram_pool, (void *)ro_data_addr,
  103. &ro_sram_data,
  104. sizeof(ro_sram_data));
  105. if (!copy_addr) {
  106. dev_err(pm33xx_dev,
  107. "PM: %s: ro_sram_data copy to sram failed\n",
  108. __func__);
  109. return -ENODEV;
  110. }
  111. return 0;
  112. }
  113. static int am33xx_do_sram_idle(u32 wfi_flags)
  114. {
  115. int ret = 0;
  116. if (!m3_ipc || !pm_ops)
  117. return 0;
  118. if (wfi_flags & WFI_FLAG_WAKE_M3)
  119. ret = m3_ipc->ops->prepare_low_power(m3_ipc, WKUP_M3_IDLE);
  120. return pm_ops->cpu_suspend(am33xx_do_wfi_sram, wfi_flags);
  121. }
  122. static int __init am43xx_map_gic(void)
  123. {
  124. gic_dist_base = ioremap(AM43XX_GIC_DIST_BASE, SZ_4K);
  125. if (!gic_dist_base)
  126. return -ENOMEM;
  127. return 0;
  128. }
  129. #ifdef CONFIG_SUSPEND
  130. static struct wkup_m3_wakeup_src rtc_wake_src(void)
  131. {
  132. u32 i;
  133. i = __raw_readl(rtc_base_virt + 0x44) & 0x40;
  134. if (i) {
  135. retrigger_irq = rtc_alarm_wakeup.irq_nr;
  136. return rtc_alarm_wakeup;
  137. }
  138. retrigger_irq = rtc_ext_wakeup.irq_nr;
  139. return rtc_ext_wakeup;
  140. }
  141. static int am33xx_rtc_only_idle(unsigned long wfi_flags)
  142. {
  143. omap_rtc_power_off_program(&omap_rtc->dev);
  144. am33xx_do_wfi_sram(wfi_flags);
  145. return 0;
  146. }
  147. /*
  148. * Note that the RTC module clock must be re-enabled only for rtc+ddr suspend.
  149. * And looks like the module can stay in SYSC_IDLE_SMART_WKUP mode configured
  150. * by the interconnect code just fine for both rtc+ddr suspend and retention
  151. * suspend.
  152. */
  153. static int am33xx_pm_suspend(suspend_state_t suspend_state)
  154. {
  155. int i, ret = 0;
  156. if (suspend_state == PM_SUSPEND_MEM &&
  157. pm_ops->check_off_mode_enable()) {
  158. ret = clk_prepare_enable(rtc_fck);
  159. if (ret) {
  160. dev_err(pm33xx_dev, "Failed to enable clock: %i\n", ret);
  161. return ret;
  162. }
  163. pm_ops->save_context();
  164. suspend_wfi_flags |= WFI_FLAG_RTC_ONLY;
  165. clk_save_context();
  166. ret = pm_ops->soc_suspend(suspend_state, am33xx_rtc_only_idle,
  167. suspend_wfi_flags);
  168. suspend_wfi_flags &= ~WFI_FLAG_RTC_ONLY;
  169. dev_info(pm33xx_dev, "Entering RTC Only mode with DDR in self-refresh\n");
  170. if (!ret) {
  171. clk_restore_context();
  172. pm_ops->restore_context();
  173. m3_ipc->ops->set_rtc_only(m3_ipc);
  174. am33xx_push_sram_idle();
  175. }
  176. } else {
  177. ret = pm_ops->soc_suspend(suspend_state, am33xx_do_wfi_sram,
  178. suspend_wfi_flags);
  179. }
  180. if (ret) {
  181. dev_err(pm33xx_dev, "PM: Kernel suspend failure\n");
  182. } else {
  183. i = m3_ipc->ops->request_pm_status(m3_ipc);
  184. switch (i) {
  185. case 0:
  186. dev_info(pm33xx_dev,
  187. "PM: Successfully put all powerdomains to target state\n");
  188. break;
  189. case 1:
  190. dev_err(pm33xx_dev,
  191. "PM: Could not transition all powerdomains to target state\n");
  192. ret = -1;
  193. break;
  194. default:
  195. dev_err(pm33xx_dev,
  196. "PM: CM3 returned unknown result = %d\n", i);
  197. ret = -1;
  198. }
  199. /* print the wakeup reason */
  200. if (rtc_only_idle) {
  201. wakeup_src = rtc_wake_src();
  202. pr_info("PM: Wakeup source %s\n", wakeup_src.src);
  203. } else {
  204. pr_info("PM: Wakeup source %s\n",
  205. m3_ipc->ops->request_wake_src(m3_ipc));
  206. }
  207. }
  208. if (suspend_state == PM_SUSPEND_MEM && pm_ops->check_off_mode_enable())
  209. clk_disable_unprepare(rtc_fck);
  210. return ret;
  211. }
  212. static int am33xx_pm_enter(suspend_state_t suspend_state)
  213. {
  214. int ret = 0;
  215. switch (suspend_state) {
  216. case PM_SUSPEND_MEM:
  217. case PM_SUSPEND_STANDBY:
  218. ret = am33xx_pm_suspend(suspend_state);
  219. break;
  220. default:
  221. ret = -EINVAL;
  222. }
  223. return ret;
  224. }
  225. static int am33xx_pm_begin(suspend_state_t state)
  226. {
  227. int ret = -EINVAL;
  228. struct nvmem_device *nvmem;
  229. if (state == PM_SUSPEND_MEM && pm_ops->check_off_mode_enable()) {
  230. nvmem = devm_nvmem_device_get(&omap_rtc->dev,
  231. "omap_rtc_scratch0");
  232. if (!IS_ERR(nvmem))
  233. nvmem_device_write(nvmem, RTC_SCRATCH_MAGIC_REG * 4, 4,
  234. (void *)&rtc_magic_val);
  235. rtc_only_idle = 1;
  236. } else {
  237. rtc_only_idle = 0;
  238. }
  239. pm_ops->begin_suspend();
  240. switch (state) {
  241. case PM_SUSPEND_MEM:
  242. ret = m3_ipc->ops->prepare_low_power(m3_ipc, WKUP_M3_DEEPSLEEP);
  243. break;
  244. case PM_SUSPEND_STANDBY:
  245. ret = m3_ipc->ops->prepare_low_power(m3_ipc, WKUP_M3_STANDBY);
  246. break;
  247. }
  248. return ret;
  249. }
  250. static void am33xx_pm_end(void)
  251. {
  252. u32 val = 0;
  253. struct nvmem_device *nvmem;
  254. nvmem = devm_nvmem_device_get(&omap_rtc->dev, "omap_rtc_scratch0");
  255. if (IS_ERR(nvmem))
  256. return;
  257. m3_ipc->ops->finish_low_power(m3_ipc);
  258. if (rtc_only_idle) {
  259. if (retrigger_irq) {
  260. /*
  261. * 32 bits of Interrupt Set-Pending correspond to 32
  262. * 32 interrupts. Compute the bit offset of the
  263. * Interrupt and set that particular bit
  264. * Compute the register offset by dividing interrupt
  265. * number by 32 and mutiplying by 4
  266. */
  267. writel_relaxed(1 << (retrigger_irq & 31),
  268. gic_dist_base + GIC_INT_SET_PENDING_BASE
  269. + retrigger_irq / 32 * 4);
  270. }
  271. nvmem_device_write(nvmem, RTC_SCRATCH_MAGIC_REG * 4, 4,
  272. (void *)&val);
  273. }
  274. rtc_only_idle = 0;
  275. pm_ops->finish_suspend();
  276. }
  277. static int am33xx_pm_valid(suspend_state_t state)
  278. {
  279. switch (state) {
  280. case PM_SUSPEND_STANDBY:
  281. case PM_SUSPEND_MEM:
  282. return 1;
  283. default:
  284. return 0;
  285. }
  286. }
  287. static const struct platform_suspend_ops am33xx_pm_ops = {
  288. .begin = am33xx_pm_begin,
  289. .end = am33xx_pm_end,
  290. .enter = am33xx_pm_enter,
  291. .valid = am33xx_pm_valid,
  292. };
  293. #endif /* CONFIG_SUSPEND */
  294. static void am33xx_pm_set_ipc_ops(void)
  295. {
  296. u32 resume_address;
  297. int temp;
  298. temp = ti_emif_get_mem_type();
  299. if (temp < 0) {
  300. dev_err(pm33xx_dev, "PM: Cannot determine memory type, no PM available\n");
  301. return;
  302. }
  303. m3_ipc->ops->set_mem_type(m3_ipc, temp);
  304. /* Physical resume address to be used by ROM code */
  305. resume_address = am33xx_do_wfi_sram_phys +
  306. *pm_sram->resume_offset + 0x4;
  307. m3_ipc->ops->set_resume_address(m3_ipc, (void *)resume_address);
  308. }
  309. static void am33xx_pm_free_sram(void)
  310. {
  311. gen_pool_free(sram_pool, ocmcram_location, *pm_sram->do_wfi_sz);
  312. gen_pool_free(sram_pool_data, ocmcram_location_data,
  313. sizeof(struct am33xx_pm_ro_sram_data));
  314. }
  315. /*
  316. * Push the minimal suspend-resume code to SRAM
  317. */
  318. static int am33xx_pm_alloc_sram(void)
  319. {
  320. struct device_node *np;
  321. int ret = 0;
  322. np = of_find_compatible_node(NULL, NULL, "ti,omap3-mpu");
  323. if (!np) {
  324. np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu");
  325. if (!np) {
  326. dev_err(pm33xx_dev, "PM: %s: Unable to find device node for mpu\n",
  327. __func__);
  328. return -ENODEV;
  329. }
  330. }
  331. sram_pool = of_gen_pool_get(np, "pm-sram", 0);
  332. if (!sram_pool) {
  333. dev_err(pm33xx_dev, "PM: %s: Unable to get sram pool for ocmcram\n",
  334. __func__);
  335. ret = -ENODEV;
  336. goto mpu_put_node;
  337. }
  338. sram_pool_data = of_gen_pool_get(np, "pm-sram", 1);
  339. if (!sram_pool_data) {
  340. dev_err(pm33xx_dev, "PM: %s: Unable to get sram data pool for ocmcram\n",
  341. __func__);
  342. ret = -ENODEV;
  343. goto mpu_put_node;
  344. }
  345. ocmcram_location = gen_pool_alloc(sram_pool, *pm_sram->do_wfi_sz);
  346. if (!ocmcram_location) {
  347. dev_err(pm33xx_dev, "PM: %s: Unable to allocate memory from ocmcram\n",
  348. __func__);
  349. ret = -ENOMEM;
  350. goto mpu_put_node;
  351. }
  352. ocmcram_location_data = gen_pool_alloc(sram_pool_data,
  353. sizeof(struct emif_regs_amx3));
  354. if (!ocmcram_location_data) {
  355. dev_err(pm33xx_dev, "PM: Unable to allocate memory from ocmcram\n");
  356. gen_pool_free(sram_pool, ocmcram_location, *pm_sram->do_wfi_sz);
  357. ret = -ENOMEM;
  358. }
  359. mpu_put_node:
  360. of_node_put(np);
  361. return ret;
  362. }
  363. static int am33xx_pm_rtc_setup(void)
  364. {
  365. struct device_node *np;
  366. unsigned long val = 0;
  367. struct nvmem_device *nvmem;
  368. int error;
  369. np = of_find_node_by_name(NULL, "rtc");
  370. if (of_device_is_available(np)) {
  371. /* RTC interconnect target module clock */
  372. rtc_fck = of_clk_get_by_name(np->parent, "fck");
  373. if (IS_ERR(rtc_fck))
  374. return PTR_ERR(rtc_fck);
  375. rtc_base_virt = of_iomap(np, 0);
  376. if (!rtc_base_virt) {
  377. pr_warn("PM: could not iomap rtc");
  378. error = -ENODEV;
  379. goto err_clk_put;
  380. }
  381. omap_rtc = rtc_class_open("rtc0");
  382. if (!omap_rtc) {
  383. pr_warn("PM: rtc0 not available");
  384. error = -EPROBE_DEFER;
  385. goto err_iounmap;
  386. }
  387. nvmem = devm_nvmem_device_get(&omap_rtc->dev,
  388. "omap_rtc_scratch0");
  389. if (!IS_ERR(nvmem)) {
  390. nvmem_device_read(nvmem, RTC_SCRATCH_MAGIC_REG * 4,
  391. 4, (void *)&rtc_magic_val);
  392. if ((rtc_magic_val & 0xffff) != RTC_REG_BOOT_MAGIC)
  393. pr_warn("PM: bootloader does not support rtc-only!\n");
  394. nvmem_device_write(nvmem, RTC_SCRATCH_MAGIC_REG * 4,
  395. 4, (void *)&val);
  396. val = pm_sram->resume_address;
  397. nvmem_device_write(nvmem, RTC_SCRATCH_RESUME_REG * 4,
  398. 4, (void *)&val);
  399. }
  400. } else {
  401. pr_warn("PM: no-rtc available, rtc-only mode disabled.\n");
  402. }
  403. return 0;
  404. err_iounmap:
  405. iounmap(rtc_base_virt);
  406. err_clk_put:
  407. clk_put(rtc_fck);
  408. return error;
  409. }
  410. static int am33xx_pm_probe(struct platform_device *pdev)
  411. {
  412. struct device *dev = &pdev->dev;
  413. int ret;
  414. if (!of_machine_is_compatible("ti,am33xx") &&
  415. !of_machine_is_compatible("ti,am43"))
  416. return -ENODEV;
  417. pm_ops = dev->platform_data;
  418. if (!pm_ops) {
  419. dev_err(dev, "PM: Cannot get core PM ops!\n");
  420. return -ENODEV;
  421. }
  422. ret = am43xx_map_gic();
  423. if (ret) {
  424. pr_err("PM: Could not ioremap GIC base\n");
  425. return ret;
  426. }
  427. pm_sram = pm_ops->get_sram_addrs();
  428. if (!pm_sram) {
  429. dev_err(dev, "PM: Cannot get PM asm function addresses!!\n");
  430. return -ENODEV;
  431. }
  432. m3_ipc = wkup_m3_ipc_get();
  433. if (!m3_ipc) {
  434. pr_err("PM: Cannot get wkup_m3_ipc handle\n");
  435. return -EPROBE_DEFER;
  436. }
  437. pm33xx_dev = dev;
  438. ret = am33xx_pm_alloc_sram();
  439. if (ret)
  440. return ret;
  441. ret = am33xx_pm_rtc_setup();
  442. if (ret)
  443. goto err_free_sram;
  444. ret = am33xx_push_sram_idle();
  445. if (ret)
  446. goto err_unsetup_rtc;
  447. am33xx_pm_set_ipc_ops();
  448. #ifdef CONFIG_SUSPEND
  449. suspend_set_ops(&am33xx_pm_ops);
  450. /*
  451. * For a system suspend we must flush the caches, we want
  452. * the DDR in self-refresh, we want to save the context
  453. * of the EMIF, and we want the wkup_m3 to handle low-power
  454. * transition.
  455. */
  456. suspend_wfi_flags |= WFI_FLAG_FLUSH_CACHE;
  457. suspend_wfi_flags |= WFI_FLAG_SELF_REFRESH;
  458. suspend_wfi_flags |= WFI_FLAG_SAVE_EMIF;
  459. suspend_wfi_flags |= WFI_FLAG_WAKE_M3;
  460. #endif /* CONFIG_SUSPEND */
  461. ret = pm_ops->init(am33xx_do_sram_idle);
  462. if (ret) {
  463. dev_err(dev, "Unable to call core pm init!\n");
  464. ret = -ENODEV;
  465. goto err_put_wkup_m3_ipc;
  466. }
  467. return 0;
  468. err_put_wkup_m3_ipc:
  469. wkup_m3_ipc_put(m3_ipc);
  470. err_unsetup_rtc:
  471. iounmap(rtc_base_virt);
  472. clk_put(rtc_fck);
  473. err_free_sram:
  474. am33xx_pm_free_sram();
  475. pm33xx_dev = NULL;
  476. return ret;
  477. }
  478. static int am33xx_pm_remove(struct platform_device *pdev)
  479. {
  480. if (pm_ops->deinit)
  481. pm_ops->deinit();
  482. suspend_set_ops(NULL);
  483. wkup_m3_ipc_put(m3_ipc);
  484. am33xx_pm_free_sram();
  485. iounmap(rtc_base_virt);
  486. clk_put(rtc_fck);
  487. return 0;
  488. }
  489. static struct platform_driver am33xx_pm_driver = {
  490. .driver = {
  491. .name = "pm33xx",
  492. },
  493. .probe = am33xx_pm_probe,
  494. .remove = am33xx_pm_remove,
  495. };
  496. module_platform_driver(am33xx_pm_driver);
  497. MODULE_ALIAS("platform:pm33xx");
  498. MODULE_LICENSE("GPL v2");
  499. MODULE_DESCRIPTION("am33xx power management driver");